JPS5567817A - Latch circuit - Google Patents

Latch circuit

Info

Publication number
JPS5567817A
JPS5567817A JP14064278A JP14064278A JPS5567817A JP S5567817 A JPS5567817 A JP S5567817A JP 14064278 A JP14064278 A JP 14064278A JP 14064278 A JP14064278 A JP 14064278A JP S5567817 A JPS5567817 A JP S5567817A
Authority
JP
Japan
Prior art keywords
signal
latch circuit
circuit
data
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14064278A
Other languages
Japanese (ja)
Other versions
JPS581810B2 (en
Inventor
Tomoji Nukiyama
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53140642A priority Critical patent/JPS581810B2/en
Publication of JPS5567817A publication Critical patent/JPS5567817A/en
Publication of JPS581810B2 publication Critical patent/JPS581810B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To ensure the high-speed latch and thus to prevent the malfunction caused by the noise signal by supplying for holding the data held at the main latch circuit into the secondary latch circuit after a fixed time.
CONSTITUTION: Main latch circuit 1 reads in the supplied data by the rise voltage level of strobe signal STB, and then holds the data at the specified level changing point. At the same time, secondary latch circuit 2 reads out for holding the output data of circuit 1 in the timing of the signal drawn out via logic circuit 3 which secures the logic product between delay element 4 delaying signal STB, signal STB and its delay signal. In this way, the high-speed latch becomes possible to prevent the malfunction caused by the noise signal.
COPYRIGHT: (C)1980,JPO&Japio
JP53140642A 1978-11-15 1978-11-15 latch circuit Expired JPS581810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53140642A JPS581810B2 (en) 1978-11-15 1978-11-15 latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53140642A JPS581810B2 (en) 1978-11-15 1978-11-15 latch circuit

Publications (2)

Publication Number Publication Date
JPS5567817A true JPS5567817A (en) 1980-05-22
JPS581810B2 JPS581810B2 (en) 1983-01-13

Family

ID=15273410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53140642A Expired JPS581810B2 (en) 1978-11-15 1978-11-15 latch circuit

Country Status (1)

Country Link
JP (1) JPS581810B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937493U (en) * 1982-09-03 1984-03-09 株式会社筑豊製作所 Rolling bearing grease syringe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5937493U (en) * 1982-09-03 1984-03-09 株式会社筑豊製作所 Rolling bearing grease syringe

Also Published As

Publication number Publication date
JPS581810B2 (en) 1983-01-13

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