JPS55109056A - Data process system - Google Patents

Data process system

Info

Publication number
JPS55109056A
JPS55109056A JP1678179A JP1678179A JPS55109056A JP S55109056 A JPS55109056 A JP S55109056A JP 1678179 A JP1678179 A JP 1678179A JP 1678179 A JP1678179 A JP 1678179A JP S55109056 A JPS55109056 A JP S55109056A
Authority
JP
Japan
Prior art keywords
circuit
output
reading memory
address
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1678179A
Other languages
Japanese (ja)
Other versions
JPS648503B2 (en
Inventor
Tetsumasa Ooyama
Ryoichi Shinoda
Toshihiko Tsunoda
Toshihiko Wakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP1678179A priority Critical patent/JPS55109056A/en
Publication of JPS55109056A publication Critical patent/JPS55109056A/en
Publication of JPS648503B2 publication Critical patent/JPS648503B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To realize the alteration of the specifications by securing the operation of several types of function in time division, forming each function with one type of the circuit peripheral to the reading memory circuit and also rewriting the contents of the reading memory circuit.
CONSTITUTION: The address of temporary memory circuit 22 is selected via timing signals 20 and 21, and the contents of the memory device are delivered as output signal 23 of circuit 22. Selection circuit 24 selects input signal 1 and the output signal of selection circuit 25 out of the output signal of circuit 22, and then designates the address of reading memory circuit 26 as well as signals 20 and 21. The conversion table stored in the designated address is delivered in the form of outputs 27∼29 of circuit 26. Then output 27 is stored again into circuit 22 as the input data of circuit 22, and output 28 is supplied to state holding circuit 30. And output 29 is used as the output of the reading memory circuit which is to be the input of state holding circuit 30 respectively.
COPYRIGHT: (C)1980,JPO&Japio
JP1678179A 1979-02-16 1979-02-16 Data process system Granted JPS55109056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1678179A JPS55109056A (en) 1979-02-16 1979-02-16 Data process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1678179A JPS55109056A (en) 1979-02-16 1979-02-16 Data process system

Publications (2)

Publication Number Publication Date
JPS55109056A true JPS55109056A (en) 1980-08-21
JPS648503B2 JPS648503B2 (en) 1989-02-14

Family

ID=11925726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1678179A Granted JPS55109056A (en) 1979-02-16 1979-02-16 Data process system

Country Status (1)

Country Link
JP (1) JPS55109056A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147832A (en) * 1985-12-23 1987-07-01 Kokusai Electric Co Ltd Frame synchronization method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62147832A (en) * 1985-12-23 1987-07-01 Kokusai Electric Co Ltd Frame synchronization method

Also Published As

Publication number Publication date
JPS648503B2 (en) 1989-02-14

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