JPS55109057A - Data transmission device - Google Patents

Data transmission device

Info

Publication number
JPS55109057A
JPS55109057A JP1678279A JP1678279A JPS55109057A JP S55109057 A JPS55109057 A JP S55109057A JP 1678279 A JP1678279 A JP 1678279A JP 1678279 A JP1678279 A JP 1678279A JP S55109057 A JPS55109057 A JP S55109057A
Authority
JP
Japan
Prior art keywords
circuit
output
reading memory
address
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1678279A
Other languages
Japanese (ja)
Other versions
JPS6031374B2 (en
Inventor
Tetsumasa Ooyama
Ryoichi Shinoda
Toshihiko Tsunoda
Toshihiko Wakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP54016782A priority Critical patent/JPS6031374B2/en
Publication of JPS55109057A publication Critical patent/JPS55109057A/en
Publication of JPS6031374B2 publication Critical patent/JPS6031374B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To secure the flexible countermeasure to the alteration of the specifications by giving the operation to several types of functions in time division and based on the memory contents of the reading memory circuit and then rewriting the memory contents.
CONSTITUTION: The address of temporary circuit 22 is selected via timing signals 20 and 21, and the contents are delivered as output signal 23. Selection circuit 24 selects the output signal of selection 25 via input terminal 1 and output signal 23, and then designates the address of reading memory circuit 26 as well as timing signals 20 and 21. Then the conversion table of the designated address is delivered in the form of outputs 27∼29 of the reading memory circuit. Output 27 is stored again into circuit 22 as the input data, and output 28 is supplied to state holding circuit 30 to be used as output terminal 13 and display output 15. Also output 29 is used as the output of the reading memory circuit which is to be the input of circuit 30 respectively.
COPYRIGHT: (C)1980,JPO&Japio
JP54016782A 1979-02-16 1979-02-16 data transmission equipment Expired JPS6031374B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54016782A JPS6031374B2 (en) 1979-02-16 1979-02-16 data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54016782A JPS6031374B2 (en) 1979-02-16 1979-02-16 data transmission equipment

Publications (2)

Publication Number Publication Date
JPS55109057A true JPS55109057A (en) 1980-08-21
JPS6031374B2 JPS6031374B2 (en) 1985-07-22

Family

ID=11925751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54016782A Expired JPS6031374B2 (en) 1979-02-16 1979-02-16 data transmission equipment

Country Status (1)

Country Link
JP (1) JPS6031374B2 (en)

Also Published As

Publication number Publication date
JPS6031374B2 (en) 1985-07-22

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