JPH0432922A - Interface control circuit - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of a CPU by generating an interrupt signal to a CPU for a first time when held data in a holding means which stores and holds data in order reaches a specific value and processing the held data by the CPU successively in response to the interruption signal. CONSTITUTION:A data significance signal (b) for receiving the data from an external device is sent out to a timing control circuit 3 and the received data is sent out as a data signal (a). The timing control circuit 3 sends a write signal (d) at the timing of the transmission of the significance data as the data signal (a) to write the data in an FIFO 4 and makes an internal accumulator count up by one. When the value in the accumulator reaches a certain value, the timing control circuit 3 judges that the FIFO 4 is saturated and sends an inter ruption signal (f) to the CPU 5, which reads data out successively in constant units. Consequently, the overhead time of interruption processing in read processing per byte by the CPU is shortened and the performance of the CPU is improved apparently.

Description

TECHNICAL FIELD The present invention relates to an interface control circuit, and more particularly to a control circuit for an interface for communication between information processing devices.

2. Description of the Related Art In general, there are two types of interface circuits: one using a parallel transfer method and one using a serial transfer method.

Conventionally, this type of interface circuit has been used in printer devices, etc., and in the so-called Centronics specification interface, which is a specification for parallel transfer, transfer data is received based on a predetermined procedure, and the transfer data is It was controlled to notify the CPU of the presence of received data. In addition, in the interface of serial transfer specifications, for example, the well-known R3232C specification, the receiving circuit accumulates the data received one bit at a time, and notifies the CPU that there is received data every time one word is generated. It was controlled like that.

In other words, the conventional interface circuit described above generates an interrupt to the CPU every time one word is received or generated, and the CPU reads, edits, and stores one word in one interrupt process. That's what I was doing. In this case, the processing time required for internal processing of CPυ in the interrupt processing routine, that is, for saving or loading the program counter and other general-purpose registers, is long. Therefore, the method of processing every word has the disadvantage that the CPU is not used efficiently, and especially when the data transfer rate from an external device increases, the time required for the CPU to perform reception processing increases, resulting in an apparent deterioration in performance. Ta.

OBJECT OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to improve the efficiency of CPU usage,
An object of the present invention is to provide an interface control circuit that can improve its apparent performance.

Structure of the Invention The interface control circuit according to the present invention includes a holding means for sequentially accumulating and holding data divided into predetermined data units and transferred from a host device, and a data processing means for receiving and processing the held data. an interface control circuit comprising: means for generating an interrupt signal to the data processing means when the amount of data held in the holding means reaches a predetermined amount (excluding one data single position); The data processing means is configured to continuously read out the held data in response to the interrupt signal.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an interface control circuit according to the present invention.

In the figure, 1 and 2 are receiving circuits that convert received data from an external device such as a host computer into an internal data format. 1 is a serial/parallel conversion circuit that converts serial data into parallel data, and 2 is a parallel data receiving circuit. Note that these two circuits are usually used alternatively.

Reference numeral 4 denotes a first-in first-out register (hereinafter abbreviated as FIFO), which sequentially holds and accumulates one byte worth of data based on the data signal from the serial/parallel conversion circuit 1 or the parallel reception circuit 2. Its output is connected to data bus e. In addition, this FIFO 4 is composed of well-known D-type flip-flops (D-PP) connected in multi-stage cascade, and all D to
When the held value of 1 to 12 is "0", a FIFO Empty signal g indicating that it is empty is sent to the CPU 5. Furthermore, the timing of writing to the FIFO 4 is determined by the write signal d from the timing control circuit 3.

The timing control circuit 3 has an accumulator (not shown) inside, and the accumulator (counter) receives the data valid signal C from the serial/parallel converter circuit 1 or the data valid signal C from the parallel receiving circuit 2. It is incremented by 1 in response to .

Furthermore, when the value of the accumulator reaches a predetermined value, which will be described later,
An interrupt signal f is sent to the CPU 5. Note that the value of the accumulator is reset by inputting a data counter reset signal i from the CPU 5.

The CPU 5 receives an interrupt signal f from the timing control circuit 3.
The interrupt processing routine is started in response to human input from the FIF.
Data held in OJ is transferred to FIFO via data bus e.
The data is read out and written into the memory 6 faster than the data retention speed in the memory 4. Note that h is an address to the memory 6.

In such a configuration, when the parallel receiving circuit 2 is currently selected and receives data from an external device (not shown), it sends a data valid signal to the timing control circuit 3, and sends out the received data as a data signal a. do. Then, the timing control circuit 3 sends out a write signal d at the timing when valid data is sent to the data signal a, and writes it into the FIFO 4.
and increments the internal accumulator by 1.

Here, the capacity of FIFO 4 is M bytes, and when the value of the accumulator reaches a certain value, the timing control circuit 3
It is assumed that the IFO4 is determined to be in a saturated state and an interrupt signal f is sent to the CPU5.

When the CPU 5 receives the interrupt signal f, it executes the interrupt process as shown in FIG.

FIG. 3 is a flowchart showing the interrupt processing procedure.

In the figure, at the beginning of interrupt processing (INTIn; Int
errupt ln), the data held in the internal register of the CPU 5 is stored in the reserved area of the memory 6 (step 31).

Next, 1 byte of the contents of the FIFO 4 is read (step 32), and the CPU 5 performs editing processing as appropriate according to the attributes of this data (step 33). This is control data,
This is a process of converting character data etc. into a predetermined format depending on the type.

The data after the editing process is stored in the memory 6 (step 3
4). Next, the CPU 5 checks the signal g to determine whether the FIFO 4 is empty or not.
5) If it is not empty, read data from FIFO4 again and perform the same process (steps 35→32→33...
).

On the other hand, if it is empty, the accumulator of the timing control circuit 3 is reset by the signal i (step 36), and the data stored in the internal register stored in the memory 6 is restored to the original state (step 37). ), ends the interrupt processing (INT Ret; InterruptL Re
turn).

Further, FIG. 2 is a time chart showing the relationship between the content capacity of FIFO 4 and the reading time of 81L. In the figure, time 0
The data held in FIFO 4, whose content capacity was 0 bytes, reaches L after one hour, and is determined to be in a saturated state by the accumulator described above. At this time, an interrupt signal f is sent to the CPU 5.

When the CPU 5 receives the interrupt signal f, it is unknown what kind of processing it is performing, and it starts reading data from the FIFO 4 after a lapse of time dT. However, since data is sequentially held and accumulated in the FIFO 4, the CPU 5 finishes reading the FIFO 4 after X time has elapsed.

Here, the reason why the value determined to be saturated is smaller than the capacity M of the FIFO 4 is because the time dT changes depending on the state of the CPU 5 at the time of the interrupt. Details will be described later.

When the FIFO 4 becomes empty, the signal g is sent out and the CPU 5 finishes reading the data, so that the amount of data in the FIFO J starts to increase again.

In other words, conventionally, each time a byte of data was received, the CPU
In contrast, in this embodiment, a FIFO is provided in the interface circuit, and the saturation state of the FIFO is detected and data is read out continuously in certain units of 2 bytes or more. That's what we're doing. As a result, the overhead of interrupt processing in read processing per byte of the CPU is reduced from several hundreds to 1
This apparently improves the performance of the CPU.

Furthermore, since FIFO is used in this embodiment, there is no need to specify an address, and the time required to import received data into the device can be shortened. Therefore, the time spent waiting for the external device can also be shortened. In addition,
If you don't mind complicated control, you can use memory.

Next, the relationship between the FIFO capacity M and the value shown in FIG. 2 will be explained. First, one reception causes FI
Assume that the data held in the FO is N words. That is, in the above-described embodiment, it is 1 word - 1 byte. That is,
The relationship between M and L is LXN<M. Note that L must be 2 or more. This is because the processing in L-1 is the same as the conventional processing.

Further, L needs to be determined according to the read speed of the CPU. In other words, as mentioned earlier, F
Since data is held and accumulated in the IFO, ML must be larger than the maximum time value from when an interrupt occurs until the CPU actually starts reading. Otherwise, the FIFO will become banked. Sunao) Chi,
It is sufficient to determine L according to the maximum value of time dT in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, an interrupt signal is generated to the CPU only when the held data reaches a predetermined value in the holding means that sequentially accumulates and holds data, and the CPU does not respond to this interrupt. Since the configuration is such that the retained data is continuously read and processed in response to a signal, the CPU
This has the effect of significantly reducing interrupt processing and significantly reducing CPU overhead, thereby improving CPU usage efficiency and improving its apparent performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an interface control circuit according to an embodiment of the present invention, FIG. 2 is a time chart showing the relationship between FIFO content capacity and read time, and FIG. 3 is a flow chart showing the interrupt processing procedure. be. Explanation of symbols of main parts

Claims (1)

[Claims] (1) An interface control circuit including a holding means for sequentially accumulating and holding data divided into predetermined data units and transferred from a host device, and a data processing means for receiving and processing this held data. means for generating an interrupt signal to the data processing means when the amount of data held in the holding means reaches a predetermined amount (excluding one data single position); An interface control circuit characterized in that the held data is continuously read out in response to an interrupt signal.