JP2823625B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (FIGS. 8 to 10) Problems to be solved by the invention Means for solving the problems Principle explanatory diagram (FIG. 1) Operation Example Block diagram of the embodiment (FIG. 2) Storage state of the memory (FIG. 3) Block diagram of the detailed embodiment (FIG. 4) State transition diagram (FIG. 5) Timing chart of the detailed embodiment (FIG. 6) The memory storage state of the detailed embodiment (FIG. 7) Effect of the Invention [Overview] The present invention relates to a data processing device that performs direct memory access transfer processing inside the device, and particularly to a data processing device that processes undefined length block data. In a data processing device for performing direct memory access transfer of block data, an object of the present invention is to provide a data processing device in which the use efficiency of a buffer area is increased and data processing is simple. And a direct memory access control unit for performing direct memory access transfer of data, in the data processing device, wherein the memory has a storage unit having a continuous storage area for storing a plurality of undefined length block data, An area information storage unit that stores area information indicating an occupied area of each undefined-length block data stored in a storage unit, wherein the direct memory access control unit stores the undefined-length block data in a continuous It is configured to include a continuous area transfer control unit for transferring to an area.

[Industrial applications]

The present invention provides direct memory access (DM
A) The present invention relates to a data processing device that performs a transfer process, and more particularly, to a data processing device that processes undefined-length block data.

In a data processing device that processes indefinite-length block data, data to be processed may be temporarily stored in a memory by DMA transfer. The temporarily stored undefined-length block data group needs to be processed later for each undefined-length block data unit. Therefore, it must be stored in the memory so that it can be recognized in units of each undefined length block data.

(Conventional example)

FIG. 8 shows a schematic block diagram of a conventional data communication device.

The data communication device 50 receives the data serially transferred from the outside and performs a serial / parallel conversion (hereinafter, referred to as S / P conversion). The reception unit 9 converts the data into parallel data. A DMA control unit 51 for controlling data to be transferred by DMA; a CPU 10 for controlling the entire data communication device 50; a data bus 3 for transferring data; and an address bus for transferring address information 4
And a memory 52 for storing data.

The memory 52 includes a reception buffer unit 53 for temporarily storing reception data, and a descriptor unit 54 for indicating a storage state in the reception buffer unit 53.

As shown in FIG. 9, the reception buffer unit 53 includes a plurality of reception buffers BF ₁ , BF ₂ ,..., BF _n each having an area of the maximum length of the undefined-length block data transferred at _one time.

As shown in FIG. 9, the descriptor section 54 includes pointer sections P ₁ , P ₂ ,..., P _n for specifying a reception buffer and size sections S ₁ , S ₂ ,.
A plurality of descriptors DE ₁ , DE ₂ ,..., DE _n having S _n are provided, and each descriptor corresponds to each reception buffer on a one-to-one basis.

Here, the data format of the undefined-length block data handled by the data processing device is HDLC (High lebel Dat
a Link Control procedure) frame format data will be described as an example.

One frame in HDLC includes, for example, as shown in FIG. 10, a 1-byte start flag indicating the start of a frame,
One or two bytes used to designate one or more secondary stations or one composite station to receive the control information to be described later, or to indicate the secondary station or composite station reporting the executed operation or status. Address information, 1- or 2-byte control information used for an operation command to the partner station or a response to the command, transfer data of an undefined length having a predetermined maximum length, and a 2-byte frame for bit error detection It is provided with a check sequence and a 1-byte end flag indicating the end of data.
As described above, since the maximum length of the transfer data is data of an undefined length, the frame itself is also block data of an undefined length.

Next, the operation will be described. Here, it is assumed that the reception data D ₁ and the reception data D ₂ are already stored in the first reception buffer BF ₁ and the second reception buffer BF ₂ , respectively.

When receiving serial data from the outside, the receiving unit 9 converts the serial data into parallel data and issues a transfer request to the DMA control unit 51. D
When the MA control unit 51 receives the request, the MA control unit 51 returns to the pointer unit P ₃ of the third descriptor DE ₃ corresponding to the third reception buffer BF _{3 (} not shown), which is a reception buffer in which data has not yet been stored in the descriptor unit 54 of the memory 52. The stored address is read via the address bus 4 and the pointer section is read.
Transfers the received data via the data bus 3 to the third reception buffer BF ₃ present in the address indicated by P _3. Transfer writes the number of bytes of the received data transferred to the size portion S ₃ of the third descriptor DE ₃ Upon completion. Hereinafter, the same operation is performed every time the variable-length data is received.

[Problems to be solved by the invention]

In the conventional data processing device, an unused empty area in which data is not written in each reception buffer is not used. Therefore, even if the total empty area of each reception buffer area is larger than the maximum data length of the undefined-length block data, these areas cannot be used, resulting in useless areas, and unnecessarily securing the reception buffer area. There was a problem that had to be.
In addition, since each variable-length block data is stored in a discontinuous area, access to the control unit becomes complicated when a similar process is performed on a plurality of variable-length block data. was there.

Accordingly, an object of the present invention is to provide a data processing device that performs DMA transfer of block data of indefinite length, which increases the efficiency of use of a buffer area and provides a simple data processing device.

[Means for solving the problem]

 FIG. 1 shows a principle configuration diagram of the present invention.

The data processing device 1 includes a DMA control unit 2 for performing DMA transfer of data, a data bus 3 for transferring data, an address bus 4 for transferring addresses, and a memory 5 for storing data. .

The DMA control unit 2 includes a continuous area transfer control unit 6 for sequentially transferring the indefinite length block data to a continuous area of the storage unit of the memory.

The memory 5 includes a storage unit 7 having a continuous storage area for storing a plurality of undefined-length block data, and an area information storage unit 8 for storing area information indicating an occupied area of the undefined-length block data stored in the storage unit. It is configured.

[Action]

When receiving a data transfer request from the outside, the DMA control unit 2 instructs the continuous area transfer control unit to transfer data. The continuous area transfer control unit 6 is a memory area information storage unit 8
Reads the area information I _n from the n-th storage portion on the basis thereof
Stored in the area A _n. When the storage of the data is completed, the continuous area transfer controller first continuous to the n region A _n (n + 1)
Stores storage information I _{n + 1,} which means an area A _{n + 1} in the area information storing section 8. When an external data transfer request is issued to the DMA control unit 2 again, the continuous area transfer control unit 6 reads out the area information In _{+ 1} , which means the (n + 1) th area, of the area information storage unit 8, and _Is stored in the (n + 1) th area An.

Therefore, a plurality of data are successively stored in the storage unit 7 of the memory 5.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

FIG. 2 shows a block diagram of an embodiment of the present invention. The same parts as those in the conventional example shown in FIG. 8 are denoted by the same reference numerals, and detailed description is omitted.

8 is different from the conventional example of FIG. 8 in that a common reception buffer 12 for storing received data in a continuous area in the memory 11 and a frame information table 13 for recording storage information of the stored received data are provided. 3 is provided with a continuous area transfer control unit 6 for storing data in a continuous area.

FIG. 3 shows a schematic configuration of the common reception buffer 12 and the frame information table 13.

The frame information table 13 includes a plurality of head address parts H ₁ , H ₂ ,
… And status parts C ₁ , C ₂ ,
.., And the start address part and the status part are paired _one by _one , and the descriptors DE ₁ , D
E ₂ ,...

Next, the operation will be described. It is assumed that no data is stored in the common reception buffer 12 in the initial state.

When receiving section 9 receives the received data, it requests DMA control section 2 to transfer the data. Continuous area transfer controller 6 of the DMA controller 3 reads the top address unit H ₁ of the first descriptor DE _1, the address indicated by the top address unit H ₁ as the start address, the received data while increasing the address Transfer one byte at a time.

Continuous and the received data D ₁ finishes transfer area transfer control section 6
It writes the status information of the presence of valid data in the status section C ₁ of the first descriptor DE _1, further top address unit
Writes the destination address of the data received in the H _1. Thereafter, the DMA control unit 2 enters a transfer request waiting state. After that,
The same operation is performed for each data transfer request.

A more detailed embodiment of the present invention will be described with reference to FIGS.

The same parts as those in the embodiment of FIG. 2 are denoted by the same reference numerals, and detailed description is omitted.

The data communication device 100 includes a receiving unit 9 that performs S / P conversion of serial data transmitted in a frame format from the outside,
DMA of parallel data converted by S / P in receiving unit 9 to memory
DMA controller 2 for transferring data, CPU 10 for processing received data and controlling the entire device, and memory 11 for storing data
And a data bus 3 for transferring data within the data communication device, and an address bus 4 for transferring addresses. In the following, the description will be made assuming that an 8-bit data bus and a 24-bit address bus are provided.

The memory 11 includes a common reception buffer 12 having a continuous area for writing received frame data, and a frame information table 13 for writing boundary information indicating a boundary between storage areas of each frame data.

The receiving unit 9 includes three shift registers 14, 15, and 16, a detection control unit 17 that performs flag detection and zero deletion control, and a CRC (Cyclic Redundancy Check) added to the received data.
It comprises a CRC checker 18 for checking a code error and a reception FIFO (First In First Out) 19 used as a buffer for preventing overflow of received data.

The shift register 14 and the detection control unit 17 cooperate to detect the start flag and the end flag of the received data and to control the automatic insertion of zeros.

The shift register 15 and the shift register 16 prevent the CRC code from being taken into a reception FIFO described later.

The receiving unit control circuit 20 includes a signal generating circuit (not shown) for generating a state notification signal EOF for notifying the state of the receiving unit 9 to the DMA control unit 2 and a DMA transfer request signal DRQ.

The DMA control unit 2 receives the status notification signal EOF from the receiving unit 9 and
It is configured to include a DMA control unit control circuit 21 that executes a DMA transfer operation by making a state transition by a DMA transfer request signal DRQ, and a DMA register unit 22 that stores various data.

The DMA register unit 22 includes three 8-bit registers DP each storing an information write address of the frame information table 13.
R (L), DPR (M), DPR (H) (hereinafter, when these three registers are treated as one register, DPR
(L, M, H). ) And three 8-bit registers ADDR (L) for storing addresses to write data,
ADDR (M) and ADDR (H) registers (hereinafter, when these three registers are treated as one register, ADDR
(L, M, H). ) And two registers BCR (L) and BCR for storing the remaining number of bytes in the reception buffer.
(H) (hereinafter, when these two registers are treated as one register, they are expressed as a register BCR (L, H)).

In the following description, the register DPR (L,
M, H) are incremented and updated each time data is written to the frame information table.
(L, M, H) is incremented and updated every time the reception data is completely written into the buffer.
The BCR (L, H) is decremented and updated each time the received data is written to the buffer.

Next, the operation of the DMA control unit 2 when receiving undefined-length block data in the frame format will be described with reference to the state transition diagram of FIG.

DMA controller 2 in a stopped state C _1, the state notification signal EOF is inverted state (i.e., when the EOF = "L", a transition to the data wait state C _2. Then, DMA transfer request signal DRQ is outputted Then, the DMA control unit 2 transits to the data transfer state C _3. Thereafter, when the data transfer is completed, the DMA control unit 2
Transitions back to the data wait state C _2. DMA control unit 2 further inverts the state signal EOF in the data wait state C ₂ becomes "H", a transition to the table write state C ₄ to write the transferred data in the table. Then, after the table write end, a transition to the stop state C _1. Thereafter, the same operation is repeated.

Next, the detailed operation of the DMA control unit 2 when receiving the undefined-length block data in the frame format will be described with reference to the timing chart of FIG.

First, as an initial setting, the DMA register 22
Is written in the register DPR (L, M, H) of the frame information table where the frame information is to be stored, and is written in the register ADDR (L, M, H). Including start address HOB
Is written, and the total number of bytes of the usable area, that is, the total number of bytes of the common reception buffer is written in the register BCR (L, H).

At time t _1, when the start flag of the received frame format data is detected by the receiver 9, a state notification signal EOF becomes "L", DMA control unit 2 is a data wait state C ₂ from the stop state.

Thereafter, when the first data is the flag detection and zero deletion is performed by the register 14 and the detection control unit 17, is input to the receiving FIFO19 through the register 15 and the register 16, the receiving section 9 at time t ₂ is DMA By setting the transfer request signal DRQ to “H”, the DMA control unit control circuit 21 of the DMA control unit 2
A Make a transfer request. This causes the DMA control unit control circuit 21 to make a state transition from the data waiting state to the data transfer state.

Then DMA controller control circuit 21 at time t ₃ is set to "H" bus request signal HRQ, to request the bus right to CPU 10.

At time t _4, CPU 10 is in "H" of the bus grant signal HACK to a request bus. At the same time, the DMA control unit 2 sets the bus control signal IRD to “H” and sets the register ADDR (L,
M, H) to the storage start address HOB of the reception buffer area
Is output to the address bus. Further, the DMA control unit 2 sets the memory write signal MWR to "H" to put the memory in a memory writable state.

DMA controller control circuit 21 at time t ₅ is set to "H" DMA transfer acknowledge signal DACK, indicating receipt of the DMA transfer request to the receiving unit 9. Further, the bus control signal IRD is set to “L”.
And receive data, that is, first data, in the receive FIFO 19
requesting to output the d ₁ to the data bus 3. Thus the data bus 3 first data d ₁ in the frame data received in the receiving FIFO19 is outputted.

DMA controller at time t ₆ is a memory write signal MWR "L"
To to to transfer data that is output to the data bus 3, i.e. in the region of the common receive buffer 12 corresponding to the first data d ₁ to store the start address of the memory 11 (HOB).

DMA controller control circuit at the time t ₇ 21 to "L" transfer request acknowledge signal DACK. The DMA control unit 2 sets the bus control signal IRD to "H" and sets the memory write signal MWR to "H".

At time t _8, DMA controller control circuit 21 to relinquish the bus in the "L" the bus request signal HRQ. Further, the register ADDR (L, M, H) and the register BCR (L, H) are updated, and a data waiting state is set.

At time t _9, CPU10 is the bus right acknowledge signal HACK "L"
To

Thereafter, when a new DMA transfer request signal DRQ data transfer request is issued from the receiving unit 9, the above operation is repeated, and the addresses (HOB + 1), (HOB + 2),.
-1), the second data d ₂ , the third data d ₃ ,.
Transferring the N data d _N. Thus, the above operation is repeated until the receiving unit 9 detects the end flag, and the data transfer is performed.

Upon detecting the end flag at the receiving section 9 at time t _10, a state signal EOF becomes "L", DMA control unit 2 shifts the table write state.

At time t _11, DMA controller control circuit 21 automatically to CPU10 to "H" the bus request signal HRQ to request the bus right.

At time t _12, CPU10 is the bus right acknowledge signal HACK "H"
To As a result, the DMA control unit 2 sets the bus control signal IRD to “H”, and registers the register DPR (L, M,
H), the storage start address (HOT) of the frame information table read out is output. At the same time, the memory write signal MWR is set to “H” to make the memory writable.

At time t _13, DMA controller control circuit 21 outputs 1 hexadecimal, namely, the "01H" to the data bus 3. This “01H” is a status indicating that the head address portion of the written descriptor is valid.

At time t _14, DMA controller address indicated the "01H" in HOT, i.e., the status unit shown in FIG. 7
It is written in C _1.

At time t _15, DMA controller to "H" MWR.

At time t _16, DMA controller to relinquish the bus in the "L" the bus request signal HRQ.

At time t _17, CPU10 is the bus right acknowledge signal HACK "L"
To

At time t _18, DMA controller control circuit 21 again automatically to CPU10 to "H" the bus request signal HRQ to request the bus right.

At time t _19, CPU10 is the bus right acknowledge signal HACK "H"
To As a result, the DMA control unit sets the bus control signal IRD to “H”.
And the leading end address (HOT + 1) of the information table read from the register DPR (L, M, H) on the address bus.
Is output. At the same time, the memory write signal MWR is set to “H” to make the memory writable.

At time t _20, DMA controller control circuit 21 outputs the contents of register ADDR (L) to the data bus 3.

At time t _21, DMA controller control circuit 21 is a register AD
The contents of DR (L) are stored in the frame information table 13 (HOT)
Write to the address indicated by.

At time t _22, DMA controller control circuit 21 to "H" memory write signal MWR.

At time t _23, the request signal HRQ for DMA control unit bus
To “L” and abandon the bus right.

At time t _24, CPU is in the "L" of the bus acceptance signal.

Hereinafter, the same processing as the processing from time t18 to t24 is repeated,
Address (HOT + 2), (HOT + 2) of frame information table 13
+3) to register ADDR (M) and register ADDR respectively
Write the contents of (H). Start address in the common receiving buffer 12 of the frame format data to the top address unit H ₁ shown in FIG. 7 in this manner so that the are stored.

Then, DMA controller 2 at time t ₂₅ is stopped.

As described above, each time the data in the frame format is received, the above series of operations is repeated.

FIG. 7 shows a state of the frame information table 13 and the common reception buffer 12 of the memory 11 after receiving the _second frame format data D2. Hatched portion already data indicates the region which is written the leading address of the area of the common receive buffer 12 should then frame format data to the top address unit H ₂ is stored is stored by the DMA controller 2 ing. Also, the status part C _3, remains still indicating that data is not being transferred "00H" is written.

As described above, the data of each frame format can be stored in a continuous area of the common reception buffer 12, and the information of the frame information table 13 allows the CPU to recognize the boundary of the data of each frame format. It is.

In the above embodiment, the next undefined-length block data is stored in an area starting from the address of the last address + 1 of the already-stored undefined-length block data. However, the final address + N (N is It is also possible to store the next undefined-length block data in an area having an address of (positive integer) as the start address. However, in this case, it is desirable that N is small in order to reduce unnecessary empty areas.

Further, in this embodiment, the head address of the area where the data of each frame is stored is used as the area information. However, the same effect can be obtained by using the number of bytes of each storage area.

〔The invention's effect〕

As described above, according to the present invention, since undefined-length block data can be stored in a continuous area in the storage unit, useless free space can be reduced, and the use efficiency of the storage unit can be improved. it can.

In addition, by storing the undefined-length data in a continuous area, the access processing is simplified when the CPU performs the same processing on each undefined-length block data.

[Brief description of the drawings]

 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a memory storage state of the embodiment of FIG. 2, and FIG. 5 is a state transition explanatory diagram of the embodiment of FIG. 4, FIG. 6 is a timing chart of the embodiment of FIG. 4, and FIG. 7 is a diagram of a memory of the embodiment of FIG. FIG. 8 is a block diagram of a conventional example, FIG. 9 is a diagram of a conventional memory, and FIG. 10 is an explanatory diagram of an HDLC data format. DESCRIPTION OF SYMBOLS 1 ... Data processing apparatus 2 ... DMA control part 3 ... Data bus 4 ... Address bus 5 ... Memory 6 ... Continuous area transfer control part 7 ... Storage part 8 ... Area information storage part 9 ... Reception Unit 10 CPU 11 Memory 12 Common receive buffer 13 Frame information tables 14, 15, 16 Shift register 17 Detection control unit 18 CRC checker 19 Receive FIFO 20 Receive Block control circuit 21: DMA control block control circuit 22: DMA register block

Claims (1)

(57) [Claims] 1. A data processing device comprising: a memory (5); and a direct memory access control unit (2) for performing direct memory access transfer of data, wherein the memory (5) stores a plurality of indefinite-length block data. Storage unit having a continuous storage area for storing (7, 12)
And area information (I _n ) indicating an occupied area (A _n , A _{n + 1} ) of the indefinite-length block data (D ₁ , D ₂ , D ₃ , D ₄ ) stored in the storage units (7, 12). , In _{+ 1} ), and the direct memory access control unit (2) stores the indefinite-length block data in a continuous area of the storage unit (7, 12). A data processing device comprising a continuous area transfer control unit (6) for transferring data to a data transfer device.