JPH0353736A - Reception buffer control system - Google Patents

Abstract

PURPOSE:To attain the data transfer without interrupting a midway data transfer by detecting it that a reception buffer residual quantity is a specified value or below and implementing the acquisition processing of the succeeding reception buffer in advance. CONSTITUTION:An address counter of a DMA control circuit 14 is counted up, a range counter is counted down and a transfer buffer residual quantity detection circuit 13 is counted down at every DMA transfer between a general- purpose receiver/transmitters(URT) 17, 18, 19, 20 and a memory section 4, and when the transfer buffer residual quantity detection circuit 13 detects the end of transfer by a byte number being a half of the reception buffer length, a LA control circuit 15 receives an instruction, a succeeding reception buffer address is set to an address register 11 and a reception buffer length is set to a range register 12 via a data bus 51. Thus, the transfer of the data from the URT 17, 18, 19, 20 to the memory section 4 is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reception buffer control method in a communication control device.

[Conventional technology]

In conventional communication control devices, in order to transfer the received data from the line to the memory unit, the start address and receive buffer length of the receive data buffer are set in a register in the line control unit at the time of starting the receive operation. This happened when the remaining capacity of the receive buffer during transfer became zero.

[Problem to be solved by the invention]

In the conventional communication control device described above, when the received data is larger than the receive data buffer length, the receive buffer 7
The transfer operation from the line control unit to the memory unit is interrupted until it is detected that the remaining capacity is zero, the next receive buffer is secured, and the data is stored in the address register and range register. This has the disadvantage that overruns are likely to occur.

[Means to solve the problem]

The configuration of the reception buffer control method of the present invention is such that a communication control device including a processor section, a higher-level interface section, a line control section, and a memory section controls the start address of a plurality of reception data buffers and the reception buffer. It has an address register and a range register that store the length, and a transfer buffer remaining amount detection circuit that indicates the remaining amount of the receive buffer during transfer from the line control section to the memory section, and the remaining amount of the receive buffer during transfer is a specified value. When the following is detected, the next receive buffer is secured and stored in the above address register and range register, and when the remaining capacity of the receive buffer during transfer is detected to be zero, the above address receiver indicating the next receive buffer is The present invention is characterized in that the contents of the star and range registers are used to continue the transfer from the line control unit to the memory unit, and the communication control device consists of a processor unit, a higher-level interface unit, a line control unit, and a memory unit. means for temporarily storing the receive buffer length added to the received data, means for holding multiple start addresses and receive buffer lengths of the received data huffer secured by performing the process of securing the receive buffer, and a means for temporarily storing the receive buffer length added to the received data; A means for comparing the added receive buffer length and the secured receive buffer length until the sum of the receive buffer length added to the received data and the secured receive huffer length is equal or the receive buffer length is smaller. It has means for securing a reception buffer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention.

The line control unit 1 includes an address register 11, a range register 12, a transfer buffer remaining amount detection circuit 13, a DMA control circuit 14, an LA control circuit 15, an LA data register 16, and a general-purpose receiver/transmitter (URT) 17.18.
, 19.20.

The processor section 2 is a block that controls the entire communication control device, the upper bus interface section 3 is a block that controls the interface between the communication control device and the upper host computer, and the memory section 4 is a block that controls the communication control device. This is a memory in which control tables and transmission data/reception data are stored.

The address registers 11 are four registers that store the start addresses of the transmit and receive buffers assigned to the memory section, and the range registers 12 are four registers that store the buffer lengths of the transmit and receive buffers. The transfer buffer remaining amount detection circuit 13 is set to a value of 172, which is the buffer length to be transferred at the start of DMA transfer, and counts down every time a transfer is performed with the memory section, and the transfer of 1/2 the number of bytes of the buffer length is completed. This is a circuit that detects when something happens.

The DMA control circuit 14 is a control circuit including a reception address counter and a range counter for directly transferring data between the memory section 4 and the LA data register 16 via the data bus 5l without going through the processor section 2.

The LA data register 16 is a data buffer circuit that temporarily stores parallel data of the general-purpose receiver/transmitter (URT) 1 7.1 8, 1 9.2 0.

General purpose receiver/transmitter (URT) 17, 18,
19.20 is a general-purpose receiver/transmitter that converts serial data from a line into parallel data and detects transmission control characters.

The operation of such a configuration will be explained below.

The address bus 52 is connected to the address bus 52 by the upper bus interface section 3.
Firmware for controlling the communication control device is stored in the memory section 4 via the data bus 51.

A reception command is issued by the host computer, transferred to the memory section 4 through the host interface section 3 and the data bus 5l, and decoded by firmware stored in the memory section 4. LA control circuit 15, URT17
, 18, 19, 20 and the DMA control circuit 14 are initialized using files stored in the memory section 4 and the processor section 2, thereby making it possible to receive data from the line.

At the time of initial setting, the start address and receive buffer length of the receive buffer stored in the memory section 4 are determined by the data bus 51.
, address register 11, and range register l2 to the address counter and range counter in the DMA control circuit l4.

At the same time, the number of bytes that is 1/2 of the value of the range register l2 is set in the transfer buffer remaining amount detection circuit 13.

When the receive data is received from the line, the serial data is
It is converted into parallel data by RT17, 18, 19.20 and sent to LA data register 16,
Data is written via the data bus 51 to the receive buffer address given by the address bus 52, which is the address of the output receive buffer of the address counter in the DMA control circuit l4.

In this way, each time a DMA is transferred between the URT 17, 18, 19, 20 and the memory section 4, the address counter of the DMA control circuit 14 is counted up, the range counter is counted down, and the transfer buffer remaining amount detection circuit 13 is counted down. let Buffer remaining amount detection circuit 1 during transfer
3, when it detects that the transfer of 1/2 bytes of the receive buffer length has been completed, it issues an instruction to the LA control circuit 15.
The A control circuit 15 sets the next reception buffer address in the address register 11 and the reception buffer length in the range register 12 through the data bus 51 through the address bus 52.

When the range counter of the DMA control circuit l4 reaches zero, instead of securing the start address and length of the receive buffer stored in the memory unit 4,
The DMA control circuit 14 uses the start address and receive buffer length of the receive buffer set in the address register l1 and range register 12, which have been secured by detecting the completion of transfer of 1/2 bytes of the receive buffer length. By setting the address counter and range counter, the data from the URTs 17, 18, 19, and 20 are continued to be transferred to the memory section 4 via the LA bus 53, LA data register 14, and data bus 5l.

Next, the second invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of the second invention.

The line control unit 1 includes an address register 1l, a reception buffer length register 16 of a range register 12, a secured reception buffer, a buffer length register 13, a comparison circuit 17, a DMA control circuit 14, an LA control circuit 15, an LA data register 18, and a general-purpose receiver/ Transmitter (URT) 1 9, 20, 21
．． Consists of 22.

The processor section 2 is a professional processor that controls the entire communication control device.
The upper bus interface section 3 controls the interface between the communication control device and the upper host computer.The block memory section 4 is a memory in which firmware and control tables for controlling the communication control device and transmission data/reception data are stored. It is.

The address register 11 stores the start addresses of the transmitting buffer and receiving buffer assigned to the memory section. In particular, multiple start addresses of the receive buffer can be stored. Range register l2 stores the buffer lengths of the transmit buffer and receive buffer.

In particular, multiple buffer lengths can be stored in the receive buffer.

The reserved reception buffer length register 13 is a register that stores the total buffer length obtained in the reception buffer reservation process.
It is compared by the reception buffer length register 16 and the comparison circuit 17.

The receive buffer length register 16 is a register that stores the receive buffer length added to received data.

The comparison circuit 17 is a circuit that compares the secured reception buffer length register 13 and the reception buffer length register l6, and determines whether the secured reception buffer length register l3 and the reception buffer length register 16 are equal, or the reception buffer length register l6 is smaller. A request is made to the LA control circuit 15 to reserve a reception buffer until the time is reached.

The DMA control circuit 14 is a control circuit including a reception address counter and a range counter for directly transferring data between the memory section 4 and the LA data register 18 via the data bus 5l without going through the processor section 2.

The LA control circuit is a general purpose receiver/transmitter (URT).
) 19, 20, 21, and 22 and performs buffer reservation processing.

The LA data register 18 temporarily stores parallel data of the general-purpose receiver/transmitter (URT) 19, 20, 21, and 22, and is an amplifier huffer circuit.

General purpose receiver/transmitter (UR, T) 19, 20
, 21 and 22 are general-purpose receiver/transmitters that convert serial data from a line into parallel data and detect transmission control characters.

The operation of such a kangkai will be explained below.

The address bus 52 is connected to the address bus 52 by the upper bus interface section 3.
Firmware for controlling the communication control device is stored in the memory section 4 via the data bus 51.

When a receive command is issued from the host computer,
This command is transferred to the memory section 4 through the upper bus interface section 3 and the data bus 5l, and is decoded by firmware stored in the memory section 4. The LA control circuit 15, the URTs 19, 20, 21.22, and the DMA control circuit 14 are initialized by the firmware stored in the memory section 4 and the processor section 2, and are enabled to receive data from the line.

At the time of initial setting (when starting reception), the start address and reception buffer length of the reception buffer stored in the memory unit 4 are set in the address register 11 and range register 12 via the data bus 51, and also in the DMA control circuit l4. Set the address counter and range counter in . At the same time as this operation, receive buffer length register l3 is secured.
Set to .

The receive buffer length added to the received data is set in the receive buffer length register 16 and compared in the comparison circuit 17. If the receive buffer length register is larger, a request is sent to the LA control circuit and the data is stored in the memory section. The receiving buffer head address and receiving buffer length are set in the address register 11 and range register 12 through the data bus 5l, and the receiving buffer length is added to the value of the secured receiving buffer length register 13.

The receiving buffer is secured until the value in the receiving buffer 7 length register 16 is smaller or equal to the value, and the data is set in the address register 11 and range register 12.

When the receive data is received from the line, the serial data is
The data is parallel-converted by the URTs 19, 20, 21, and 22, and is written through the LA bus 53 to the LA data register 18, and then to the receive buffer address given by the address counter in the DMA control circuit 14 through the data bus 51.

In this manner, each time DMA transfer is performed between the URTs 19, 20, 21.22 and the memory unit 4, the address counter of the DMA control circuit 14 is counted up and the range counter is counted down.

If the range counter of the DMA control circuit l4 reaches zero, instead of securing the start address of the receive huffer and the receive buffer length stored in the memory unit 4, the address register set at the time of starting reception is used. 11
By setting the reception buffer start address and reception huffer length of the range register 12 to the address counter and range counter of the DMA control circuit l4,
Data from , 20, 21.22. LA bus 53,L
Transfer to the memory section via the A data register 18 and data bus 51 is continued.

[Effects of the Invention] As explained above, the first invention detects that the remaining amount of the reception buffer is less than a specified value and performs the process of securing the next reception buffer in advance. Since data can be transferred without interrupting the transfer operation, overruns are less likely to occur and performance can be improved.

Further, in the second invention, when securing a reception buffer at the time of starting reception, the reception buffer length added to the reception data and the total of the secured reception buffer lengths are equal or until the total of the secured reception buffer lengths becomes larger. Since a repetitive reception buffer is secured, data transfer can be performed without interrupting the data transfer operation in the middle, so overruns are less likely to occur and performance can be improved.

[Brief explanation of drawings]

1 and 2 are block diagrams showing first and second embodiments of the present invention. l...Line control unit, 2...Flosser unit, 3...Upper bus interface unit, 4...
...Memory L51...Data bus, 52.
... Address bus, 53 ... LA bus,
11...Address register, l2...
Range register, 13... Transfer buffer remaining amount detection circuit, 13'... Secure reception buffer length register, 14... DMA control circuit, 15...
...LA control circuit, 16.18'... LA data register, 16'... Receive buffer length register, 17, 18, 19, 19', 20, 21.22.
...General-purpose receiver/transmitter (URT), 1 7' ...Comparison circuit.

Claims (1)

[Claims] 1. In a communication control device comprising a processor section, a higher-level interface section, a line control section, and a memory section,
It has an address register and a range register that store the start addresses and receive buffer lengths of a plurality of receive data buffers, and a transfer buffer remaining amount detection circuit that indicates the remaining amount of the receive buffer that is being transferred from the line control section to the memory section. When the remaining capacity of the receive buffer during transfer is detected to be less than the specified value, the next receive buffer is secured, stored in the above address register and range register, and the remaining capacity of the receive buffer during transfer becomes zero. A reception buffer control method characterized in that, upon detection, the contents of the address register and range register indicating the next reception buffer are used to continue the transfer from the line control unit to the memory unit. 2. In a communication control device consisting of a processor section, a higher-level interface section, a line control section, and a memory section, a means for temporarily storing the receive buffer length added to received data and a process for securing the receive buffer are provided. means for holding a plurality of reception data buffer start addresses and reception buffer lengths secured by a receiver; means for comparing the reception buffer length added to reception data with the reception buffer length secured; A reception buffer control method having means for securing a reception buffer until the sum of the buffer length and the secured reception buffer length is equal or the reception buffer length is smaller.