JP2523874B2 - Asynchronous serial data transmission device - Google Patents

Description

The present invention relates to an asynchronous serial data transmission device (UART; Univers) for controlling data transmission between microcomputers.
al Asynchronous Receiver and Transmitter).

[Conventional technology]

Figure 2 shows a conventional asynchronous serial data transmission device (UA
It is a block diagram showing an example of (RT).

In the figure, 1 is an input / output terminal connected to a system bus line, 2 is a serial data transmission terminal, 3 is a serial data transmission terminal, 4 is data transmission to a system bus line, and data is from the system bus line. A bidirectional data bus buffer for carrying in, 6 is a transmission buffer for storing the transmission data from the system bus line and transmitting from the transmission terminal 2, 7 is a transmission for converting the transmission data of the transmission buffer 6 to serial and outputting it A control circuit, 10 is a reception buffer for storing the reception data from the reception terminal 3 and sending it to the system bus line from the input / output terminal 1, 11 is for receiving serial reception data and storing the reception data after converting the reception data into parallel data. It is a reception control circuit.

 Next, the operation will be described.

Parallel transmission data of one character consisting of a plurality of bits written in the transmission buffer 6 from the microprocessor through the data bus buffer 4 is transmitted from the transmission buffer 6 as serial data by the transmission control circuit 7. In this serial data, a start bit consisting of one "L" level bit and a stop bit consisting of a plurality of "H" level bits are added to the beginning of each character.

Further, the reception control circuit 11 causes the reception control circuit 11 to receive serial data of one character consisting of a plurality of bits with a start bit consisting of 1 bit of “L” level at the beginning and a stop bit consisting of plural bits of “H” level at the end. It is received by 10, converted into parallel data and stored. The microprocessor reads this received data through the data bus buffer 4.

[Problems to be Solved by the Invention]

In the conventional UART, data is transmitted asynchronously as described above, that is, without being given a synchronizing signal from the outside, by synchronizing within itself, in this case, bit synchronization is performed for each character. Therefore, it is not possible to handle multiple characters as one block. Therefore, in order to handle multiple characters as one block, a circuit that counts the number of characters is required separately from the UART in both systems where the number of characters in one transmission is always constant and systems where it is not. However, there is a problem that an extra board area is required.

The present invention has been made to solve the above problems, and an object thereof is to obtain an asynchronous serial data transmission device capable of handling a plurality of characters as one block without increasing the board area. And

[Means for solving the problem]

The asynchronous serial data transmission device according to the present invention,
Programmable character number register capable of writing a desired number of characters to be handled as one block from a data bus line, wherein one character is composed of a plurality of predetermined bits, and transmission controlled by a transmission control circuit A transmission character number counter for counting the number of characters transmitted by the buffer, a reception character number counter for counting the number of characters received by the reception buffer controlled by the reception control circuit, a transmission character number counter and a character number register. A transmission character number match detection circuit that sequentially compares and sets a flag when they match, and a reception character number match detection circuit that sequentially compares the reception character number counter and a character number register and sets a flag when they match, Multiple characters into one Tsu is that to be able to be treated as a click.

[Action]

In the UART according to the present invention, the set value of the character number register and the value of the transmitted character number counter are a transmission character number matching detection circuit, and the set value of the character number register and the received character number counter are a received character number matching detection circuit. Since successive comparisons are made and a flag is set when a match is found, a plurality of characters can be treated as one block. Further, since the both character number counters are built in the chip, the substrate area is not increased.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an input / output terminal connected to a system bus line, 2 is a serial data transmission terminal, 3 is a serial data reception terminal, 4 is data transmission to a system bus line, and from the system bus line. Bidirectional data bus buffer for carrying in the data of 5, a programmable character number register writable from the system bus line, 6 stores data for transmission from the system bus line, and transmits it from the transmission terminal 2. A transmission buffer, 7 is a transmission control circuit for converting the transmission data of the transmission buffer 6 to serial and outputting the same, and 8 is a transmission buffer 6
, A transmission character number counter that counts the number of transmission characters sent from the transmission terminal 2, and 9 is a transmission character number match that detects a match between the set value of the character number register 5 and the value of the transmission character number counter 8. A detection circuit, 10 is a reception buffer that stores the reception data from the reception terminal 3 and sends the data to the system bus line from the input / output terminal 1, 11 is reception of serial reception data and storage after converting the reception data to parallel. Reception control circuit, which performs
Is a received character number counter for counting the number of received characters to be stored in the receive buffer 10, 13 is a received character number detection circuit for detecting a match between the set value of the character number register 5 and the value of the received character number counter 12, 14
Is a transmission character number match flag output terminal which outputs a flag when the transmission character number match detection circuit 19 detects a match, and 15 is a reception character which outputs a flag when the reception character number match detection circuit 13 detects a match It is a number match flag output terminal.

 Next, the operation of the above embodiment will be described.

When the number of characters transmitted / received once is predetermined, the microprocessor writes the value of the number of characters in the character number register 5 through the data bus buffer 4. After the setting of the number of characters is completed, data transmission / reception is started. The transmission data of one character written in the transmission buffer 6 through the data bus buffer 4 is transmitted from the transmission terminal 2 as serial data by the transmission control circuit 7. The transmission character number counter 8 is incremented each time one character is transmitted. The transmission character number coincidence detection circuit 9 successively compares the set value of the character number register 5 and the value of the transmission character number counter 8, and when a coincidence is detected, a flag is set to the transmission character number coincidence flag output terminal 14. . The microprocessor can check the number of characters sent by this flag.
Therefore, it is possible to perform various interrupt processes not for each character but for each block composed of a plurality of characters.

On the other hand, the reception data of one character received from the reception terminal 3 is stored in the reception buffer 10 by the reception control circuit 11. When the storage is completed, the received data can be read through the data bus buffer 4.

The received character number counter 12 is incremented each time one character is received. The received character number match detection circuit 13 successively compares the set value of the character number register 5 and the value of the received character number counter 12, and when a match is detected, the received character number match flag output terminal.
Flag 15 The microprocessor can confirm the number of received characters by this flag, and can perform various interrupt processes not for each character but for each block composed of a plurality of characters.

In the above, the case of a system in which the number of characters sent / received once is always constant has been described. However, even in a system in which the number of characters sent / received once is changed, the programmable character number register of the programmable This can be dealt with by resetting the set value.

In this embodiment, since a circuit for counting the number of transmitted / received characters is built in, it is not necessary to provide the counter separately from the UART, and the board area does not increase.

Since the device of the above embodiment is a UART, the data via the data bus buffer is of course parallel data.
The present invention may be a system in which the data bus buffer portion handles serial data, and has the same effect as the above embodiment.

Also, in the above embodiment, the transmission or reception character number counter is described as incrementing each time one character is transmitted or received, but this may be a counting method in which it decrements each time one character is transmitted or received.

〔The invention's effect〕

As described above, according to the present invention, the number of transmitted / received characters is counted, and a comparison is made with a preset character number register, and a flag is set when a match is found. Therefore, bit synchronization is performed for each character. UART
Despite this, it is possible to handle multiple characters as one block, and in both systems where the number of sent and received characters is predetermined and systems where it is not, a circuit for counting the number of sent and received characters is separate from the UART. It is not necessary to provide it, and there is an effect that the substrate area does not increase.

[Brief description of drawings]

FIG. 1 is a block diagram of a UART according to an embodiment of the present invention,
FIG. 2 is a block diagram of a conventional UART. 1 is an input / output terminal, 2 is a transmission terminal, 3 is a reception terminal, 4 is a data bus buffer, 5 is a character number register, 6 is a transmission buffer, 7 is a transmission control circuit, 8 is a transmission character number counter, and 9 is a transmission character. Number match detection circuit, 10 receive buffer, 11 receive control circuit, 12 receive character number counter, 13 receive character number match detection circuit, 14 send character number match flag output terminal, 15 receive character number This is a match flag output terminal. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A programmable character number register capable of writing a desired number of characters to be handled as one block from a data bus line, wherein one character is composed of a predetermined plurality of bits, and a transmission control circuit. A transmission character number counter that counts the number of characters transmitted by the transmission buffer controlled by, a reception character number counter that counts the number of characters that the reception buffer controlled by the reception control circuit receives, and a transmission character number counter. Successive comparison with the character count register and raises a flag when they match The transmission character count match detection circuit and the receive character number counter and the character count register are successively compared and raises a flag when they match With a circuit, multiple characters Asynchronous serial data transmission apparatus characterized by capable of handling data as one block.