KR960003649B1 - Microcomputer system for communication - Google Patents

Abstract

No content.

Description

Microcomputer System for Communications

1 is a block diagram showing one embodiment of a DMA controller constituting a serial communication apparatus according to the present invention.

2 is a block diagram showing an example of a serial communication system to which the present invention is applied.

3 is a flowchart showing an example of a frame transfer procedure by the DMA controller according to the present invention.

4 is a block diagram showing an example of the configuration of a microcomputer system having a serial communication device comprising a communication control device and a DMA controller.

TECHNICAL FIELD The present invention relates to a communication control technique, and more particularly to a serial communication between microprocessors. The present invention relates to, for example, transmitting data and receiving data in a first in first out type memory (hereinafter referred to as FIFO) and The present invention relates to a technology effective for use in a serial communication device having a DMA (direct memory access) controller for transferring between random access memory.

Conventionally, in order to be able to execute serial communication between microprocessors, a communication LSI such as µPD7201A manufactured by Nippon Electric Co., Ltd. has been provided. 4 shows an example of a system using this communication μPD7201A. That is, the microprocessor PU is connected to the memory MEM, DMA controller DMAC, and LSI SIO for serial communication via the system bus BUS.

In this system, when there is data that the microprocessor CPU wants to send to another microprocessor not shown, the microprocessor CPU sends a comment about the DMA controller DMAC. In doing so, the DMA controller DMA outputs an address on the system bus BUS, reads the desired transmission data in the memory MEM and supplies it to the communication LSI SIO. The transmission data supplied to the communication LSI SIO is stored in the internal FIFO and then converted into serial data and output.

On the other hand, when received data enters the communication LSI SIO from the outside, it is converted into parallel data every byte and stored in the receiving FIFO. When the FIFO becomes full, an interrupt is notified to the microprocessor CPU. The read command is then sent from the microprocessor CPU to the DMA controller DMAC, which transfers the received data in the FIFO to the memory MEM. Thereafter, the microprocessor CPU accesses the memory MEM to obtain the received data. (NEC Electronic Devices μPD7201A User's Manual issued in 1984 by Nippon Electric Co., Ltd.) P.1 to P.5, P, 24 ~ P, 26).

The communication LSI μPDPD7201A is an LSI that performs control according to a high level data link control (HDLC) protocol for transmitting data in units of frames. In a protocol for performing data communication on a frame-by-frame basis, a microprocessor may want to perform interpretation of received data for each received frame. Therefore, in the system using the communication LSI μPD7201A, an interrupt signal is sent to the microprocessor whenever the last data indicating the end of one frame is received.

However, in the method of interrupting the microprocessor every one frame as described above, when the bus license is transferred to the microprocessor by an interrupt and processing by the microprocessor is executed, data is transferred to the memory MEM by the DMA controller in the meantime. Will be interrupted. As a result, transmission of the next frame received by the FIFO to the memory MEM is disabled, which causes a decrease in the transmission efficiency in the case where several frames are transmitted in succession.

Thus, the present inventors have studied the method of prioritizing the transmission of the frame received in the FIFO to the memory when the frames are continuously transmitted to some extent as described above. That is, first, all frames sent in succession are received and transmitted to the memory MEM. Then, by interrupting the microprocessor in the DMA controller or the like, the microprocessor becomes the bus master instead of the DMA controller and the microprocessor executes processing for the frame transferred to the memory MEM.

However, since the conventional system does not have a function of counting the number of received frames, the number of frames to be processed by the microprocessor after the end of the frame transfer to the memory MEM is unknown. That is, the length or the number of interrupt request signals to be sent to the microprocessor by the DMA controller or the like cannot be known, and there is a possibility that the normal analysis is not executed. This has been made clear by the inventor's review. It is also possible to know the number of memories by the microprocessor reading all of the received data in the memory MEM after the end of the transfer. However, in such a method, the procedure of knowing the number of frames requires a very long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer system having a serial communication device that performs data transmission on a frame-by-frame basis, thereby reducing the overhead of receiving data, improving communication efficiency and reducing the burden on the microprocessor. This is to improve the throughput of the system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The outline | summary of the typical thing disclosed in this application is as follows.

In the case where frames are continuously received to some extent, data transfer to the memory is prioritized, and the microprocessor is prohibited from becoming a bus master. In addition, a counter is provided in the system for counting the number of frames received. The countdown of the count value counted to this counter is executed whenever the microprocessor finishes processing one frame. As a method of confirming that the frames are continuously received to some extent, for example, a method of determining that the frames are continuously received when any of the received frames exist in the FIFO is considered. Although the reception frame is continuously transmitted from the FIFO to the memory, the fact that the reception frame exists in the FIFO is because the frames are considered to be continuously received to some extent.

According to the above-described means, the frame is transmitted to the memory by the DMA controller while the series of frame reception is continuous, and processing of the frame in the memory by the microprocessor is started after the final frame reception. As a result, interrupt processing of the microprocessor causing interruption of the DMA transfer can be prevented and communication efficiency can be improved. When the microprocessor interprets the communication data after receiving a series of frames, it is possible to immediately know the number of frames received by the counter value, thereby reducing the burden on the microprocessor and improving the throughput of the system. Can be achieved.

In addition, as a method of confirming that the last frame of the continuous series of frames has been received, for example, a method of determining that the last frame has been received when the received data does not exist in the FIFO is considered. As a result of sequentially transmitting the frame data in the FIFO to the memory, the absence of data in the FIFO in which the received frame is stored is because it can be determined that the reception of a series of frames has been completed.

1 illustrates one embodiment of a DMA controller constituting a microcomputer system having a serial communication function together with an LSI (SIO) for communication control in accordance with the HLDC protocol.

The DMA controller of this embodiment has a micro ROM (read only memory) 1, an address generator 2 for generating an address of a memory to which data is transferred, a control register or a status register, and the like to determine an operation mode inside the controller. It consists of the control part 3 etc. which are performed. The micro ROM 1 stores a microprogram comprising a series of microcommand groups for executing DMA transfer of received data from the receiving data FIFO in the communication controller SIO to the memory of the host computer, and the like. Generates a control signal for each part inside the controller according to the command.

When the DMA transfer request signal DTR is received from the communication control device SIO, the DMA controller DMAC activates the micro ROM 1 and reads a corresponding series of micro instructions, thereby causing the address generator 2 to read. A destination address is generated which in turn indicates where the data is to be controlled and transmitted, which is output on the address bus 11 of the system (at this time, the head address of the data storage area prepared on the memory is generated in advance by the microprocessor). Is set in the register in section (2). In addition to the output of the address, the DMA controller DMAC sends an acknowledgment signal RXACK to the communication control device SIO. Then, the received data for one frame is automatically read from the FIFO in the communication control device SIO and output on the data bus 12. The received data read from the FIFO may be transferred to the memory after being loaded into the DMA controller, but in this embodiment, the address bus in the DMA controller corresponds to the output of the received data in the FIFO onto the data bus 12. The destination address is output on (11). For this reason, the data on the data bus 12 are stored in the memory of the host computer as it is.

In this embodiment, a counter circuit 4 for counting the number of received frames is provided. When the frame end signal FES is supplied to the DMA controller from the communication control device SIO, the frame end processing signal is supplied from the micro ROM 1. The counter circuit 4 is counted up by the output. The counter circuit 4, for example, takes a logical sum of each bit of the counter and outputs it as an interrupt request signal IRQ to the microprocessor. In the counter circuit 4, the microprocessor is read at any time from the outside. Therefore, an address is assigned to the counter, and an address decoder 5 is provided in the DMA controller. The DMA transfer request signal DTR is, for example, at a high level when received data is stored in a FIFO in the communication control device SIO. This generates a transfer request to the DMA controller DMAC. In addition, when no reception data is stored in the FIFO, the DMA transfer request signal DRT becomes low. This reduces the transfer request to the DMA controller DMAC.

In the microcomputer system having a serial communication function using the DMA controller of this embodiment, the interrupt request signal IRQ output from the DMA controller DMAC is treated as a signal having a lower priority than the DMA transfer request signal DTR for the DMA controller DMAC. As a result, even if the counter circuit 4 counts up by the frame end signal FES supplied from the communication control device SIO to the DMA controller, and the interrupt request signal IRQ is output, the DMA transfer request signal DTR becomes First, processing such as interpretation of received data by the microprocessor is not started. In other words, in the system of this embodiment, the interrupt processing by the microprocessor is executed after the final frame is entered in the communication line and its transfer is terminated and after the occupied state of the bus by the DMA controller is released. For this reason, as in the conventional system, reception of a frame is not interrupted midway, and communication efficiency is improved.

In addition, although not particularly limited, the DMA controller DMAC of this embodiment is configured such that DMA transfer control is executed on the condition that the enable bit provided in the status register is set to "1" by the microprocessor. For example, by the DMA controller DMAC, the enable bit is set to "1" by setting the head address of the area in which the data to be transmitted is stored in a register in the address generator 2.

2 shows another embodiment of the present invention.

In this embodiment, a microprocessor CPU, a DMA controller DMAC, a communication controller SIO and a bus controller BC are formed on the same semiconductor substrate. This one-chip semiconductor constitutes a processor NPU for communication control. Control signals provided between the microprocessor CPU, the DMA controller DMAC, or the communication control device SIO, that is, the frame end signal FES, the DMA transfer request signal DTR, the arc signal signal RXACK, and the interrupt request signal IRQ, respectively, are shown in FIG. It has the same role as the control signal of the signal. In this embodiment, a bus controller BC for an internal bus is provided in the processor NPU for communication control. The bus controller BC receives the bus occupancy request signal RE1 from the DMA controller DMAC and, upon confirming this, sends an acknowledgment signal ACK1 to the DMA controller DAMC. When the bus occupancy request signal RE2 is received from the microprocessor CPU, and this is confirmed, the acknowledgment signal ACK2 is sent to the microprocessor CPU. When the bus occupancy request signals RE1 and RE2 occur at the same time, bus ticket acquisition of the DMA controller DMAC is given priority. In this embodiment, a bus occupancy request signal RE1 is generated in accordance with the generation of the DMA transfer request signal DTR. In addition, the bus occupancy request signal RE2 is generated in response to the occurrence of the interrupt request signal IR1.

3 shows an example of the procedure of frame reception processing by the microprocessor in the DMA controller DMAC of the above embodiment.

If the enable bit provided in the status register in the controller 3 is set to "1", the DMA controller first determines whether or not the DMA transfer request signal DTR is input from the communication control device SIO (routine R1). When there is a DMA transfer request, only one byte of the received data stored in the byte unit in the FIFO is read and transferred to the memory (routine R2). Then, the frame end signal FES is checked to determine whether the frame has ended (routine R3). If it is determined that the frame has not ended, the routine returns to the routine R2 to repeat the data transfer. When the frame ends, the frame termination processing routine R4 is executed and the counter circuit 4 is counted up (routine R5). Then, the process returns to the routine R1 again and repeats the above operation. Here, the frame end processing routine is, for example, a check of whether there is an error in the received data, the type of error, and the like are determined, and the result is stored in a status register (not shown) in the communication control device SIO. Says the action.

Further, the counter circuit 4 of the above embodiment is configured such that the microprocessor counts down, for example, by writing "1" to the frame end bit provided in the status register in the control unit 3.

When the reception of a series of frames ends, the bath right is transferred to the microprocessor, and the received data is analyzed and the like. The reception termination of the series of frames can be determined by the reception data stored in the FIFO in the communication control device SIO being transferred to the memory and the inside of the FIFO being empty. When the frame processing by the microprocessor for one frame ends, "1" is written to the frame end bit, and the counter circuit 4 in the DMA controller DMAC counts down. In this way, since the interrupt signal IR1 for the microprocessor is supplied continuously until the value of the counter becomes " 0 ", the microprocessor recognizes that the processing up to the last frame has not yet finished and proceeds to processing of the next frame.

As described above, in the above embodiment, even if the DMA controller continuously executes the transmission processing of several reception frames, the microprocessor can repeat the frame processing such as the reception data analysis by the number of frames after the transmission is completed. Therefore, even when the received frames are transmitted continuously, the microprocessor can accurately know the number of end-of-frame interrupts or the period required for interrupt processing without having to decode the status after transmission and find the end of the frame. For this reason, it is not necessary to perform the procedure for confirming such a number of frames, and the throughput of a system will be improved.

In the above embodiment, only the reception functions of the communication control apparatus SIO and the DMA controller have been described, but in general, these LSIs are often provided in parallel with the transmitter, and this embodiment is no exception.

As described above, the embodiment is a microcomputer system having a serial communication device for performing data transmission on a frame-by-frame basis, in which a frame is terminated in a DMA controller DMAC for transferring data from a FIFO in which data of a received frame is stored to a memory. A counter for counting signals is provided. As long as the counter value is "1" or more, the microprocessor is continuously supplied with the interrupt request signal IRQ, which has a lower priority than the DMA transfer request signal DTR. It is received and sent to the memory by the DMA controller. In addition, after receiving a series of frames, the interrupt processing of the frame is started by the microprocessor. In this case, the countdown of the count value counted to the counter is executed each time the microprocessor finishes processing one frame. As a result, the effect of preventing interruption of the DMA transfer due to the interrupt processing of the microprocessor has the effect of improving the communication efficiency. In addition, when the microprocessor interprets the communication data after a series of frame reception ends, the microprocessor can immediately recognize the number of frames received by the counter value, thereby reducing the burden on the microprocessor and improving the throughput of the system. have.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

For example, a count for counting the number of received frames is provided in the DMA controller DMAC, but is not limited to this, and may be provided in any other place.

In addition, the embodiment has been described in the case of applying to the serial communication device according to the HDLC protocol as an example, the communication protocol is not limited to the HDLC serial communication device according to another type of protocol for dividing a series of communication data into multiple transmissions The same applies to.

In the above description, the invention mainly applied to the DMA controller for serial communication, which is the field of use as the background, has been described. However, the present invention is not limited to this, and can be used for the general DMA controller.

Claims (19)

A counter means comprising a plurality of bits, a communication means having a first storage means for storing received data, a data transmission means for transferring the received data stored in the first storage means to a second storage means, and the second A central processing unit for processing the received data transmitted to the storage means for each unit information according to the output of the counter means, and the usage right of the bus provided in common between the central processing unit and the communication means and the second storage means. A bus control means for managing attribution, wherein the received data is composed of one or a plurality of unit information, the count value of the counter means is counted up according to the number of unit information of the received data, and the received data Each time unit information of data is processed by the CPU, the bus control means Than the processing of each unit of information by the central processor microcomputer system of the first transport operation by the data transfer means. 2. The processor according to claim 1, wherein the central processing unit forms a bus ticket request signal for requesting a bus usage right to the bus control means in accordance with the output of the counter means, and the communication means comprises the first storage means. And a bus ticket request signal for requesting a bus license right from the bus control means, provided that the reception data is stored in the bus control means. The method of claim 1, wherein the first storage means is a memory of a first-in first-out type, and the communication means converts serial data received through a communication line for transmitting or receiving serial data into parallel data. And storing the data in the first-in first-out type memory, and the data transfer means is a direct memory access controller. 4. The microcomputer system according to claim 3, wherein said counter means is provided inside said direct memory access controller. A communication controller used together with a microcomputer and a memory and processing a frame composed of serial data, comprising: a first memory means (FIFO) for receiving the frame and storing parallel data according to serial data constituting the frame; Serial communication means (SIO), including in response to the data transmission request signal (DTR) generated in the serial communication means (SIO) in response to the reception, the parallel data stored in the first memory means (FIFO) Data transfer means (DMAC) for transmitting the data to the memory, and counting means for indicating the number of frames as a count value of several bits, wherein the count value of the counter means is the serial communication means each time the frame is received. In response to the frame end signal FES generated at SIO, the counter counts up. And when not in the furnace, generate an interrupt request signal (IRQ) for the microcomputer, and the count value of the counter means is counted down in response to a predetermined control signal. 10. The apparatus of claim 8, further comprising a status register comprising a frame end bit, wherein the predetermined control signal is generated in the status register in response to the microcomputer writing data to the frame end bit. Communication controllers generated by means. A serial communication means (SIO) having a receiving memory (FIFO) for receiving a frame composed of serial data and storing received data according to the serial data constituting the frame, buses 11 and 12, coupled to the bus. A first bus request signal RE2 in response to a transfer request signal DTR for transmitting the received data stored in the memory MEMORY and the bus and stored in the receive memory FIFO to the memory MEMORY. In response to the frame transfer signal FES being supplied from the data transfer means (DMAC) and the serial communication means (SIO), the count value is counted up, and the number of received frames is counted by several bits. A counter means (4) for displaying as a value, coupled to the bus, for generating received data stored in the memory, in response to the non-zero count value being generated in the counter means; The CPU and the first and third bus request signals that receive the interrupt request signal IRQ and generate a second bus request signal RE1 having a lower priority than the first bus request signal RE2. Coupled to receive (RE2, RE1) and according to the priority of the first and second bus request signals (RE2, RE1), a bus to either of the data transfer means (DMAC) and the central processing unit (CPU). And a bus controller (BC) for selectively granting a volume, wherein the serial communication means (SIO) generates a transmission request signal (DTR) in response to the reception data stored in the reception memory, The count value is counted down in response to the CPU processing the data corresponding to one frame of the received data stored in the memory when the CPU has a bus ticket. 8. A communication system according to claim 7, wherein the receiving memory is a memory of a first-in first-out type. 8. A communication system according to claim 7, wherein said data transfer means (DMAC), said serial communication means (SIO) and said counter means (4) are formed on a semiconductor substrate. The communication system according to claim 12, wherein the central processing unit (CPU) and the bus controller (BC) are formed on the semiconductor substrate. The communication system according to claim 12, wherein the frame is in the form of a frame according to the HDLC protocol. The communication system according to claim 10, wherein said counter means (4) are provided inside said data transfer means (DMAC). A communication microcomputer used together with the buses 11 and 12 and a memory coupled to the bus and capable of receiving a plurality of frames supplied continuously, the serial data corresponding to at least one receiving frame. A serial communication means (SIO) having a receiving memory (FIFO) which can be stored as, and generating a transmission request signal (DTR) in response to storing received data in the receiving memory, coupled to the bus, and receiving the receiving memory ( Data transmission means (DMAC) for generating a first bus request signal (RE2) in response to the transmission request signal (DTR) to transmit the received data stored in the FIFO to the memory (MEMORY), the serial communication. In response to the frame end signal FES being supplied from the means SIO, the count value is counted up, and the number of received frames is displayed as a count value of several bits. An interrupt request signal (IRQ) generated in the counter means (4) in response to the counter value being nonzero for processing the received data stored in the memory (MEMORY), coupled to the counter means (4) ) And a CPU which generates a second bus request signal RE1 having a lower priority than the first bus request signal RE2 and the first and second bus request signals RE2 and RE1. When receiving the first bus request signal (RE2, RE1) from the data transmission means (DMAC), the bus license is first given to the data transmission means (DMAC), and the first bus request signal ( And a bus controller BC for giving a bus right to the CPU in response to the second bus request signal RE1 supplied from the CPU after RE2 is extinguished. The count value of the counter means is determined by the CPU. And a communication microcomputer counting down each time the data corresponding to one frame of the received data stored in the memory is processed. The communication microcomputer of claim 13, wherein the receiving memory is a memory of a first-in first-out type. The communication microcomputer of claim 13, wherein the communication microcomputer is formed on a semiconductor substrate. The communication microcomputer of claim 13, wherein the frame is in a frame format conforming to the HDLC protocol. The communication microcomputer according to claim 13, wherein said counter means (4) is provided inside said data transfer means (DMAC). The apparatus of claim 13, further comprising a status register coupled to the counter means and having a frame end bit, wherein the CPU corresponds to one frame of received data stored in the memory. Each time data is processed, data is written to the frame total bit, and the counter means counts down the count value in response to writing of the data to the frame end bit. The apparatus of claim 7, further comprising a status register coupled to the counter means and having a frame end bit, wherein the CPU corresponds to one frame of received data stored in the memory. Communication data is written to the frame end bit each time data is processed, and the counter means counts down the count value in response to the data being written to the frame end bit.

Images