KR100199021B1 - A multi-interrupt control device and method by interrupt order on pci bus - Google Patents

Abstract

The present invention relates to a multi-interrupt control device and a method for a sequential PCI bus for handling the interrupt between the system and the HST system to be connected to the PCI bus, difficulty in interrupt processing in the prior art, other systems In order to solve the limitation in using the interrupt with the present invention, the present invention provides a plurality of interrupt resources in a system connected to the PCI bus through the interrupt line of one of the PCI buses. It is suggested to make it possible.

Description

Multiple interrupt control device and method for sequential PCI bus

The present invention relates to a multi-interrupt control device and method for a sequential PCI bus for handling interrupts between a system and a host system to be connected to the PCI bus.

Conventionally, one interrupt is satisfied in a system connected to a PCI bus, but due to the miniaturization of the chip and the multifunction of the system, there are many interrupt resources in the system connected to the host bus. (Starvation) phenomenon occurs, and there is a problem that places a lot of restrictions on the performance and use of the system, such as interrupt conflicts when using the same system with other systems.

The present invention allows a host system to process interrupts in an order of occurrence and priority via an interrupt line of one of the PCI buses through a plurality of interrupt resources in the system connected to the PCI bus, thereby reducing the local interrupt resources in the system. It is efficiently managed by interrupt queues and flags so that interrupt processing of local interrupt resources in the system can be processed in order of occurrence and priority without starvation.

1 is a block diagram showing the present invention and the peripheral relationship functional block.

2 is a block diagram of a multiple interrupt controller for a sequential PCI bus of the present invention.

3 is a control flowchart of an interrupt detector according to the present invention.

4 is a control flowchart of an interrupt queue controller according to the present invention.

5 is a control flowchart of an interrupt queue input / output controller according to the present invention.

* Explanation of symbols for main parts of the drawings

410: interrupt detector 420: interrupt flag

430: interrupt queue controller 431: queue counter

440: interrupt queue 441: queue flag

450: interrupt queue I / O controller 460: priority encoder

In order to achieve the above object, the multi-interrupt control for the sequential PCI bus provides an interrupt from an interrupt detector to process a plurality of interrupt resources in a host and a system connected to the PCI bus through one interrupt line of the PCI bus. Detecting and setting an interrupt flag, determining an interrupt priority from the flag state, requesting a queue input from the interrupt queue controller, and acknowledging the reset flag; Setting interrupt information in the interrupt queue, incrementing the queue counter, confirming the queue input upon receiving a queue input request, shifting the interrupt queue to the right and decelerating the queue counter upon receiving a queue shift request; If the queue flag of the interrupt queue is set by checking, it requests an interrupt from the host, transmits it when the interrupt information is requested from the host, and requests a queue shift.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of the present invention and the peripheral related functional blocks, and shows a system for a PCI bus that is to be connected to the host system 100 and the PCI bus 110.

The system for the PCI bus is an essential element, and is composed of a PCI bus master / slave controller 200 that is responsible for data transmission through the PCI bus, and a PCI bus configuration register 300 that stores the configuration of the PCI bus. And it shows the connection state with the multi-interrupt controller 400 for the PCI bus according to the present invention.

The multi-interrupt controller 400 for the PCI bus receives local interrupts from the plurality of local interrupt resources 500 and is responsible for processing to deliver the interrupts to the host system 100 connected through the PCI bus 110. The interrupt line 400 is directly connected to the multiple interrupt controller 400 and the host system 100 through the PCI bus 110.

Queue output requests from host system 100 indicate that they are to be delivered to multiple interrupt controllers 400 through PCI bus master / slave controller 200, which is an integral part of the system for the PCI bus.

2 is an internal block diagram of the multi-interrupt controller 400 for the sequential PCI bus according to the present invention. The interrupt detector 410, the interrupt flag 420, the priority encoder 460, and the interrupt queue controller 430 are shown in FIG. ), A queue counter 431, an interrupt queue 440, and an interrupt queue input / output controller 450.

The interrupt detector 410 detects an interrupt from the local interrupt resources (1, 2, 3, ..., n), sets 415 the corresponding interrupt flag 420, and sets the interrupt information to the interrupt queue 440. A queue input request 416 is made to the interrupt queue controller 430 for writing. At this time, if several interrupts are detected at the same time, the priority among the plurality of interrupts detected at the same time is determined by the priority encoder 460, and the queue input request 416 to the interrupt queue controller 430 sequentially according to the priority. In response to the queue input fine signal 417 from the interrupt queue controller 430, the operation of resetting the corresponding flag 415 is repeated as many as the interrupt request detection number.

The interrupt queue controller 430 receives the queue input request 416 from the interrupt detector 410 and the queue shift request 451 from the interrupt queue input / output controller 450 to control the interrupt queue 440. A cue counter 431 is provided for addressing. When a queue input request 416 from the interrupt detector 410 comes, it inputs to the interrupt queue 440 corresponding to the current queue counter 431 value, increments the queue counter, and then queues the interrupt detector 410. Sending a confirmation 417 completes the queue input 432. When a queue shift request 451 from the interrupt queue input / output controller 450 arrives, the interrupt queue 440 is shifted to the right and the queue counter 431 is moved. Performs the function of reducing.

In addition, the interrupt queue input / output controller 450 searches for the queue flag 441 indicating whether the interrupt queue 440 is valid, and generates an interrupt signal to the host if it is set. When interrupt information is received from the host system 100 after an interrupt is generated, the 0th queue of the interrupt queue 440 is transmitted to the host system 100 through the PCI bus 110, and the interrupt queue controller 430 is transmitted to the host system 100. Performs a queue shift request 451.

The control flow according to the present invention is divided into the control flow of the interrupt detector, the control flow of the interrupt queue controller, and the input / output control flow of the interrupt queue, and the description of each is as follows.

3 is a detection flowchart of an interrupt detector.

In the start state, it is repeatedly checked whether an interrupt is detected (S1), and when an interrupt is detected, it is first checked whether there is at least one detected interrupt (S2), and if there is one detected interrupt, the corresponding flag is set ( S3) After encoding the interrupt (S4), a queue input request 416 is made to the interrupt queue controller 430 (S5).

When the queue input confirmation signal 417 is received while checking the queue input confirmation from the interrupt queue controller 430 (S6), the corresponding flag is reset and branched to the start state (S7). However, if one or more interrupts are detected (S2), the priority encoder 460 encodes the detected interrupts (S8), then makes a queue input request (S9) to the interrupt queue controller 430, and then interrupts the queue controller. When the queue input confirmation signal 417 is received (S10) and the queue input confirmation signal 417 is received, the corresponding flag is reset (S11), and when all detected interrupts are sequentially input to the interruption queue. This process is repeatedly performed until (S12).

4 is a flowchart for controlling an interrupt queue, and is a flowchart for managing an interrupt queue by receiving input from an interrupt detector and an interrupt queue input / output controller.

In the start state, it is checked whether there is a queue shift fairy 451 from the interrupt queue input / output controller 450 (S13). If there is a queue shift request, the interrupt queue is shifted to the right (S14), the queue counter is decremented by one (S15), and the branch is started. If there is no queue shift request, the interrupt detector 410 checks whether there is a queue input request 416, and if not (S16), branches to the initial state. If there is a queue shift request, it reads the count value from the queue counter 431 to check if the queue is empty, and if the queue is empty, the interrupt queue 440 from the priority encoder 460 to the queue according to this value. The interrupt information is controlled to be written (S18), the queue counter 431 is incremented by one (S19), the cue input confirmation signal 417 is sent to the interrupt detector 410, and then branches to the initial state.

5 is a flowchart of input / output control of an interrupt queue.

In the start state, the interrupt queue input / output controller 450 checks the interrupt queue flag 441 and sets it (S20), generates an interrupt signal to the host (S21), and receives an interrupt information request from the host (S22). Reads interrupt information from the host and sends it to the host (S23), and makes a queue shift request (S24) to the interrupt queue controller, and branches to the start state.

As described above, the present invention processes a plurality of interrupt resources in a system connected to a PCI bus through an interrupt line of one of the PCI buses, so that the use of a host system can be utilized by another system because of convenience of interrupt use and limited interrupt resources. Can promote it.

In addition, interrupts are processed in the order of interrupt occurrence and priority interrupts are handled first, so it is easy to process multimedia, efficient use of system resources, and access to host using queue flags. The number can be reduced.

Claims (5)

In order to process the host system connected to the PCI bus and a plurality of local interrupt resources in the system as one interrupt line of the PCI bus, the interrupt information detected from the plurality of local interrupt resources is detected and the corresponding interrupt flag is controlled. Interrupt detection means for making a cue input request according to priority and receiving a cue input acknowledgment signal to control a corresponding flag; An interrupt flag indicating a plurality of interrupt partners according to flag control of the interrupt detection means; Priority determining means for determining the priority of the plurality of input interrupt information according to the enable signal of the interrupt detecting means; Interrupt queue control means for receiving an queue input request signal and a queue shift request signal to control an interrupt queue; An interrupt queue which is input according to the control of the interrupt queue control means and outputs according to the priority determined by the priority determining means; Check the validity of the interrupt queue to generate an interrupt signal to the host system, receive the interrupt information request signal from the host system, transmit the interrupt queue information to the host system through the PCI bus, and queue shift to the fraud interrupt queue control means. Multiple interrupt control device for a sequential PCI bus, characterized in that the interrupt queue input and output control means for making a request. 2. The apparatus of claim 1, wherein the priority determining means uses an encoder. 2. The apparatus of claim 1, wherein the interrupt queue control means is incremented in response to a queue input request signal from the interrupt detection means to address a queue, and in accordance with this queue shift request signal from the interrupt queue input / output control means. A multi-interrupt control device for a sequential PCI bus, characterized by comprising a decrementing queue counter. 2. The apparatus of claim 1, wherein the interrupt queue has a queue flag indicating whether the interrupt queue is valid. An interrupt detector, an interrupt queue controller, a priority encoder, and an interrupt queue input / output controller are provided to handle interrupts from the interrupt detector to process a plurality of interrupt resources in a system and a host connected to the PCI bus through one interrupt line of the PCI bus. Detecting and setting an interrupt flag, determining an interrupt priority from the flag state, requesting a queue input from an interrupt queue controller, and acknowledging the reset flag to reset the interrupt flag; A second step of setting interrupt information in an interrupt queue, increasing a queue counter, confirming a queue input when receiving the queue input request, and shifting the interrupt queue to the right and decreasing a queue counter when a queue shift request is received; And a third process of requesting an interrupt to the host if the queue flag of the interrupt queue is set and transmitting the interrupt information to the host if the interrupt information is requested from the host, and requesting a queue shift.