JPH084278B2 - Microcomputer system with serial communication function - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication control technology and a technology particularly effective when applied to serial communication between microprocessors.
For example, DMA that transfers transmission data and reception data between a first-in / first-out type memory (hereinafter referred to as a FIFO) and a random access type memory
The present invention relates to a technique effective for use in a serial communication device having a (direct memory access) controller.

[Prior Art] Conventionally, communication LSIs such as μPD7201A manufactured by NEC Corporation have been provided to enable serial communication between microprocessors. FIG. 3 shows an example of a system using this communication LSI EμPD7201A. That is, to the microprocessor CPU, via the system bus BUS, along with the memory MEM DMA controller DMA
C and serial communication LSI SIO are connected.

In this system, when there is data that the microprocessor CPU wants to send to another microprocessor (not shown), the microprocessor CPU sends a command to the DMA controller DMAC. Then, the DMA controller DMAC outputs the address on the system bus BUS, reads out the desired transmission data in the memory MEM, and then the communication LSI
Supply to SIO. The transmission data supplied to the communication LSI SIO is once stored in an internal FIFO, then converted into serial data and output.

On the other hand, when the received data enters the communication LSI SIO from the outside, it is converted into parallel data byte by byte and stored in the receiving FIFO, and when the FIFO is full, an interrupt is sent to the microprocessor CPU to notify it. Then, a read command is sent from the microprocessor CPU to the DMA controller DMAC, and the DMA controller DMCA transfers the received data in the FIFO to the memory MEM. After that, the microprocessor CPU can access the memory MEM to obtain the received data (“NEC Electronic Device μPD720” issued by NEC Corporation in 1984).
1A User's Manual ").

[Problems to be Solved by the Invention] The communication LSI μPD7201A described above is an LSI that performs control according to an HDLC (High Level Data Link Control) protocol for transmitting data in units called frames.
Is. In a protocol that performs data communication in frame units, the microprocessor for each received frame
There are cases where it is desired to analyze received data. Therefore,
In the system using the communication LSI μPD7201A, the interrupt signal is sent to the microprocessor when the final data of the frame comes in.

However, in the method of interrupting the microprocessor on a frame-by-frame basis as described above, when the bus is transferred to the microprocessor by the interrupt and processing is performed by the microprocessor, the transfer of data by the DMA controller is interrupted during that time. Will end up. As a result, it becomes impossible to receive the next frame, which causes a decrease in communication efficiency when a plurality of frames are continuously transmitted.

Therefore, when the frames are continuous as described above, the present inventor gives priority to the reception of the frames, receives all the frames transmitted continuously, transfers the frames to the memory, and then the DAM.
We investigated a method of interrupting the microprocessor from the controller so that the microprocessor processes each frame after reception.

However, since the conventional DMA controller does not have the function of counting the number of received frames, there is a possibility that the number of interrupts to be sent to the microprocessor after the end of frame reception is unknown and normal analysis cannot be performed. However, it is possible to know the number of frames by reading all the received data in the memory after the end of reception, but in such a method, even the procedure of knowing the number of frames requires a considerably long time.

An object of the present invention is to reduce the overhead at the time of receiving data in a microcomputer system equipped with a serial communication device that transmits data in frame units, improve communication efficiency, and reduce the load on the microprocessor. To improve the system throughput.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, the FI in which the received frame data is stored
A counter that counts the frame end signal is provided in the DMA controller that transfers data from the FO to the memory, and while the count value of this counter is "1" or more, the microprocessor continuously receives a transfer rate higher than the DMA transfer. It is intended to supply a low interrupt signal.

[Operation] According to the above-described means, while a series of frames is continuously received, the frames are accepted and transferred to the memory by the DMA controller, and the frame interrupt processing by the microprocessor is started after the final frame is received. In this way, it is possible to prevent interruption of DMA transfer due to interrupt processing of the microprocessor to improve communication efficiency, and when the microprocessor analyzes communication data after receiving a series of frames, the number of received frames is the counter value. As will be readily understood from the above, it is possible to achieve the above object of reducing the load on the microprocessor and improving the throughput of the system.

[Embodiment] FIG. 1 shows a communication control LSI according to the HLDC protocol.
With (SIO), one embodiment of a DMA controller to achieve a microcomputer system with serial communication capability is shown.

The DMA controller of this embodiment includes a micro ROM (read only memory) 1, an address generator 2 that generates an address of a memory to which data is transferred, and a control
It has a register, a status register, and the like, and is configured by the control unit 3 and the like that determines the operation mode inside the controller. The micro ROM 1 is a communication control device SI
A microprogram consisting of a series of microinstructions for performing DMA transfer of received data from the receive data FIFO in O to the memory on the host computer side is stored. Based on the read microinstruction, the microprogram in the controller is stored. It generates control signals for each part.

Then, the DMA controller sends DM from the communication control device SIO.
When the A transfer request signal DTR is input, the micro ROM is activated,
A series of corresponding microinstructions are read out, the address generator 2 is controlled by this, and destination addresses indicating the data transfer destinations are generated one after another, which are output to the address bus 11 of the system (at this time). , The start address of the data storage area prepared on the memory is preset in the register in the address generator 2 by the microprocessor). In addition to the output of the address, the DMA controller sends an acknowledge signal RXACK to the communication control device SIO. Then, the communication control device SIO
Received data for one frame is automatically read from the internal FIFO and output to the data bus 12. The received data read from the FIFO may be first read into the DMA controller and then transferred to the memory, but in this embodiment, the received data in the FIFO is output on the data bus 12. Correspondingly, the destination address is output from the DMA controller onto the address bus 11. Therefore, the data on the data bus 12 is stored as it is in the memory on the host computer side.

Moreover, in this embodiment, the counter circuit 4 for counting the number of received frames is provided, and the communication control device SIO
When a frame end signal FES is supplied from the DMA controller to the DMA controller, a frame end processing signal is output from the micro ROM 1, whereby the counter circuit 4 is made to count up. The counter circuit 4 takes the logical sum of the bits of the counter,
Interrupt request signal IRQ to the microprocessor
Is output as. Also, the counter 4
Is designed so that the microprocessor can read it from the outside at any time, so that an address is assigned to the counter and an address decoder 5 is provided in the DMA controller.

In the microcomputer system with serial communication function using the DMA controller of this embodiment, the interrupt request signal IRQ output from the DMA controller is DMA
It is handled as an interrupt with lower priority than the DMA transfer request to the controller. As a result, even if the counter 4 is counted up by the frame end signal supplied from the communication control device SIO to the DMA controller and the interrupt request signal IRQ is output, if the next received frame is present, the data received by the microprocessor is received. However, processing such as analysis is not started. That is, in the system of this embodiment, the interrupt processing by the microprocessor is
The final frame comes in from the communication line, the transfer is completed, and after the bus occupancy state of the DMA controller is released, it is executed collectively. Therefore, unlike the conventional system, the reception of the frame is not stopped midway, and the communication efficiency is improved.

Although not particularly limited, in the DMA controller of this embodiment, the DMA transfer control is executed when the enable bit provided in the status register is set to "1" by the microprocessor.

FIG. 2 shows an example of the procedure of frame reception processing by the microprogram in the DMA controller of the above embodiment.

If the above enable bit is set to "1", DMA
The controller first determines whether or not a DMA transfer request is received from the communication control device SIO (routine R1). When there is a DMA transfer request, the received data stored in the FIFO in byte units is read out by 1 byte and transferred to the memory (routine R2). Then, by looking at the frame end signal, it is determined whether or not the frame has ended (routine
R3). If it is determined that the frame has not ended, the routine returns to the routine R2 and the data transfer is repeated again.
When the frame ends, the frame end processing routine R4 is executed and the counter 4 is incremented (routine R5). Then, it returns to the routine R1 again and repeats the above operation.

The counter circuit 4 of the above embodiment is configured to count down by writing "1" to the frame end bit provided in the status register in the control unit 3 by the microprocessor, for example.

When the reception of a series of frames is completed, the bus use right is transferred to the microprocessor, and the received data is analyzed. Then, when the frame processing by the microprocessor for one frame is completed, the counter 4 in the DMA controller is counted down. Then, since the interrupt signal IRQ is continuously supplied to the microprocessor until the value of the counter becomes "0", the microprocessor confirms that the processing up to the final frame is not finished yet, and shifts to the processing of the next frame. To do.

As described above, in the above embodiment, even if the DMA controller continues to transfer a plurality of received frames, the microprocessor can repeat the frame processing such as the received data analysis for the number of frames after the transfer is completed. Therefore, even when the received frames are continuously transferred, the microprocessor can accurately know the number of end-of-frame interrupts without decoding the status after transfer and searching for the end of the frame. Therefore, it is not necessary to perform the procedure for confirming the number of frames, and the system throughput is improved.

In the above embodiment, only the reception function of the communication control device SIO and the DMA controller has been described.
In many cases, a transmitter is provided in the LSI, and this embodiment is no exception.

As described above, in the above-described embodiment, in a microcomputer system including a serial communication device that performs data transmission in frame units, a DM that transfers data from a FIFO in which received frame data is stored to a memory.
A counter for counting the frame end signal is provided in the A controller, and while the count value of this counter is "1" or more, the microprocessor is continuously supplied with interrupt signals of lower priority than DMA transfer. So, while the series of frames is being received, the frames are accepted and transferred to the memory by the DMA controller.
Since the interrupt processing of the frame is started by the microprocessor after the final frame is received, the interruption of the DMA transfer due to the interrupt processing of the microprocessor is prevented, and the communication efficiency is improved.

In addition, a counter that counts the frame end signal is provided in the DMA controller that transfers the data from the FIFO in which the received frame data is stored to the memory, and continuously while the count value of this counter is "1" or more. Since the interrupt signal with a lower priority than the DMA transfer is supplied to the microprocessor, the number of received frames can be immediately known from the value of the counter when the microprocessor analyzes communication data after receiving a series of frames. The effect is that the load on the microprocessor is reduced, and the throughput of the system is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the system in which the communication control device SIO and the DMA controller are configured by different LSIs has been described, but it is needless to say that the present invention can be applied to the case where they are formed on the same LSI.

In addition, although the embodiment has been described by way of example as applied to a serial communication device conforming to the HDLC protocol, the communication protocol is not limited to HDLC, and a protocol of another format for transmitting a series of communication data by dividing it into a plurality of parts is transmitted. The same can be applied to the following serial communication device.

In the above description, the invention made by the present inventor is mainly used for serial communication, which is the field of application behind the invention.
I explained the one applied to the DMA controller,
The present invention is not limited to this, and can be used for a DMA controller in general.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a microcomputer system equipped with a serial communication device that performs data transmission in frame units, the overhead at the time of data transmission is reduced to improve communication efficiency and reduce the burden on the microprocessor to reduce system throughput. Can be improved.

[Brief description of drawings]

FIG. 1 is a DM constituting a serial communication device according to the present invention.
FIG. 2 is a block diagram showing an embodiment of an A controller, FIG. 2 is a flow chart showing an example of the frame transfer procedure, and FIG. 3 is a structural example of a microcomputer system including a serial communication device including a communication control device and a DMA controller. It is a block diagram showing. 1 ... Micro ROM, 2 ... Address generation unit, 3 ... Control unit, 4 ... Counter circuit, 11 ... Address bus, 12 ...
… Data bus, CPU …… Microprocessor, SIO …… Communication controller, DMAC …… Transfer controller (DMA controller).

Claims (2)

[Claims] 1. A serial communication device which has a microcomputer, a memory connected to the microcomputer via a bus, a buffer for storing received data, and which transmits data in frame units, and directly through the bus. In a microcomputer system including a transfer control device for performing data transfer between the memory and the serial communication device, a counter for counting a frame end signal supplied from the serial communication device in the transfer control device. Is provided and an interrupt signal for the microcomputer is formed based on the count value of the counter until the count value becomes "0", and the count value of the counter is processed by one frame in the microcomputer. I will count down when it is over A microcomputer system comprising a serial communication function, characterized by comprising configured. 2. The interrupt signal is supplied to the microcomputer as a signal having a lower priority than a direct transfer request signal to the transfer control device, and the interrupt signal is supplied to the microcomputer. A microcomputer system having the serial communication function described.