JPH09269936A - Remote reading processing method and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up remote reading and to eliminate the interruption of a user program in a destination processor. SOLUTION: A user process traveling on CPU 111 of a processor A writes the request header 170 of remote reading into a header queue 120 and waits for the writing of a remote reading completion notice into a log buffer 127. A transmission device 113 generates the header of remote writing from the header 170, generates a remote read packet 171 having the header in a packet main body and sends it to a processor B. The reception device 214 of the processor B writes the header 270 of remote writing in the received packet 171 into a header queue 221. A transmission device 213 processes the header 270 of remote writing, generates the packets 271 and 274 of a series of remote writing and transmits them to the processor A. A reception device 114 data in the received packets 271 and 274 into a memory 112 and finally writes a remote reading completion notice into the log buffer 127.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inter-processor communication in a system in which a plurality of processors each having a CPU (Central Processing Unit), a memory, a receiving device and a transmitting device are connected to each other through an inter-processor network. The present invention relates to a remote read processing method and device for performing remote read at a high speed, which is a process in which a processor reads data on a memory of another processor.

[0002]

2. Description of the Related Art Conventionally, this type of remote lead has
It was realized as a system call made by (operating system), and the actual processing was performed by message communication between OSs. In the system call, the OS requests remote read as a message to the OS of the destination processor. The conventional technique will be described below with reference to FIG.

In FIG. 4, the CP of the processor A101
When the system call remote-read is executed from the user program running in U111, the CPU1
The control of 11 is switched to the OS, and the OS creates the parcel header 160 of the remote read message in the parcel header queue 120 on the memory 112 as a message to the OS of the destination processor that reads the data.
Parcel header 16 of this remote read message
In 0, as shown in the packet 161, which is generated from the parcel header 160, the destination processor number 162 of the message, the message type 163 indicating the remote read, the number of read words 164, the read address 165, and the read are performed. Own processor number (write processor number) 16 to which data is transferred
6, the write address 167 of the read data is included. The OS on the CPU 111 is the transmitter 11
3 is requested to transmit the parcel of this remote read message. The transmitting device 113 has a memory 112.
The parcel header 160 is read from the upper parcel header queue 120, a packet 161 of a remote read message is generated, and the packet 161 is sent to the processor B201 through an interprocessor network (not shown).

Packet 1 of remote read message
Receiving device 214 of processor B201 that received 61
Writes a remote read message in the message buffer 228 on the memory 212, generates an interrupt to the CPU 211, and requests the OS to process the message. The OS is the message buffer 22 on the memory 212.
The remote read parcel header 26 addressed to the processor A 101 having the read address 165 as the source address and the write address 167 as the destination address.
0 and the parcel header 261 of the remote read completion message to the OS of the processor A 101 are stored in the memory 21.
No. 2 is created in the parcel header queue 220, and a transmission request is issued to the transmission device 213.

The transmitter 213 of the processor B201 is
Upon receiving the transmission request from the OS, the remote write parcel header 260 in the parcel header queue 220 is read out and processed. The remote write parcel header 260 becomes a plurality of remote write packets 262 by the transmitting device 213 and is sent to the processor A 101 through the inter-processor network (not shown). After that, the transmission device 213 reads the remote read completion message header 261 in the parcel header queue 220 and processes it to process the packet 265 of the message to notify the completion of the remote read to the processor A101.
Send to OS.

The receiver 114 of the processor A101 is
Remote write packet 26 from processor B201
When 2 is received, the packet body 264 is written to the address on the memory 112 designated by the destination address 263. When the receiving device 114 receives the subsequent message to the OS, the receiving device 114 receives the message from the memory 112.
Write to upper message buffer 128, CPU11
Generate an interrupt for 1. The OS reads the message, knows the completion of the remote read, exits the system call, and transfers control to the user program.

[0007]

In remote read, read data is often necessary for the next processing, and the speed of processing the remote read affects the performance of the entire program. Therefore, the processing must be performed as quickly as possible, but the following problems are problems in the above-described conventional technology.

The first problem is that it takes a long processing time until a remote read request is issued by the processor that has performed the remote read. The reason is that remote read is realized by messages between OSs,
This is because when performing remote read, it is necessary to make a system call, a context switch from the user program to the OS occurs, and processing takes time.

The second problem is that it takes a long processing time for a processor requested for remote read. The reason for this is that the remote read request is transmitted in the form of a message between OSs, and therefore it requires context switch time to switch the CPU that was executing the user's program to the OS, and processing takes time. Is.

The third problem is that the execution time of the user program in the processor requested for remote reading becomes long. The reason is that the remote read request is transmitted in the form of a message between OSs, and the CPU that was executing the user's program is switched to the OS, so the user program is interrupted.

That is, in the prior art, when a remote read is performed, a context switch from the user program to the OS occurs due to the system call, and it takes time for the requesting processor to process the message. Since a remote read is requested by, the destination processor also needs to switch the context to the OS, which requires a long processing time, and at that time, the user program in the destination processor is interrupted.

Therefore, an object of the present invention is to eliminate the processor requesting remote read and the context switch from the user program to the OS in the requested processor to enable high-speed processing of remote read which influences the performance of the entire program. Is to

Another object of the present invention is to prevent the execution of the user program from being prolonged by not interrupting the execution of the user program in the CPU of the processor for which remote read is requested.

[0014]

A remote read processing method of the present invention is a processor in a system in which a plurality of processors each having a CPU, a memory, a transmitter and a receiver are connected via an interprocessor network. In a remote read processing method in which a user process running on the CPU reads data stored in the memory of another processor, in the remote read source processor, the user process reads the read processor number, the read word number, and the read. Write the remote read parcel header containing the address and write address to the parcel header queue on the memory of the local processor and request the transmitter of the local processor to send it, and then poll the log buffer on the memory of the local processor for remote read. End of In the remote read source processor, the transmission device requested to transmit reads the remote read parcel header from the parcel header queue on the memory of the self processor, and sets the self processor number to the destination processor number and the word number. A remote read packet having a remote write parcel header in which the read word number, the source address, the read address, the destination address, the write address, and the set remote write parcel header are respectively generated, and the destination is set via the interprocessor network. Of the remote read destination processor, and the remote read destination processor receives the remote read packet via the interprocessor network, and the receiving device of the processor receives the remote read packet. Writing the remote write parcel header, which is the packet body, of the packet to the parcel header queue on the memory of the self-processor and requesting the transmission device of the self-processor to perform transmission; and the transmission device requested to be transmitted at the remote read destination processor. Reads the remote write parcel header from the parcel header queue in the memory of its own processor, processes it, generates a series of remote write packets, and sends them to the remote read source processor via the interprocessor network. In the former processor, the receiving device, which has received a series of remote write packets as a response to the remote read via the interprocessor network, transmits the data contained in the body of the received remote write packet to its own processor. Memory and storing the fact that the remote read is completed in the log buffer on the memory of the processor itself when the last packet is received.

In the remote read processing device of the present invention, the user process running on the CPU of the remote read source processor is stored in the memory of the remote read destination processor connected to the processor via the interprocessor network. In the remote read processing device that controls the processing for reading the read data, the user process is provided in the remote read source processor and the user process includes a remote read parcel header including a read processor number, a read word number, a read address, and a write address. In response to the transmission request issued after writing to the parcel header queue on the memory of the local processor, read the parcel header of the remote read,
A remote read packet having a remote write parcel header in which a destination processor number is its own processor number, a word number is the read word number, a source address is the read address, and a destination address is the write address. To the remote read destination processor via the inter-processor network, and the remote write parcel header, which is provided in the remote read destination processor and is the packet body of the received remote read packet, in its own memory. A remote read destination receiver that writes to the above parcel header queue and requests transmission, and is provided in a remote read destination processor, and receives a transmission request from the remote read destination receiver, The remote read destination transmission device that reads and processes the remote write parcel header from the parcel header queue, generates a series of remote write packets, and sends them to the remote read source processor via the interprocessor network, and the remote read source processor. A remote read source that is provided and stores the data contained in the body of the received remote write packet in the memory of the local processor and writes the fact that the remote read is completed to the log buffer on the memory of the local processor when the last packet is received. And a receiver.

In the remote read processing device having the above-mentioned configuration, the user process of the remote read source processor places the remote read parcel header including the read processor number, the read word number, the read address and the write address on the memory of its own processor. When the transmission is requested by updating the normal header queue offset register after writing to the parcel header queue of, the transmitter of the remote read source processor receives the request for transmission, reads the remote read parcel header, and sends it to the destination. The processor number is its own processor number, the word number is the read word number, the source address is the read address, and the destination address is the write address. The remote read packet with a header as a packet body, and transmits to the remote read destination processor via the interprocessor network. Next, the remote read destination receiving device provided in the remote read destination processor writes the remote write parcel header, which is the packet body of the received remote read packet, into the parcel header queue on the memory of its own processor for remote read. A request is sent to the remote read destination transmission device by updating the header queue offset register, etc., and this remote read destination transmission device reads the remote write parcel header from the parcel header queue and processes it to generate a series of remote write packets. To the remote read source processor via the interprocessor network. Then, the remote read source receiving device provided on the remote read source processor stores the data contained in the main body of the received remote write packet in the memory of its own processor, and at the time of receiving the last packet, the data in the memory of its own processor. It writes that the remote read is completed in the log buffer of and notifies the user process of the completion of the remote read.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. As shown in FIG. 1, the plurality of processors 1 are
They are connected by the inter-processor network 2.
Each processor 1 includes a CPU 11 and a memory 12.
It has a transmitting device 13, a receiving device 14, and a bus 10 connecting them. The transmitter 13 and the receiver 14 constitute an interprocessor communication device.

On the memory 12, a normal parcel header queue 20 and a remote read parcel header queue 21.
2 parcel header queues are provided. The remote read parcel header queue 21 is used to send back the remote read result, and the normal parcel header queue 20 is used to send other parcels.

Within the transmitter 13, there is a normal header queue base address register 30 and a normal header queue offset register 32 that point to the normal parcel header queue 20. The normal parcel header queue 20 indicates the head position of the normal header queue 20, and the normal header queue offset register 32 indicates the normal header queue 2.
The write position of the parcel header within 0 is indicated by a relative address from the beginning. Further, there is a normal header queue offset register 31 that holds a value equal to the value of the normal header queue offset register 32 in a state where there is no unprocessed parcel header in the normal header queue 20. Further, the normal header queue offset register 32
Is provided with a comparator 33 for comparing the value of 1 with the value of the header queue offset register 31 for normal use, and the comparison result is input to the sequencer 37. Also, a copy 25 of the value of the above-mentioned normal header queue offset register 31
However, the base address 24 of the normal parcel header queue 20 (the normal header queue base address register 30
(Equivalent to the value of) and stored in the memory 12. It also indicates how much space is left in the normal parcel header queue 20 (however, exactly how much is free is determined by the value in the normal header queue offset register 32).
The normal last pointer 26 is also stored in the memory 12, and the CPU 11 writes the parcel header 22 in the normal parcel header queue 20 using these values.

Similar to the normal parcel header queue 20, the remote read parcel header queue 21 also has the following registers for it. First, the receiving device 14 has a remote read header queue base address register 50 and a remote read header queue offset register 51. The remote read header queue base address register 50 points to the beginning of the remote read parcel header queue 21, and the remote read header queue offset register 51 indicates the write position of the remote read parcel header queue 21 as a relative address from the beginning. . These are used when the receiving device 14 writes the parcel header 22 for sending the remote read result in the remote read parcel header queue 21. Further, the receiving device 14 indicates the end of the empty space of the remote read parcel header queue 21 (however, the exact space is determined by the value of the remote read header queue offset register 35) and the remote read last pointer 52. Is also equipped. The values of the remote read header queue offset register 51 and the remote read last pointer 52 are compared by the comparator 53, and the comparison result is input to the sequencer 55. On the other hand, the transmission device 13 has a remote read header queue base address register 34 and a remote read header queue offset register 35 similar to the remote read header queue base address register 50 and the remote read header queue offset register 51. Both remote read header queue offset registers 51, 3
A comparator 36 for comparing the values of 5 is provided. The value of the remote read header queue offset register 35 is set to 1 by the decrementer (-1 circuit) 54 in the receiving device 14.
The remote read last pointer 52 can be set.

The transmitting device 13 also includes the memory 2 on the memory 12.
Parcel header register 3 for storing parcel headers 22 read from one parcel header queue 20, 21
8 is provided. The parcel header register 38 stores in advance the first word 39 of the remote write parcel header required for processing the remote read parcel header. Further, since the source address written in the parcel header 22 is a logical address, the transmitting device 13 is provided with the TLB 40 for converting it into a physical address.

The receiver 14 also stores the packet sent from the interprocessor network 2 temporarily.
An IFO memory 56 and a packet header register 57 for storing the header portion of the packet are provided. Also,
The receiving device 14 includes a TLB 58 for converting the write address of the transmitted packet from a logical address to a physical address.

Further, the memory 12 is provided with a log buffer 27 for notifying the user process of the arrival of the last packet of the remote read response packets received by the receiving device 14, and the receiving device 14 has the log buffer 27. There is a log buffer address register 59 that holds the write address of this log buffer 27.

FIG. 3 exemplifies the structure of various parcel headers and the packets generated from them.

Of these, FIG. 3A shows the structure of a general parcel header 300 and a packet 305. The parcel header 300 is composed of 4 words. In the first word 301, the type of parcel, the processor number of the destination, whether the write address (destination address) in the destination processor is designated, and the like are designated. In the second word 302, the number of words to be transferred by this parcel is designated. Since the size of the packet transferred through the interprocessor network 2 is limited due to the hardware limitation of the interprocessor network 2,
In general, multiple packets are used to transfer the number of words specified here. In the third word 303, the start address (source address) of the memory 12 in which the data to be transferred is stored is designated. 4th word 3
In 04, a destination address which is a write address in the destination processor is designated. If it is written in the first word 301 that the sender does not specify the write address, the fourth word 304 is not used. That is, the value of the fourth word 304 is ignored by the transmitting device 13.

This parcel header 300 is transmitted by the transmitter 13.
Are processed into a plurality of packets 305 and sent to the interprocessor network 2. Packet 1 of 305
The word 306 stores almost the same information as the first word 301 of the parcel header 300. In other words, the type of packet, destination processor number, selection of write address, etc. In addition, it is also designated whether or not to write the completion of reception in the log buffer 27 when the reception by the destination processor is completed. In the second word 307, the number of words in the packet body is designated. The destination address is stored in the third word 308. If the receiving side determines the write address in the destination processor, the third word of the packet header 3
08 does not exist. After these packet headers,
Followed by the data to be transferred, which is the body 309 of the packet.

FIG. 3B illustrates the format of the remote write parcel header 310 and packet 315.
Remote write parcel header 310 first word 3
In 11, it is specified that it is a remote write parcel, that there is a destination processor number, and that there is a destination address. The number of words to be transferred is specified in the second word 312, and the source address, which is the storage address of the data to be transferred on the memory 12, and the write address in the destination processor are specified in the third word 313 and the fourth word 314. The destination address and is specified.

In the packet 315 generated from the remote write parcel header 310, it is specified that the packet is a remote write, the destination processor number and the destination are added, and whether to leave a log in the log buffer 27. The bit to do is the first word 316
The number of words in the packet body is designated in the second word 317, and the destination address is designated in the third word 318. Then, the packet body 319 is followed by the data to be transferred.

FIG. 3C illustrates a remote read parcel header 320 and a packet 325. Remote read parcel header 320 first word 321
Is the remote read parcel header and
The destination processor number is stored. Second word 32
2 is the number of words read by remote read, and the third word 323 is the read address of the destination processor.
In the fourth word 324, an address to write the remote read result is stored.

In the case of the remote read parcel header 320, the transmitting device 13 performs processing different from that of the normal parcel header, and the remote read packet 325.
Create In the remote read packet 325, the first word 326 stores the remote read packet and the destination processor number. 2nd word 3
27 includes 2 of the parcel header 320 of the remote lead.
Instead of the value of the word 322, 4 which is the number of words in the packet body is stored. Remote write parcel header 3 in the part of the packet body after the 3rd word
The four words that make up 28 are stored. That is, the third word 329 contains the remote write parcel header and the processor number of the destination, which is the fourth word 33.
In 0, the number of words read by the remote read designated by the second word 322 of the parcel header 320 is 5
The read address in the destination processor, which was specified in the third word 323 of the parcel header 320, was specified as the source address in the word 331, and was specified in the fourth word 324 of the parcel header 320 in the sixth word 332. The address where the remote read result is written is stored as the destination address. The remote read packet 325 is one packet having a packet word number of 4 regardless of the read word number.

FIG. 2 is a diagram for explaining the operation of remote read in this embodiment. The user program of the processor A101 is the data 2 on the memory 212 of the processor B201.
The case where 29 is remotely read is described. Less than,
The operation will be described with reference to the drawings.

In FIG. 2, the user program running on the processor A101 is a communication library function re.
It is assumed that the mote-read is executed. As the arguments of the communication library function remote-read, the read processor number, the number of read words, the read address in the destination processor, and the address to write the read result are specified. The communication library calculates the address to write the parcel header by combining the value of the normal header queue base address register 24 on the memory 112 and the value of the copy 25 of the normal header queue offset register 31, and calculates the remote read parcel at that address. The header 170 is written and the normal header queue offset register 31 in the transmitter 113 is updated by one header.
At the same time, the copy 25 of the normal header queue offset register 31 on the memory 112 is also updated by one header. After that, the communication library polls the log buffer 127 on the memory 112 and waits for the result of the remote read to be written. Here, the user program and the communication library constitute a user process.

At the time of writing the parcel header 170, the communication library compares the copy 25 of the normal header queue offset with the value of the normal last pointer 26, and if they match, the normal header queue offset register 32. Value is reset to the normal last pointer 26 and the comparison is performed again. If the values still match, the normal parcel header queue 120 is almost full, and this is notified to the OS. If they do not match, there is sufficient space in the normal parcel header queue 120, and the processing is continued.

On the other hand, the transmitter 11 of the processor A101
In 3, the value of the normal header queue offset register 31 and the value of the normal header queue offset register 32 are compared by the comparator 33. As described above, the communication library uses the normal header queue offset register 31.
Is updated by one header, the two values become different, and the fact is notified from the comparator 33 to the sequencer 37. As a result, the sequencer 37 recognizes that its own transmission device has been requested to transmit, and starts parcel transmission processing.

First, the sequencer 37 reads a 4-word parcel header 170 from the address of the memory 112 indicated by the values of the normal header queue address base register 30 and the normal header queue offset register 32, and stores it in the parcel header register 38. . Next, the first word of the parcel header 170 (3 in FIG. 3C)
(Corresponding to No. 21), and recognizes that this parcel header 170 is a remote read parcel header. And 1 in the parcel header
The word 321 is converted into the first word 172 of the packet of the remote read and sent to the interprocessor network 2. Then, the packet length of 4 words is sent to the interprocessor network 2 as the second word 173 of the remote read packet. Then, the processor number is incorporated in the first word 39 of the remote write packet header stored in advance in the parcel header register 38 and sent to the interprocessor network 2 as the third word 174 of the remote read packet. Thereafter, the second word 322 to the fourth word 324 of the remote read parcel header stored in the parcel header register 38 are sent to the interprocessor network 2 as the fourth word 175 to the sixth word 177 of the remote read packet. This completes the remote read parcel sending process in the processor A101. It should be noted that the transmitting device 13 uses one parcel header 22 in the normal header queue 20.
Each time the processing is completed, the normal header queue offset register 32 is increased by one header. As a result, the free area of the normal header queue 20 increases, but in order to avoid an increase in access frequency to the memory 12, the normal last pointer 26 is not updated every time the normal header queue offset register 32 is updated.

The remote read packet 171 from the processor A 101 arriving at the processor B 201 is stored in the FIFO memory 56 in the receiving device 214 of the processor B 201. The sequencer 55 notified of the arrival of the packet from the FIFO memory 56 stores the first word 172 and the second word 173 of the packet in the FIFO memory 56.
Read out from and stored in the packet header register 57. The sequencer 55 inspects the first word 172 of the packet and recognizes that this is the remote read packet 171. Then, the remote write parcel header 270, which is the portion of the packet body of 4 words following the 3rd word of the packet, can be calculated by the combination of the remote read header queue base address register 50 and the header queue offset register 51. Top remote read parcel header queue 22
Write to address 1. Then, the remote read header queue offset register 51 is increased by one header. This completes the processing of the remote read packet 171 in the receiver 214 of the processor B201.

Here, the body of the packet 171 of remote read of 4 words (parcel header of remote write)
When writing 270, the value of the remote read header queue offset register 51 and the value of the remote read last pointer 52 are the same.
If it is determined in step 3, the sequencer 55 sets the value obtained by subtracting 1 in the −1 circuit 54 from the value of the remote read header queue offset register 35 of the transmission device 213 as the latest last pointer 52 for remote read. Then, the judgment result of the comparator 53 is checked again.
If the comparison result does not change even after updating, it indicates that the remote read parcel header queue 221 is almost full, and therefore an interrupt is generated to the CPU 211 to request exception processing.

When the remote read header queue offset register 51 in the receiver 214 is updated as described above, the value of the remote read header queue offset register 51 and the remote read header queue offset in the transmitter 213 are updated. Since the value of the register 35 is different from that of the register 35, the comparator 36 informs the sequencer 37 of the comparison result indicating the non-coincidence, and the sequencer 37 recognizes that the transmission is requested. The sequencer 37 uses the header queue base address register 3 for remote read.
4 and the value of the remote read header queue offset register 35, the parcel header 270 is read from the remote read parcel header queue 221 on the memory 212 and stored in the parcel header register 38. Next, the sequencer 37 uses 1 of the parcel header 270.
The word number is checked to recognize that this is the remote write parcel header 270 in the remote read parcel header queue 221. The sequencer 37 then processes the parcel in the same way as a normal remote write parcel header. That is, a remote write packet header is created, and from the address of the memory 212 indicated by the source address of the third word of the parcel header 270, the word number indicated by the second word is changed to the destination number indicated by the fourth word. , 274 of remote write to be written in the Nation address are created and sent to the interprocessor network 2. However, what is different from the normal remote write is that the first word of the last packet 274 is designated to write a log in the log buffer 127 after the reception of this packet is completed. It should be noted that the transmission device 13 increments the value of the remote read header queue offset register 35 by one header each time it finishes processing one parcel header 270.

Remote write packets 271, ..., 274 sent from the transmitter 213 of the processor B201
Is received by the receiver 114 of the processor A101. The reception device 114 processes each remote write packet and writes the sent data 273 to the destination address 272 specified in the packet header. In the final processing of the packet 274, after the packet body is written, the reception is completed in the log buffer 127 on the memory 112 pointed to by the log buffer address register 59 in the reception device 114 (that the remote read is completed). Is written and the value of the log buffer address register 59 is incremented by 1.

The communication library of the processor A101 is
After confirming that the remote read completion is written in the log buffer 127 on the memory 112, the library call is exited and the control of the CPU 111 is passed to the user program.

[0042]

As described above, according to the present invention, the following effects can be obtained.

The first effect is that the time required for remote reading can be shortened. The reason is that the remote read process is performed by the user process (the user program and the communication library called by the user process), not by the OS system call, and therefore the context switch need not be performed at the time of calling. Further, even in the destination processor, the processing is performed only by the receiving device and the transmitting device without passing through the CPU, so that it is not necessary to cause an interrupt to the CPU, and the overhead due to the interrupt in the destination processor, which is a problem in the conventional technology, is eliminated. Because. That is, since the overhead at the above two locations is eliminated, the time required for remote read is shortened.

The second effect is by the remote lead.
The original processing at the destination processor is not interrupted. The reason is that the receiver of the destination processor interprets the remote read packet sent, writes the remote write packet sent as its body directly to the packet header queue on the memory, and processes it for the transmitter. Because it demands. The remote read process in the destination processor does not require any CPU, so the original process in the destination processor is not interrupted.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the remote read according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of various parcel headers and a packet generated from them.

FIG. 4 is a block diagram of a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor 2 ... Inter-processor network 10 ... Bus 11 ... CPU (Central Processing Unit) 12 ... Memory 13 ... Transmitter 14 ... Receiver 20 ... Normal parcel header queue 21 ... Remote read parcel header queue 22 ... Parcel header 23 ... Parcel body 24 ... Normal header queue base address register 25 ... Copy of normal header queue offset register 26 ... Normal last pointer 27 ... Log buffer 30 ... Normal header queue base address register 31 ... Normal header queue offset register 32 ... normal header queue offset register 33 ... normal header queue offset registers 31, 3
Comparator 34 for comparing the values of 2 ... Header queue base address register for remote read 35 ... Header queue offset register for remote read 36 ... Comparator for comparing the values of header queue offset registers 35, 51 for remote read 37 ... Transmitting device Sequencer 38 ... Parcel header register 39 ... First word of remote read parcel header 40 ... TLB of transmitter 50 ... Header queue base address register for remote read 51 ... Header queue offset register for remote read 52 ... Last pointer for remote read 53 ... comparator 54 for comparing the value of the remote read header queue offset register with the value of the remote read last pointer 54 ... decrementer (-1 circuit) 55 ... receiver sequencer 56 ... FIFO Memory 57 ... Packet header register 58 ... Receiving device TLB 59 ... Log buffer address register 101 ... Processor A 111 ... Processor A CPU 112 ... Processor A memory 113 ... Processor A transmitting device 114 ... Processor A receiving device 120 ... Normal parcel header queue 127 of processor A ... Log buffer of processor A 128 ... Message buffer of processor A 160 ... Parcel header of remote read message 161 ... Packet of remote read message 162 ... Destination processor number; Processor B 163 ... Message Type; remote read 164 ... number of words read by remote read 165 ... start address read by remote read 166 ... processor number that returns remote read result;
Processor A 167 ... Memory address for writing remote read result 170 ... Remote read parcel header 171 ... Remote read packet 172 ... First word of remote read packet 173 ... Second word of remote read packet; Number of packet words 4 words 174 ... Remote 3rd word of read packet; 1st word of remote write packet 175 ... 4th word of remote read packet 176 ... 5th word of remote read packet 177 ... 6th word of remote read packet 201 ... Processor B 211 ... Processor B CPU 212 ... Memory of processor B 213 ... Transmission device of processor B 214 ... Reception device of processor B 220 ... Parcel header queue 221 for normal use of processor B 221 ... Remote processing of processor B Parcel header queue for reading 228 ... Message buffer of processor B 260 ... Remote write parcel header 261 ... Parcel header of remote read completion message 262 ... Remote write packet 263 ... Destination address of remote write packet 264 ... Main body of remote write packet (data ) 265 ... Remote read completion message packet 270 ... Read / write parcel header 271 ... Remote write packet for sending remote read result 272 ... Destination address specified in remote write packet 273 ... Remote write packet body (data) 274 ... Last remote write packet for sending remote read result 300 ... General parcel header 301 ... General parcel 1st word 302 ... 2nd word of general parcel header 303 ... 3rd word of general parcel header 304 ... 4th word of general parcel header 305 ... General packet 306 ... 1st word of general packet 307 ... 2nd word of general packet 308 ... 3rd word of general packet 309 ... Packet body of general packet 310 ... Parcel header of remote write 311 ... 1st word of parcel header of remote write 312 ... Parcel header of remote write Second word 313 ... Remote write parcel header third word 314 ... Remote write parcel header fourth word 315 ... Remote write packet 316 ... Remote write packet first word 317 ... Remote write packet 2 Word 3 8 ... 3rd word of remote write packet 319 ... Remote write packet body 320 ... Remote read parcel header 321 ... Remote read parcel header 1st word 322 ... Remote read parcel header 2nd word 323 ... Remote 3rd word of read parcel header 324 ... 4th word of remote read parcel header 325 ... Remote read packet 326 ... 1st word of remote read packet 327 ... 2nd word of remote read packet 328 ... Remote write parcel header 329 ... 3rd word of remote read packet 330 ... 4th word of remote read packet 331 ... 5th word of remote read packet 332 ... 6th word of remote read packet

Claims (4)

[Claims] 1. In a system in which a plurality of processors each having a CPU, a memory, a transmitting device and a receiving device are connected via an inter-processor network, a user process running on the CPU of a certain processor is different. In a remote read processing method for reading data stored in a memory of a processor, in the remote read source processor, the user process includes a read processor number, a read word number,
After writing the remote read parcel header containing the read address and write address to the parcel header queue in the memory of the local processor and requesting the transmitter of the local processor to send it, the log buffer in the memory of the local processor is polled for remote In the step of waiting for the completion of read, in the remote read source processor, the transmission device requested to transmit reads the remote read parcel header from the parcel header queue on the memory of the self processor, and the self processor number as the destination processor number, A remote read having a remote write parcel header as a packet body in which the read word count is set as the number of words, the read address is set as the source address, and the write address is set as the destination address. Of the remote read packet to the destination processor via the interprocessor network, and the receiving device of the processor that has received the remote read packet via the interprocessor network at the remote read destination processor receives the remote read packet. Writing the remote write parcel header, which is the packet body of the packet, to the parcel header queue on the memory of the own processor and requesting the transmitter of the own processor to send the packet; and the transmission requested by the remote read destination processor. The device reads the remote write parcel header from the parcel header queue in the memory of its own processor, processes it, generates a series of remote write packets, and processes the remote read source processor via the interprocessor network. In the remote read source processor, the receiving device that receives a series of remote write packets, which is a response to the remote read via the inter-processor network, receives the data contained in the body of the received remote write packet. Storing in the memory of the processor itself and writing the fact that the remote read is completed to the log buffer on the memory of the processor when the last packet is received. 2. The user process writes a remote read parcel header into the parcel header queue on the memory of its own processor, and then sets the value of the normal header queue offset register indicating the write position of the parcel header queue for one header. By requesting transmission by updating, the transmission device of the remote read source processor recognizes that there is a request for transmission by detecting that the value of the normal header queue offset register has been updated, The receiving device of the remote read destination processor writes the remote write parcel header to the parcel header queue on the memory of its own processor, and then sets the value of the remote read header queue offset register indicating the write position of the parcel header queue to 1 header. Sent by updating the minutes And the transmission device of the remote read destination processor recognizes that there is a transmission request by detecting that the value of the remote read header queue offset register has been updated. The remote read processing method according to claim 1. 3. A process when a user process running on a CPU of a remote read source processor reads data stored in a memory of a remote read destination processor connected to the processor via an interprocessor network. In the remote read processing device under the control of the remote read source processor, the user process stores a remote read parcel header including a read processor number, a read word number, a read address and a write address in a parcel header queue on its own memory. In response to the transmission request issued after writing to, the remote read parcel header is read, the destination processor number is the own processor number, the word number is the read word number, and the source address is the read address. And a remote read source transmission device that transmits a remote read packet having the write address as the destination address and the remote write parcel header set as the packet body to the remote read destination processor via the interprocessor network, and the remote read source. The remote read destination receiving device, which is provided in the destination processor, writes the remote write parcel header, which is the packet body of the received remote read packet, to the parcel header queue on the memory of the local processor and requests the transmission, and the remote read destination processor. The remote read destination receiving device is provided with a transmission request, reads a remote write parcel header from the parcel header queue, processes the packet, and processes a series of remote write packets. A remote read destination transmission device that is configured to transmit the data to the remote read source processor via the interprocessor network, and the data included in the main body of the received remote write packet provided in the remote read source processor and stored in the memory of the local processor. In addition, the remote read processing device further comprises a remote read source receiving device that writes the fact that the remote read is completed to the log buffer on the memory of its own processor when the last packet is received. 4. The normal read header queue offset register, wherein the remote read source transmitter indicates a write position of a parcel header queue for writing a remote read parcel header, and is updated by one header by a user process after writing the remote read parcel header. And a means for recognizing that the transmission has been requested by updating the value of the normal header queue offset register, the remote read destination receiving device is remote to the parcel header queue on the memory of its own processor. After writing the write parcel header, the remote read destination transmission device further comprises means for requesting transmission by updating the value of the remote read header queue offset register indicating the next write position of the parcel header queue by one header. Is the 4. The remote read processing device according to claim 3, further comprising means for recognizing that the transmission has been requested by updating the value of the header queue offset register for mote read.