JP3115801B2 - Parallel computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer system, and more particularly, to a configuration of a multiprocessor computer system with high cost performance in a multiprocessor computer system aiming at high-speed execution of a program.

[0002]

2. Description of the Related Art Conventionally, regarding multifunctional networks in a multiprocessor computer system, IEICE Technical Report CPSY91-26, Vol.91, No.130, "Architecture and Performance Evaluation of Highly Parallel Computer AP1000" Reference 1). This parallel computer system has the configuration shown in FIG.

FIG. 7 shows a barrier synchronization protocol and a general-purpose S
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system configuration diagram according to the related art including two protocols of an END protocol, wherein A, B, C, and D are processors, 107 is a barrier synchronization network, 108 is a network, 1 is an instruction processor, and 2 a memory control circuit. Reference numeral 3 denotes a memory, 48 denotes a network interface circuit, and 49 denotes a barrier synchronization control circuit.

In a multiprocessor, a plurality of processors share and execute processing. Barrier synchronization means that when one processor reaches the execution of a particular instruction, it stops processing and waits for another processor to reach the same stage, so that only one processor does not go too far.
When a plurality of processors reach the same stage, the processing is restarted all at once. Thus, the processing is synchronized between the plurality of processors.

[0005] The technique of the above-mentioned Document 1 describes that high-speed network processing is realized by providing a plurality of networks for each application in a parallel computer system, but emphasizing only the high-speed performance of the network. No consideration is given to the cost performance of massively parallel systems.

As a result, the network function has been dramatically improved. However, since the cost performance of the network has not been considered, three networks having the same data transfer throughput are provided. As a result, the number of cables to be used and the number of LSI (Large Scale Integrated Circuit) mounted cards are doubled, resulting in twice the cost.

[0007] Further, regarding virtual channel control for improving network throughput when a plurality of packets coexist, IEEE, Transactions on Parallel A
nd Distributed Systems 1992 Vol.3, No.2, `` Virtual-Ch
annel Flow Control "(Dally) (hereinafter referred to as Reference 2).

[0008]

According to the technique disclosed in Document 2, it is possible to connect a plurality of buffers having substantially the same scale to one physical network, and to logically configure a plurality of networks efficiently. It has been described. The technique of Literature 2 aims at improving the system throughput by transferring a plurality of packets having the same urgency and packet length from those that can be processed. No consideration is given to the urgency of barrier synchronization for synchronization between multiple processors. Furthermore, there is no urgency such as barrier synchronization, and there is no consideration on the cost performance of transfer control hardware when packets with a short packet length are mixed. Although this has the effect of reducing contention for a large number of packets at a relatively low cost, the barrier switching time and the processing for writing to the register file increase the barrier synchronization processing time and complicate the processing. was there.

An object of the present invention is to provide a technique capable of realizing multifunctional network control with good cost performance in a network-connected multiprocessor computer system.

[0010]

SUMMARY OF THE INVENTION A typical one of the inventions disclosed in the present application will be briefly described as follows.

In a parallel computer system in which a plurality of processors are connected by a network, a transmission line for transmitting packets is provided with an interrupt signal line for realizing a virtual channel for changing the arrival order between packets. The interrupt signal line transmits an interrupt signal indicating that the top of the packet to be prioritized exists on the transmission line. Using the leading bits of the packet specified by the interrupt signal, the purpose of the packet is identified. For example, 4
When handling packets of various priorities, at least one interrupt signal line is required since identification is performed using the plurality of bits. Therefore, cost performance is achieved by reducing the number of transmission lines in the network by increasing the number of functions of the network control circuit and reducing the number of cables connecting processor boards in the system.

Further, the priority control circuit which sets the barrier synchronization packet to the highest priority performs a normal communication packet process having a variable packet length of several thousand bytes immediately in a fixed cycle corresponding to the barrier synchronization packet length. Stop by the number, and transfer with priority given to barrier synchronization processing. Accordingly, the barrier synchronization processing, in which the overall processing time is determined by the processing time of the slowest processor among many processors, is speeded up by several thousand times, and the processing time of the user program including the barrier synchronization is reduced.

Further, by providing a dedicated priority path for passing a fixed-length packet with the highest priority, such as a barrier synchronization packet, without writing it into a buffer, the transfer time is shortened and the circuit is simplified.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION In all the drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated explanation will be omitted. In addition, various storage units that can be changed by those skilled in the art can be used for each unit of a memory, a flip-flop, and a register referred to in the following description without departing from the gist of the present invention.

In the parallel computer system of this embodiment, a plurality of processors A, B, C and D are connected via a network 105 as shown in FIG. Processor A,
B, C, and D have the same configuration. In FIG.
The internal configuration of only the processor A is shown, and the display of other processor configurations is omitted.

In FIG. 1, processors A, B, C, D
Are instruction control circuits 1A, 1B, 1C, 1D, memory control circuits 2A, 2B, 2C, 2D, memories 3A, 3B, 3
C, 3D, network interface circuits 4A, 4
B, 4C and 4D. Note that 1B, 1C, 1D, 2
B, 2C, 2D, 3B, 3C, 3D, and 4B, 4C,
4D is not shown in FIG.

Further, the network interface circuit 4A in the processor A has a transmission control circuit 401A and a reception control circuit 402A. Similarly, the network interface circuit 4B in the processor B has a transmission control circuit 401B and a reception control circuit 402B. Similarly, the network interface circuit 4C in the processor C includes a transmission control circuit 401C and a reception control circuit 402
C. Similarly, the network interface circuit 4D in the processor D has a transmission control circuit 401D and a reception control circuit 402D. Processors B, C, D
Has the same configuration as the processor A, so the transmission control circuit 40
1B, C and D and the reception control circuits 402B, C and D are not shown in FIG.

The network 105 has a transmission control circuit 411A corresponding to the reception control circuit 402A in the processor A. Further, the network 105 has a reception control circuit 412A corresponding to the transmission control circuit 401A in the processor A. The reception control circuit 402A has the same structure as the reception control circuit 412A. The transmission control circuit 401A has the same structure as the transmission control circuit 411A.

The transmission control circuit 40 of the processor A
The data transmitted from 1A is received by the reception control circuit 412A in the network 105. Conversely, data transmitted from the transmission control circuit 411A in the network 105 is received by the reception control circuit 402A in the processor A.

The transmission control circuits 401B, 401C, and 401D in the processors B, C, and D and the reception control circuit 4
02B, 402C, and 402D, similarly to the transmission control circuit 401A and the reception control circuit 402A, the reception control circuits 412B, 412C, 412D, and the transmission control circuit 4
11B, 411C and 411D are provided correspondingly in the network. The reception control circuit 412B (412C,
412D) and the transmission control circuit 411B (411C, 4C).
11D) has the same configuration as the reception control circuit 402A and the transmission control circuit 401A, respectively.

Here, the transmission control circuits 411A, 411B, 411C, and 411D in the network 105 transmit data to arbitrary reception control circuits 412A, 412B, 412C, and 412D in the network 105 via the switch 550.

Further, the reception control circuit 402A includes a normal reception buffer queue 50A and a barrier synchronous reception control circuit 60A.
A is provided. Although not shown, the reception control circuits 402B, 402C, 402D, 412A, 41
2B, 412C, and 412D also include a normal reception buffer queue and a barrier synchronization reception control circuit, similarly to the reception control circuit 402A.

FIGS. 2 and 3 show the configuration of a network control circuit which handles the barrier synchronization and the normal protocol according to the present embodiment in these two drawings. Indicated by.

In FIGS. 1, 2 and 3, 10-13
Denotes a buffer ID switching signal line (interrupt signal line). In response to the buffer ID switching signal (interrupt signal) of this signal line, the reception control circuit 402B controls the switching between the normal reception buffer queue 50B and the barrier synchronous reception control circuit 60B, and the transmission control circuit 401A transmits through.

In the network 105, a switch 55 is connected from the reception control circuit 412A to the transmission control circuit 411B.
Conveyed via 0. (In FIGS. 2 and 3, the switch 55 is used.
0 is simplified. When the barrier control is necessary, the instruction control circuit switches from the normal reception buffer queue to the barrier synchronization reception control circuit by controlling the buffer ID switching signal, thereby stopping the transmission of the normal data and the barrier synchronization packet. By passing through a barrier synchronous reception control circuit as a priority packet, normal data can be overtaken and transmitted.

Since this operation is performed in all the reception control circuits on the transmission path from the transmission side to the reception side, the normal data transmission is interrupted once and the barrier synchronization packet can be transferred. After the transfer of the barrier synchronization signal, the transmission of the normal data is resumed by returning the buffer switching signal again.

19 is a memory store (register store) control signal line, 20 to 23 are data and buffer ID signal lines, and 24 is a register load signal line. 28 is a barrier synchronization start register and 29 is a barrier synchronization completion report register.

Numerals 30 to 33 denote data transmission signal lines;
2 is a buffer entry release signal line (release signal line), 5
1 is a read address pointer, 52 is a write address pointer, 53 is a receive buffer, and 58 is a read control comparator.

Reference numeral 61 denotes a barrier synchronization packet transfer flip-flop, 62 denotes a control signal generation flip-flop, 70 denotes a priority control circuit (OR gate), and 97 denotes a reception buffer empty entry number up / down counter.

500 is an inter-processor synchronization report generation circuit,
501A and 501B are inter-processor synchronization flip-flops, 502 is an inter-processor synchronization AND circuit, 511 is a read address adder, and 521 is a write address adder.

In this embodiment, two systems of a barrier synchronization protocol and a general-purpose SEND protocol are provided in one physical network.
For example, when a remote memory access protocol having an intermediate priority between the two is added, and the memory of another processor in the system can be read and written with a fixed-length packet, the further description will be given. A high signal number reduction effect can be obtained.

In this embodiment, as shown in FIGS. 2 and 3, a message packet transmitted from the transmission control circuit 401A of the processor A is transferred to the reception control circuit 412A of the network 105 and described in the packet. The transmission control circuit 411B of the network selected according to the transmission destination processor number is switched to the reception control circuit 402B of the second processor. It is assumed that a message packet arriving at the processor is written to an address in the reception area on the processor memory in the same procedure as in the related art.

The transmission control circuit 401A is provided with an up / down counter 97 for calculating the number of empty entries in the destination receiving buffer.

From the barrier synchronization start register 28, a signal having a value of 1 is output to the signal line 10 when the head of the barrier synchronization packet is transmitted. The up / down counter 97 has a memory 3
A send signal (data transmission signal) having a value of 1 every time data is sent to the read data signal line 20 from A
In response, the value of the register 98 is decremented (−1). On the other hand, 1
An entry is sent out, and a release signal (buffer entry release signal) which is returned each time the buffer becomes empty is signal line 41.
, The counter 97 increments (+1) the value of the register 98.

The reception control circuits 402B and 412A include reception buffer queues 50A and 50B for temporarily storing normal message packet data, barrier synchronization reception control circuits 60A and 60B, and occupy three data lines in this embodiment. And a priority control circuit including a control signal generation flip-flop 62 and a priority control circuit (OR gate) 70 for generating a control signal for a selector that transfers a barrier synchronization packet with priority.

The reception buffer queues 50A and 50B include a reception buffer 53, a write address pointer 52, an address adder 521 for updating the pointer, a read address pointer 51, an address adder 511 for updating the read address pointer 51, and a read operation. A comparator 58 compares the value of the pointer 51 with the value of the write pointer 52 and sends a read control signal line (data transmission signal) 33 when it is not empty.

The barrier synchronization reception control circuits 60A and 60B include a flip-flop 61 for transferring barrier synchronization packet data.

The data and buffer ID signal from transmission control circuit 412A are applied to decode circuit 510A. The decoding circuit decodes a plurality of leading bits of the transferred packet, and identifies a use. The decoding circuit 510A determines whether the transmitted packet is a barrier synchronization packet or not, and transfers the packet to the inter-processor synchronization flip-flop 501A if the packet is a barrier synchronization packet. If it is not a barrier synchronization packet, the packet is sent to the multiplexer 503 via the signal line 504A. Decode circuit 51
The same thing as 0A is also provided in another transmission control circuit (the decoding circuit 510B is connected to the transmission control circuit 412B).

Signal line 560 from transmission control circuit 412A
Are connected to a signal line 570 via a circuit (not shown).

When the process reaches a certain stage, the instruction control circuit 1A sets the value 1 to the barrier synchronization start register 28 to start the barrier synchronization process, and transmits the barrier synchronization packet via the signal line 20. Forward. This packet will be referred to as a synchronization report packet. The synchronization report packet is stored in the inter-processor synchronization flip-flop 501A via the transmission control device 401A, the signal line 21, and in the network 105 via the reception control circuit 412A.

The synchronization report packet is repeatedly transferred from the instruction control circuit at a specific cycle together with the buffer ID switching signal (the value of the register 28). Synchronization is established, and is repeatedly generated until the instruction control circuit receives a synchronization establishment packet described later. The buffer ID switching signal is transferred via the signal lines 10 and 11 together with the synchronization report packet.

When the processing reaches a specific stage from another instruction control circuit, the barrier synchronization processing is started in the same manner as the instruction control circuit 1A. For example, also in the instruction control circuit 1B, when the processing reaches a certain stage, the synchronization report packet is accumulated in the inter-processor synchronization flip-flop 501B via the reception control circuit 412B. Inter-processor synchronization flip-flops are similarly provided for other instruction control circuits (not shown), and when reports from all processors are accumulated, a new inter-processor synchronization report generation circuit 500 A barrier synchronization packet is generated, and the accumulated information is cleared. This new barrier synchronization packet will be referred to as a synchronization establishment packet. Multiplexer 5
Reference numeral 03 indicates that the synchronization established packet is transferred instead of the normal packet from the signal lines 504A and 504B and other transmission control circuits due to the satisfaction of the condition in the AND circuit 502. The barrier synchronization packet has a length of three cycles as described later. The data of the first cycle indicates the purpose, but the data of the remaining two cycles includes identification information indicating whether the packet is a synchronization report packet or a synchronization establishment packet. In.

This synchronization establishment packet is broadcast to all processors that have started barrier synchronization processing. For example, in the reception control circuit 402B of the processor B,
The normalization packet is bypassed and the synchronization establishment packet is passed to the processor to the memory control unit, and the processor updates the value of the barrier synchronization completion report register 29 from which the processor repeatedly reads out the synchronization establishment report. The establishment of synchronization is similarly reported for other processors.

Transmission control circuit 401A and reception control circuit 41
Buffer ID switching signal lines 10 to 13 and data and buffer ID signal lines 20 to 23 are added to the wiring connecting 2A and the wiring connecting the transmission control circuit 411B and the reception control circuit 402B. That is, signal lines 10 to 13 for instructing a change in the packet priority are provided in addition to the signal lines forming the data transfer path conventionally used.

Next, the operation of the network control circuit of this embodiment will be described.

Now, in FIGS. 2 and 3, it is assumed that data is transmitted from the instruction control circuit 1A to the instruction control circuit 1B.

(1) The storage control circuit 2A on the transmission side uses a memory store (register store) control signal line 19 from the instruction control circuit 1A to transmit a normal message packet stored in advance at a specified address on the memory 3A. Start sending. The transmission control circuit 401A determines that the value of the empty entry number counter 97 of the destination buffer is "+"
Permitted when transmission data is sent from memory.
The message packet data is transmitted from the signal line 20 to the signal line 2
It is passed to 1 and the value of the counter 97 is decremented.

(2) The reception control circuit 412A in the network 105 sends the data to the reception buffer 53 via the signal line 21 and writes it to the address 0, and increments the write pointer by the send signal line (data transmission signal) 31. Set the value to “1”. Hereinafter, reception processing is performed by the signal line 31 and the data signal line 21. As soon as the transmission control circuit 411B at the next stage of the reception control circuit 412A becomes empty, the data read from the reception buffer address 0 is sent to the transmission control circuit 411B, the value of the read pointer 51 is incremented, and the transmission source (transmission The release signal line (buffer entry release signal) 41 of the buffer entry is returned to the circuit 411A).

(3) The transmission control circuit 411B, which has received the data from the reception control circuit 412A, performs data transfer in the same procedure as in the above item (1). Hereinafter, similarly, by transmitting and receiving data from the circuit to the next circuit,
The message transfer on the network 105 is performed.

(4) The reception control circuit 402B on the receiving side receiving the data from the network 105 performs the data transfer in the same procedure as in the above item (2).

(5) The instruction control circuit 1B detects the completion of the message transfer to the memory 3B by the register load control 24.

It is assumed that a barrier synchronization packet is sent during data transmission described in (1) to (5) above. When transferring the barrier synchronization packet, the newly provided buffer ID switching signal lines 10 to 13 are used.
In the processor A, when the barrier synchronization is started during the normal data transfer from the storage control circuit 2A, the normal data transfer is interrupted, the buffer ID switching signal is set to the register 28 and transferred via the signal line 10, and the data is transferred. Data for barrier synchronization (synchronization report packet) is transmitted from the line.

While the buffer ID switching signal is set on the buffer ID switching signal line 10, normal data is not transferred, and data transmitted on the data line during this time is data for barrier synchronization (packet synchronization). ). Since the data line is configured with a plurality of bit widths, by giving a meaning to the value sent from the data line, for example, changing the priority of barrier synchronization or giving a meaning other than barrier synchronization It is also possible.

In the reception control circuit 412A, the internal three flip-flops 6
2 and the circuit 70 form a signal line 71 for controlling the selector so that the synchronization report packet can be preferentially transferred on the data line for three cycles.

The signal 71 for controlling this selector gives
Transmission of normal data from the reception buffer 53 is interrupted for a period of three cycles, and a synchronization report packet is output from the barrier synchronization reception control circuit 60B instead. The decoder circuit 510A determines whether the transmitted packet is a barrier synchronization packet or not, and if the packet is a barrier synchronization packet, the packet is transferred to the inter-processor synchronization flip-flop 501A.

On the other hand, when the reports from all the processors are accumulated, the AND condition is satisfied at the AND gate 502,
The inter-processor synchronization report generation circuit 500 generates a new barrier synchronization packet and clears the accumulated information. The synchronization establishment packet is broadcast to all processors that have started barrier synchronization processing. At this time, it should be noted that the buffer ID switching signal is transferred to each processor together with the synchronization establishment packet from the processor performing the barrier synchronization processing. Normally, the buffer ID switching signal is not transferred to the transmission control circuit 411B by the operation of the gate 508.

The transmission control circuit 411B bypasses the synchronization establishment packet and transfers it to the reception control circuit 402B. At this time, the buffer ID switching signal also passes through the AND gate, and is transferred together with the synchronization establishment packet to the processor that should receive the synchronization establishment packet.

In the reception control circuit 402B, the buffer ID
The switching signal is received via the signal line 12, and the three flip-flops 62 and the circuit 7 in the reception control circuit 402B are received.
With 0, a signal line 71 for controlling the selector is created so that the synchronization report packet can be preferentially transferred on the data line for three cycles.

The signal 71 for controlling the selector gives
The transmission of normal data from the reception buffer 53 is interrupted for a period of three cycles, and instead, the transmission of a synchronization establishment packet from the barrier synchronization reception control circuit 60B is performed.

FIG. 4 is a time chart of the barrier synchronization packet transfer during the normal packet transfer according to the present embodiment. In particular, the case where the processor A of the plurality of processors finally starts the barrier synchronization processing and transfers the synchronization report packet is shown. Assuming that the instruction control circuit 1A transfers a 3-cycle barrier synchronization packet (synchronization report packet) after transferring the nth data of the normal packet, the synchronization report packet is transmitted by the transmission control circuit 401.
A, it is stored in the synchronization start flip-flop 501A via the reception control circuit 412A. Since it is assumed that the other processor has already started the barrier synchronization processing, the synchronization report packet has already been accumulated in the synchronization start flip-flop corresponding to the other processor. For this reason,
Since the condition of the AND gate 502 is satisfied, the inter-processor synchronization flip-flop is reset and a synchronization report packet is generated from the synchronization report generation circuit 500.

The synchronization report is sent to the transmission control circuits 411A and 411B in the network. For example, the packet being processed by the transmission control circuit 411B in the network is interrupted at the k-th element, and the reception control circuit in the processor is transmitted. At 402B, the processing is interrupted at the j-th position (j ≦ k).
As described above, the barrier synchronization packet (synchronization report packet, synchronization establishment packet) is processed prior to the normal packet, so that the barrier synchronization processing can be performed in a short time.
If each reception and transmission control circuit requires two cycles, the barrier synchronization processing can be completed in ten cycles.

The data line between 401A and 412A is 9
Bits or 64 kilobytes of data transfer.
Request a kilocycle. Exceeding these two packets saves more than 100 kilocycles and ending the processing in 10 cycles is equivalent to a 10 kilofold speedup.

According to the configuration of this embodiment, the output of the storage control circuit 2A in the processor A, for example, the transmission packet processing during the DMA transfer is interrupted at the n-th element, and the interrupt signal line 10 is set to the value "1". In this example, by sending a value “4” to the packet head data 20,
The barrier synchronization packet for the cycle can be sent immediately.

This overtaking control is also repeated at the output of the transmission control circuit 401A of the processor, and the same packet m
It is interrupted at the (m ≦ n) th element. The interruption processing can be realized by a method generally used as a path contention circuit arbitration, and when the signal line 330 in the reception control circuit 402B is output, the SEND signal line 33 is connected so as to be suppressed.

The synchronization report packet from the reception control circuit 412A is transmitted to the synchronization start flip-flop 501A. When the condition of the AND gate 502 is satisfied, the inter-processor synchronization flip-flops 501A and 501B are reset, and the synchronization establishment packet is transmitted to the synchronization report generation circuit 500.
Generate from

The establishment of synchronization is output to the transmission control circuits 411A and 411B in the network. For example, a packet being processed by the transmission control circuit 411B in the network is interrupted at the k-th element, and the reception control circuit in the processor is stopped. At 402B, the processing is interrupted at the j-th position (j ≦ k).

As described above, in this embodiment, the barrier synchronization is achieved by adding one signal line without doubling the number of cables and the number of network boards as in the prior art of the above-mentioned Document 1. A network is realized.

In the present embodiment, similarly to the technique of the above-mentioned document 2, the barrier synchronization processing time is reduced by changing the packet arrival so that the barrier synchronization packet does not wait for the transfer of the normal packet to end. Reduced to one thousandth.

Further, in this embodiment, the barrier synchronization packet is fixed length and written into the flip-flop to bypass the high-density but low-speed storage means of the register file and the like, so that the network transfer time can be further reduced and a large-scale network for that purpose can be obtained. Unnecessary buffer.

Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, but may be variously modified without departing from the gist thereof. Of course.

In this embodiment, a new synchronization establishment packet is generated when the synchronization report packet from each processor is aligned with the synchronization flip-flop. It may be modified so that such a priority packet (hereinafter, referred to as a general priority packet) is transferred from one processor to another processor as it is at the time of communication.

FIGS. 5 and 6 show another embodiment in which such a modification is made. FIGS. 5 and 6 show the configuration of the network control circuit that handles the barrier synchronization and the normal protocol according to the present embodiment in these two drawings, and shows the connection relationship of the signal lines with alphabets surrounded by circles. I have.

Not only does the first bit of the packet indicate whether it is a barrier synchronization packet or a normal packet, but it is set so that it is not a barrier synchronization packet but a priority packet that has priority over other packet communications. Is done. The instruction control circuit transfers the buffer ID switching signal to the signal line 10 when transferring the priority packet. The difference from the configurations of FIGS. 2 and 3 is that the decoding circuit (51
0A, 510B) can further decode the priority packet, and the function of transferring the value 1 to the signal lines (506A, 506B) when the priority packet is decoded is added as a function. However, the priority packet is sent to the multiplexer 503 via the signal line 504A (or 504B) like the normal packet. Further, an OR circuit 507 is provided, and the AND circuit 502 and the signal lines 506A and 506 are provided.
The signal of B (the connection between the signal line 506B and the OR circuit 507 is not shown for simplification of the drawing) is logically ORed. As a result, the priority packet is transferred to the processor to be transferred together with the buffer ID switching signal. The priority packet passes through the reception control circuit and the transmission control circuit in preference to the normal packet, and is exchanged between the instruction control circuits in the same manner as the barrier synchronization packet.

[0074]

The interrupt signal line added as a transmission line informs that one additional packet head is to be sent, and a plurality of bits at the head of a packet sent from a normal data transfer line are used for identification of use. A barrier synchronization network can be realized only by adding one line.

Further, the priority control circuit which sets the barrier synchronization packet as the highest priority transfers the barrier synchronization processing in preference to the normal communication packet, so that the processing of the slowest processor among a large number of processors can be performed. Since the barrier synchronization processing in which the overall processing time is determined by the time is accelerated, the processing time of the user program including the barrier synchronization can be reduced.

Furthermore, since the barrier synchronization packet is written to the flip-flop as a fixed length and bypasses a highly integrated but low speed storage means such as a register file, the network transfer time is further shortened, and a buffer for the network transfer is reduced to several tens per receiver circuit. Bytes can be made unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a parallel computer system provided with a network according to the present invention.

FIG. 2 is a block diagram, combined with FIG. 3, showing a schematic configuration of an embodiment of a network control circuit that handles a barrier synchronization and a normal protocol according to the present embodiment;

FIG. 3 is a block diagram showing a schematic configuration of an embodiment of a network control circuit for handling barrier synchronization and a normal protocol according to the embodiment, which is combined with FIG. 2;

FIG. 4 is a time chart of barrier synchronization packet transfer during normal packet transfer according to the embodiment.

FIG. 5 is a block diagram, combined with FIG. 6, illustrating a schematic configuration of an embodiment of a network control circuit that handles a priority packet in addition to a barrier synchronization packet and a normal packet according to another embodiment.

FIG. 6 is a block diagram, combined with FIG. 5, showing a schematic configuration of an embodiment of a network control circuit for handling a priority packet in addition to a barrier synchronization packet and a normal packet according to another embodiment.

FIG. 7 is a block diagram showing a schematic configuration of a conventional parallel computer system including a dedicated network for a barrier synchronization protocol and a general-purpose SEND protocol;

[Explanation of symbols]

1A, 1B, 1C, 1D: Instruction control circuit 2A, 2B, 2C, 2D: Memory control circuit 3A, 3B, 3C, 3D: Memory 4A, 4B, 4C, 4D: Network interface circuit 401A, 401B, 401C, 401D ... Transmission control circuits 402A, 402B, 402C, 402D ... reception control circuits 105 ... networks 411A, 411B, 411C, 411D ... transmission control circuits 412A, 412B, 412C, 412D ... reception control circuits 50A, 50B ... normal reception buffer queues 60A, 60B ... Barrier synchronization reception control circuit 19 ... Memory store control signal line 20-23 ... Data and buffer ID signal line 24 ... Register load signal line 28 ... Barrier synchronization start register 29 ... Barrier synchronization completion report register 30-33 ... Data transmission signal line 40-4 ... buffer entry release signal line (release signal line) 51 ... read address pointer 52 ... write address pointer 53 ... receive buffer 58 ... read control comparator 61 ... barrier synchronization packet transfer flip-flop 62 ... control signal creation flip-flop 70 ... priority Degree control circuit (OR gate) 97... Up / down counter of the number of empty entries in reception buffer 500... Inter-processor synchronization report generation circuit 501 A, 501 B... Inter-processor synchronization flip-flop 502. Write address adder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/177 676

Claims (3)

(57) [Claims] 1. A plurality of processors connected by a network
Parallel computer system,
A packet transmission line having a
A path that bypasses the
A signal line of an interrupt signal attached to the packet;
In response to the signal line interrupt signal, the corresponding packet is
A selector for switching to the bypass is provided.
The transmitter issues a priority packet to the transmission line and
Means for transferring an embedded signal to the signal line,
Processors advance their processing to a predetermined extent.
In other words, the synchronization report packet is transmitted as a priority packet as described above.
Originating on a transmission line, the network comprising the plurality of processors;
Provided that it receives a synchronization report packet from
And a transmission packet for each of the transmission lines
And a transfer to the signal line.
Stem. 2. A plurality of processors, said plurality of processors.
Network for transmitting packets from the server
A parallel computer system, wherein each processor has the network
A transmission circuit for transferring a packet to a network,
A receiving circuit for receiving packets from the network.
Each receiving circuit has a multi-stage buffer for storing the packet.
And a path that bypasses the packet buffer,
To select the buffer or the bypass
Each transmitting circuit and each receiving circuit
And the network further interrupts the packet
And a signal line for transmitting only the signal, and the transmitting circuit has another signal line.
For priority packets to be transmitted prior to
Means for transferring an interrupt signal to a signal line;
The circuit responds to the interrupt signal of the signal line and responds
A selector for switching a packet to the bypass,
The plurality of processors each have a predetermined degree.
When the process proceeds, the corresponding transmission circuit
Notification packet as a priority packet to the transmission line.
The network further instructs the synchronization establishment packet.
A synchronous report packet from a plurality of processors.
The synchronization establishment packet on condition that the
Transfer to the transmission line and the signal line respectively
A parallel computer system characterized by: 3. The plurality of processors and the plurality of processors.
Network for transmitting packets from the server
A parallel computer system, wherein each processor has the network
A transmission circuit for transferring a packet to a network,
A receiving circuit for receiving packets from the network.
Each receiving circuit has a multi-stage buffer for storing the packet.
And if the buffer is not full with packets,
A means for issuing a packet transfer request to the network
A path bypassing the packet buffer;
Decide whether to select the buffer or the bypass
Means for transmitting, wherein each of the transmitting means is the network
Via the receiving circuit of the packet destination
It has a means to send a packet when it receives a transfer request,
Each transmitting circuit, each receiving circuit, and the network are connected to each other.
Signal line that transmits the interrupt signal attached to the packet
And the transmitting circuit transmits the packet in preference to other packets.
Interrupt signal on the signal line for the priority packet
Transferring means, wherein the receiving circuit is configured to divide the signal lines.
The corresponding packet in response to the
Parallel selector having selector for switching to
Computer system.