JP2017010319A - Arithmetic processing device, information processing device, and information processing device control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten read-out latency for processing object data.SOLUTION: An arithmetic processing device 10A connected with another arithmetic processing device 10B includes: a processing unit 11A for generating a readout request for processing object data; a communication unit 14A for transmitting the readout request to the other arithmetic processing device 10B and for receiving a data block including the processing object data corresponding to the transmitted readout request from the other arithmetic processing device 10B; a buffer 141 for storing the data block; a writing unit 142 for sequentially writing multiple pieces of unit data included in the data block received by the communication unit 14A in the buffer; and a reading unit 143 for preferentially reading out the processing object data, i.e. at least one of the multiple pieces of unit data from the buffer 141.SELECTED DRAWING: Figure 1

Description

  The present case relates to an arithmetic processing device, an information processing device, and a control method for the information processing device.

  An information processing apparatus such as a PC (Personal Computer) or a server includes an arithmetic processing apparatus such as a CPU (Central Processing Unit) that performs arithmetic processing on data read from a memory. In such an information processing apparatus, the latency until the CPU receives response data corresponding to the read request after the fetch request, which is a read request to the memory, is issued from the CPU that is the endpoint is an important factor in processing performance. It is one of the factors.

  Further, as the information processing apparatus, a multiprocessor system in which a plurality of CPUs are connected so as to communicate with each other may be used. In such a multiprocessor system, in recent years, as shown in FIG. 14, for example, a plurality of CPUs and routers are connected to each other via a network using high-speed serial transmission. By adopting high-speed serial transmission, high communication throughput can be realized.

JP 2010-124448 A JP 2010-116228 A

  By the way, in a network using high-speed serial transmission, a transmission error is checked by CRC (Cyclic Redundancy Check). When a transmission error is detected, the end of the packet is rewritten to EDB (end bad). Therefore, the endpoint (CPU) cannot determine whether or not the packet is normal unless it receives all the data up to the end of the packet including the response data.

  Therefore, in the CPU that has issued the fetch request, all the data up to the end of the packet including the response data corresponding to the fetch request is temporarily stored in the reception buffer, and then the data in the reception buffer is processed in order from the top. Sent out.

  However, since the reception buffer is a FIFO (First In First Out), the processing target data requested by the CPU core (one unit data; for example, 8-byte data) is read from the reception buffer immediately before the unit data. Wait until data is read. For this reason, when viewed from the CPU core, communication latency may increase and processing performance may deteriorate.

  In one aspect, an object of the invention disclosed in this specification is to shorten a read latency of data to be processed.

  The arithmetic processing device of the present case is connected to another arithmetic processing device, and includes a processing unit, a communication unit, a buffer, a writing unit, and a reading unit. The processing unit generates a read request for processing target data. The communication unit transmits a read request generated by the processing unit to the other arithmetic processing device and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device. To do. The buffer stores the data block. The writing unit sequentially writes a plurality of unit data included in the data block received by the communication unit to the buffer. The reading unit preferentially reads the data to be processed, which is at least one of the plurality of unit data, from the buffer.

  According to one embodiment, it is possible to shorten the read latency of data to be processed.

It is a block diagram which shows the structure of the information processing apparatus containing the arithmetic processing unit (CPU) as 1st Embodiment and 2nd Embodiment of this invention. It is a figure explaining packet routing in the case of making a fetch request from one CPU to another CPU in the information processing apparatus of the first embodiment. It is a figure which shows the format of the header of the fetch response packet in 1st Embodiment. It is a block diagram which shows the structure (a writing part and a reading part) which concerns on the receiving buffer contained in the router in 1st Embodiment, and the packet writing / reading process with respect to the said receiving buffer. FIG. 5 is a block diagram showing in detail a configuration (reading unit) related to the packet reading process shown in FIG. 4. 6 is a flowchart illustrating an operation of a configuration (reading unit) related to the packet reading process illustrated in FIG. 5. 6 is a time chart illustrating an operation when the configuration (reading unit) according to the packet reading process illustrated in FIGS. 4 and 5 first reads tenth data according to the flowchart illustrated in FIG. 6. (A) is a figure which shows the format of the header of the fetch request packet in 2nd Embodiment, (B) is a figure which shows the format of the header of the fetch response packet in 2nd Embodiment. It is a figure explaining packet routing in the case of making a fetch request from one CPU to another CPU in the information processing apparatus of the second embodiment. It is a block diagram which shows the structure (a writing part and a reading part) which concerns on the receiving buffer contained in the router in CPU of 2nd Embodiment, and the packet write / read process with respect to the said receiving buffer. It is a block diagram which shows in detail the structure (reading part) which concerns on the packet reading process shown in FIG. 12 is a flowchart illustrating an operation of a configuration (reading unit) related to the packet reading process illustrated in FIG. 11. 12 is a time chart showing an operation when the configuration (reading unit) related to the packet reading process shown in FIG. 10 and FIG. 11 reads the second, sixth, tenth and fourteenth data first in accordance with the flowchart shown in FIG. It is a block diagram which shows an example of a structure of a multiprocessor system (information processing apparatus). It is a block diagram which shows an example of a structure of a multi-core processor (CPU, arithmetic processing unit). FIG. 15 is a diagram illustrating packet routing when a fetch request is made from one CPU to another CPU in the multiprocessor system shown in FIG. 14. (A) is a figure which shows the format of a packet without data, (B) is a figure which shows the format of a packet with data. (A) is a figure which shows the format of the header of a fetch request packet, (B) is a figure which shows the format of the header of a fetch response packet. FIG. 16 is a block diagram showing a configuration relating to a reception buffer included in a router and a packet writing / reading process for the reception buffer in the CPU (multi-core processor) shown in FIG. 15. 20 is a flowchart for explaining the operation of the configuration related to the packet writing process shown in FIG. 19. 20 is a flowchart for explaining the operation of the configuration related to the packet reading process shown in FIG. 20 is a time chart showing an operation in the shortest case in the configuration related to the packet writing / reading processing shown in FIG. FIG. 20 is a time chart showing an operation when the end of the received packet is EDB in the configuration related to the packet writing process shown in FIG. 19. FIG.

  Hereinafter, embodiments of an arithmetic processing device, an information processing device, and a control method for the information processing device disclosed in the present application will be described in detail with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment. Each figure is not intended to include only the components shown in the figure, and may include other functions. And each embodiment can be suitably combined in the range which does not contradict a processing content.

[1] Technology Related to the Present Embodiment First, the technology related to the present embodiment will be described with reference to FIGS.
In recent years, in a multiprocessor system (information processing apparatus), a high-speed serial transmission network (see reference numeral 30 in FIG. 16) is used between a plurality of CPUs and routers to achieve high communication throughput. ). FIG. 14 is a block diagram illustrating an example of a configuration of a multiprocessor system.

  In recent years, a multi-core processor incorporating a plurality of cores is generally used as the CPU. Here, an example of the configuration of each CPU (multi-core processor, arithmetic processing unit) 10 constituting the multiprocessor system shown in FIG. 14 will be described with reference to FIG. FIG. 15 is a block diagram illustrating an example of the configuration of the CPU 10.

  As shown in FIG. 15, in the CPU 10, a plurality of cores 11 are connected via a shared cache (tertiary cache) 12. In FIG. 15, the core 11 includes N + 1 cores # 0 to #N (N is an integer equal to or greater than 1). In FIG. 15, a primary cache (not shown) and a secondary cache (not shown) are built in each core 11, and a tertiary cache is used as the shared cache 12. However, a primary cache is built in each core 11, A secondary cache may be used as the shared cache 12.

  In addition to the core 11, a MAC (Memory Access Controller) 13 and a router (Router) 14 are connected to the shared cache 12. The MAC 13 is connected to a DIMM (Dual Inline Memory Module) 20 that functions as a main memory, and functions as a control unit that controls data exchange with the DIMM 20. The router 14 is connected to another CPU 10 or another router (for example, an LSI (Large Scale Integrated circuit) for routing), and functions as a communication unit that performs data communication with the other CPU 10 by a packet.

  In such a CPU 10, consider a case where one of the cores 11 requests reading (fetching) of memory data (when issuing a fetch request). The core 11 designates an address indicating 8-byte data (processing target data) required by the core 11 and first accesses a cache (primary cache, secondary cache) built in the core 11. As a result, when the core 11 hits the cache, the core 11 reads the 8-byte data from the internal cache.

  On the other hand, when a cache miss occurs in the built-in memory, the core 11 accesses a shared cache (tertiary cache in FIG. 15) 12 shared by a plurality of cores. However, if a cache miss occurs in the shared cache 12, the main memory 20 is accessed. Since the cache line size of the shared cache 12 is, for example, 128 bytes, the MAC 13 is requested to read a 128-byte data block including 8-byte processing target data requested by the core 11.

  Next, the core 11 has memory data (for example, 8-byte memory) in another CPU 10 (for example, CPU # 1 in FIGS. 14 and 16) different from the CPU 10 (for example, CPU # 0 in FIGS. 14 and 16) to which the core 11 belongs. A case of requesting reading of (processing target data) will be described with reference to FIG. FIG. 16 is a diagram for explaining packet routing when a fetch request is made from one CPU # 0 to another CPU # 1 in the multiprocessor system shown in FIG.

  In this case, as shown in FIG. 16, the core 11 in the CPU # 0 transmits the fetch request packet to the other CPU # 1 via the router 14 and the network 30. Receiving the fetch request packet, the CPU # 1 reads a data block including the requested memory data (8-byte processing target data) from the DIMM 20 of the CPU # 1, and sends back the data block as a fetch response packet. The size of the data block at this time is 128 bytes.

  Here, the fetch request packet and the fetch response packet will be described with reference to FIGS. 17 (A) and 17 (B). FIG. 17A is a diagram showing the format of a packet without data (fetch request packet), and FIG. 17B is a diagram showing the format of a packet with data (fetch response packet).

  The packet includes a packet without data as shown in FIG. 17A and a packet with data as shown in FIG. The fetch request packet transmitted from CPU # 0 to CPU # 1 is a no-data packet, and the fetch response packet for the fetch request packet is a packet with data. The head cycle of the packet is a header (HD) on which information for determining the content and destination of the packet is placed.

  Further, the header of the fetch request packet and the fetch response packet will be described with reference to FIGS. 18 (A) and 18 (B). FIG. 18A is a diagram showing the format of the header of the fetch request packet, and FIG. 18B is a diagram showing the format of the header of the fetch response packet.

  As shown in FIG. 18A, the header of the fetch request packet includes an Opcode (opcode; OPC) indicating the type of packet, a physical address (physical address; PA or pa) of memory data requested by the core 11, and the like. , Information such as Request ID (RQID), which is an identifier for identifying a packet, is included. As shown in FIG. 18B, the header of the fetch response packet includes information such as OPC and RQID. RSV (reserve) is an unused bit.

  As shown in FIG. 17B, the 128-byte data block including the processing target data requested by the core 11 is divided into 8-byte data after the header and transmitted over 16 cycles. In the fetch response packet, 8-byte data in each cycle corresponds to data Data0, Data1,..., DataF at physical addresses pa [6: 3] = 0000, 0001,.

  The CPU # 0 (router 14) that has received the fetch response packet from the CPU # 1 registers the data block attached to the fetch response packet in the shared cache 12 of the CPU # 0 and to the core 11 that has made the fetch request. send.

  On the other hand, a transmission error between the CPUs # 0 and # 1 is detected by checking the CRC attached to the packet at the packet receiving side. When a transmission error is detected, the packets after the packet in which the transmission error is detected are discarded, and a NACK (Negative ACKnowledgement) is sent using DLLP (Data Link Layer Packet), so that the packet of the packet is sent to the sending CPU # 1. A resend is requested.

  When a packet in which a transmission error is detected cannot be discarded at the relay point (router; see FIG. 14) or the receiving CPU # 0, the packet is sent with the end of the packet as EDB.

  The router 14 in the receiving CPU # 0 temporarily stores the fetch response packet received from the other CPU # 1 in a buffer (see reference numeral 141 in FIG. 19) in the router 14 concerned. This buffer is called a reception buffer. The reception buffer is a FIFO buffer. Here, with reference to FIGS. 19 to 23, the reception buffer 141 and packet writing / reading processing for the reception buffer will be described.

  FIG. 19 is a block diagram showing a configuration relating to reception buffer 141 included in router 14 and packet writing / reading processing to reception buffer 141 in CPU 10 shown in FIG. As shown in FIG. 19, on the write side of the reception buffer 141, WDR (Write Data Register), HDWP (Header Write Pointer) and WP (Write Pointer) are provided. Is provided. On the reading side of the reception buffer 141, an RDR (Read Data Register) and an RP (Read Pointer) are provided.

  The WDR is a register that temporarily stores write target data (one unit data; for example, 8-byte data) to be written in the reception buffer 141. The WP controls writing of a write target packet, and is a pointer that specifies a write destination address in the reception buffer 141 of write target data stored in the WDR. WP is set to 0 in the initial state, and is incremented by 1 every cycle when the write target packet is written to the reception buffer 141. The write target data stored in the WDR is written at an address specified by the WP. HDWP is a pointer that specifies the address of the header of the write target packet, and is set to 0 in the initial state.

  The RDR is a register that temporarily stores read data (one unit data; for example, 8-byte data) read from the reception buffer 141. The RP controls reading of data from the reception buffer 141 and is a pointer for designating an address of data read from the reception buffer 141. RP is set to 0 in the initial state, and is incremented by 1 every cycle when data is read from the reception buffer 141. Data at the address specified by the RP is read from the reception buffer 141, temporarily stored in the RDR, registered in the shared cache 12 as described above, and transmitted to the core 11 that has made the fetch request.

  The operation of the configuration related to the packet writing process shown in FIG. 19 (router 14 in CPU # 0) will be described according to the flowchart shown in FIG. 20 (steps S101 to S107). The router 14 waits for reception of the header (HD) or data (DT) at the time of packet writing (NO route of step S101), and receives the header (HD) or data (DT) (YES route of step S101). ), It is determined whether an EDB has been received (step S102).

  If the EDB has not been received (NO route in step S102), the router 14 determines whether or not an END indicating the final cycle of the packet has been received (step S103). When END is received (YES route in step S103), the router 14 sets WP + 1 as a value for designating the head address (header address) of the next write target packet in the HDWP (step S104). Thereafter, the router 14 writes the data (or header) in the WDR to the entry of the reception buffer 141 specified by the WP (step S105), increments the WP by 1 (step S106), and performs the process of step S101. Return to.

  If it is determined in step S102 that an EDB has been received (YES route), the router 14 sets HDWP in the WP (step S107), and returns to the processing in step S101. As a result, the current write target packet (packet with EDB set at the end) is written again to the reception buffer 141 in order from the head (header).

  Next, the operation of the configuration (router 14 in CPU # 0) related to the packet reading process shown in FIG. 19 will be described according to the flowchart shown in FIG. 21 (steps S111 to S113). The router 14 determines whether or not the RP value matches the HDWP value (step S111). If the RP value matches the HDWP value (YES route in step S111), the router 14 determines that the write target packet is being written, and returns to the process in step S111.

  If the RP value and the HDWP value do not match (NO route of step S111), the router 14 determines that the writing of the write target packet has been completed, and starts reading the packet from the reception buffer 141 (FIG. 22 timing T18). That is, the router 14 reads the entry (one unit data) of the reception buffer 141 designated by the RP from the reception buffer 141 via RDR (step S112). Thereafter, the router 14 increments RP by 1 (step S113) and returns to the process of step S111.

  Here, FIG. 22 shows a time chart of the shortest case of writing / reading processing of the fetch response packet with respect to the reception buffer 141. As shown in FIG. 22, in the initial state (see timing T0), WE (Write Enable) and RE (Read Enable) are set to the Low state, and WP, HDWP, and RP are set to 0. The packet writing process is started by setting WE to a high state, and first, the header HD is written to the reception buffer 141 via the WDR (see timing T1).

  Thereafter, each time WP is incremented by 1, 16 pieces of data DT0 to DTF are sequentially written to the reception buffer 141 via the WDR (see timing T2 to T17; refer to steps S105 and S106 from the NO route of step S103 in FIG. 20). ).

  When data DTF and END indicating the last cycle of the packet are received at timing T17, WE is set to the Low state and RE is set to the High state. Accordingly, at timing T18, the value WP + 1 = 17 indicating the header address of the next packet is set as the HDWP value (from the YES route in step S103 in FIG. 20 to step S104). As a result, the HDWP value 17 and the RP value 1 do not match (NO route in step S111 in FIG. 21), and the packet reading process is started. First, the header HD is read from the reception buffer 141 via the RDR ( (See timing T18).

  Thereafter, each time RP is incremented by 1, 16 pieces of data DT0 to DTF are sequentially read from the reception buffer 141 via RDR (see timings T19 to T34; refer to steps S112 and S113 from the NO route of step S111 in FIG. 21). . Such a reading process is executed until the HDWP value and the RP value match at timing T34 (that is, until YES is determined in step S111 in FIG. 21). In the example shown in FIG. 22, the HDWP value and the RP value coincide with each other at the timing T <b> 34.

  As described above with reference to FIGS. 20 to 22, the packet reading process is started after waiting for the last unit data to be written in the final cycle of the packet. This is because the packet needs to be discarded when the last cycle (end) of the packet is EDB.

  Next, FIG. 23 shows a time chart when the end of the received fetch response packet is EDB. FIG. 23 illustrates a case where EDB is detected at the time when the write timing T10 of the packet data DT8 is reached according to the same procedure as in FIG. In this case, at timing T11, the HDWP value (0 in FIG. 23) is stored as the WP value (refer to step S107 from the YES route in step S102 in FIG. 20).

  Thus, the current write target packet (packet with EDB set at the end) is written again to the reception buffer 141 in order from the head (header) without performing the reading process from the reception buffer 141. At that time, a packet with EDB at the end is overwritten by a subsequent packet.

[2] Outline of the Embodiment As described above, in the network 30 based on high-speed serial transmission, a transmission error is checked by the CRC. When a transmission error is detected, the end of the packet is rewritten to EDB. Therefore, the endpoint (CPU # 0) cannot determine whether or not the packet is normal unless it receives all the data up to the end of the packet including the response data (processing target data).

  Therefore, in CPU # 0 that issued the fetch request, all the data up to the end of the packet including the response data corresponding to the fetch request is temporarily stored in the reception buffer 141, and then the data in the reception buffer 141 is the head. Are sent to the core 11 in order.

  However, since the reception buffer 141 is a FIFO, the processing target data (one unit data; for example, 8-byte data) requested by the core 11 is read from the reception buffer 141 by reading the data immediately before the unit data. Wait until. For this reason, the communication latency increases from the viewpoint of the core 11, and the processing performance of the CPU # 0 and the processing performance of the information processing apparatus (multiprocessor system) including the CPU # 0 may decrease.

  For this reason, in a multiprocessor system connected by a high-speed serial transmission network 30, it is desired to shorten the read latency of processing target data requested by the core 11.

  Therefore, in the present embodiment (first and second embodiments), for example, of the 128-byte data block in the fetch response packet read and transferred from the other CPU 10, the 8-byte required by the core 11 is used. The processing target data is first read from the reception buffer 141 and sent to the core 11. As a result, the communication latency (read latency of processing target data) viewed from the core 11 is shortened.

  That is, in the information processing apparatus according to the first embodiment to be described later, all response packets to the fetch request are written in the reception buffer 141 of the endpoint, as in the related art described above. The end point is a receiving CPU 10A (see FIG. 1; first arithmetic processing unit, CPU # 0) that is connected to the high-speed serial transmission network 30 and receives a fetch response packet. However, in the information processing apparatus according to the first embodiment, as will be described later with reference to FIGS. 1 to 7, after the packet is written, when the packet is read from the reception buffer 141, Instead, the 8-byte processing target data requested by the core 11 is read first.

  Since the information processing apparatus according to the first embodiment, which will be described later, first reads 8-byte processing target data requested by the core 11, the fetch response packet includes a physical address (pa [6] indicating the processing target data requested by the core 11. : 3]) (see FIGS. 2 and 3). In addition, in the end point, HDRP (header read pointer), Length register, and CycleCT (cycle counter), which will be described later, are added to the configuration related to the packet read processing of the related technology described above (see RP and RDR in FIG. 19). (See the reading unit 143 in FIGS. 4 and 5). By controlling the RP using the HDRP, Length register, and CycleCT, it is possible to first read 8-byte processing target data requested by the core 11 (see FIGS. 5 to 7).

  In this way, the read latency is shortened by reading from the reception buffer 141 with the processing target data requested from the core 11 of the CPU 10A as the head. For example, when the processing target data requested by the core 11 is the tail end of the packet, the processing target is read first, so that the latency can be shortened by [the number of cycles of the data portion of the packet−1]. Conversely, if the data to be processed is at the beginning of the packet, the latency does not change. That is, the number of cycles for shortening the latency varies depending on what number of data the processing target data is. Therefore, on average, it is possible to reduce the latency by about [number of cycles of the data portion of the packet-1] / 2.

  In the second embodiment to be described later with reference to FIG. 1 and FIGS. 8 to 13, in the stride access generated by matrix calculation or the like, necessary unit data (processing target data) is included in one packet with data. This is a technique corresponding to the case where there are a plurality of. When an array is handled by matrix calculation or the like, the core 11 requests a plurality of unit data at addresses having a fixed interval shorter than the packet length, and the plurality of unit data is included in one packet.

  In such a case, in the second embodiment, when a packet is read from the reception buffer 141, a plurality of necessary unit data are sent before being packed (front side) before the other unit data, and the necessary plurality of unit data are transmitted. These unit data are read before other unit data. Thereby, the latency seen from the core 11 of the CPU 10A is greatly shortened.

[3] Information processing apparatus according to the first embodiment With reference to FIG. 1, the configuration of an information processing apparatus (multiprocessor system) 1 including arithmetic processing units (CPUs) 10A and 10B according to the first embodiment of the present invention. explain. FIG. 1 is a block diagram showing the configuration.

  As shown in FIG. 1, the information processing apparatus 1 according to the first embodiment is a multiprocessor system having a plurality (two in FIG. 1) of CPUs 10A and 10B, such as a PC and a server. The CPU 10A corresponds to the first arithmetic processing unit, and may be referred to as a receiving CPU or CPU # 0. Further, the CPU 10B corresponds to a second arithmetic processing unit and may be referred to as a transmitting CPU or CPU # 1. Although the information processing apparatus 1 according to the first embodiment includes two CPUs, the present invention is not limited to this, and may include three or more CPUs.

  The CPU 10A and the CPU 10B are connected to be communicable with each other via a network 30 based on high-speed serial transmission.

  The CPU 10A is a multi-core processor incorporating a plurality of cores 11A, as with the CPU 10 shown in FIG. In the CPU 10A, a plurality of cores 11 are connected via a shared cache (tertiary cache) 12A. In FIG. 1, as the core 11A, N + 1 cores # 0 to #N (N is an integer equal to or greater than 1) are provided. In FIG. 1, a primary cache (not shown) and a secondary cache (not shown) are built in each core 11, and a tertiary cache is used as the shared cache 12A, but a primary cache is built in each core 11A. A secondary cache may be used as the shared cache 12A.

  In addition to the core 11A, a MAC 13A and a router 14A are connected to the shared cache 12A. The MAC 13A is connected to a DIMM 20A that functions as a main memory, and functions as a control unit that controls data exchange with the DIMM 20A. The router 14A is connected to another CPU 10B or another router (for example, an LSI for routing; see FIG. 14), and functions as a first communication unit that performs data communication with the other CPU 10B by a packet.

  The CPU 10B includes a core 11B, a shared cache (tertiary cache) 12B, a MAC 13B, and a router 14B. The core 11B, shared cache 12B, MAC 13B, and router 14B are the same as the core 11A, shared cache 12A, MAC 13A, and router 14A of the CPU 10A described above, respectively. However, the MAC 13B is connected to a DIMM 20B that functions as a main memory, and functions as a control unit that controls exchange of data with the DIMM 20B. The router 14B is connected to another CPU 10A or another router (for example, a routing LSI; see FIG. 14), and functions as a second communication unit that performs data communication with the other CPU 10A by a packet.

  At least one of the plurality of cores (processing units) 11A in the CPU 10A generates a read request for necessary processing target data (for example, 8-byte unit data). Hereinafter, the read request may be referred to as a fetch request.

  The router (first communication unit) 14A in the CPU 10A transmits a fetch request generated by one core 11A to the CPU 10B by a fetch request packet (see FIGS. 2 and 17A). Further, the router (first communication unit) 14A receives from the CPU 10B a fetch response packet (see FIGS. 2 and 17B) attached with a data block including data to be processed corresponding to the fetch request.

  On the other hand, the router (second communication unit) 14B in the CPU 10B receives the fetch request from the CPU 10A by a fetch request packet (see FIGS. 2 and 17A). Further, the router (second communication unit) 14B transmits a fetch response packet (see FIGS. 2 and 17B) to which the data block including the processing target data corresponding to the fetch request is attached to the CPU 10A.

  In particular, in the first embodiment, the router (second communication unit) 14B of the CPU 10B performs processing extracted from address information (see PA in FIG. 18A) included in the fetch request (the header of the fetch request packet). A response header in which the address information pa [6: 3] of the target data is recorded is attached to the data block. Here, the response header is, for example, a header of a fetch response packet described later with reference to FIG. Then, the router (second communication unit) 14B transmits the data block with the response header to the CPU 10A as a fetch response packet (see FIGS. 2 and 17B).

  The router (first communication unit) 14A of the CPU 10A includes a reception buffer 141, a writing unit 142, and a reading unit 143. In the first embodiment, the reception buffer 141, the writing unit 142, and the reading unit 143 are provided in the router 14A of the CPU 10A, but may be provided in the CPU 10A.

  The reception buffer (buffer) 141 stores a packet with data attached with a data block as unit data (for example, 8 bytes).

  The writing unit 142 sequentially writes a plurality of unit data included in the packet (header and data block) received by the router 14A in the reception buffer 141. As will be described later with reference to FIG. 4, the writing unit 142 of the first embodiment is configured in the same manner as the related technique shown in FIG. 19.

  The reading unit 143 reads from the reception buffer 141 preferentially processing target data that is at least one of the plurality of unit data included in the packet. In particular, the reading unit 143 according to the first embodiment refers to the address information pa [6: 3] of the processing target data recorded in the response header attached to the data block. The reading unit 143 first reads processing target data corresponding to the referenced address information pa [6: 3] from the reception buffer 141, and then sequentially reads unit data other than the processing target data from the reception buffer 141. . The reading unit 143 of the first embodiment is configured as described later with reference to FIGS. 4 and 5, and operates as described later with reference to FIGS. 6 and 7.

  In the first embodiment, the CPU 10A has a function as a first communication unit and functions as a reception buffer 141, a writing unit 142, and a reading unit 143, and the CPU 10B serves as a second communication unit. The case of having a function is described. However, each of the plurality of CPUs 10 </ b> A and 10 </ b> B may have a function as the first and second communication units and a function as the reception buffer 141, the writing unit 142, and the reading unit 143.

  Here, referring to FIG. 2, in the information processing apparatus 1 shown in FIG. 1, packet routing in the case where a fetch request for memory data of another CPU 10B is issued from the core 11A of one CPU 10A will be described.

  In this case, as shown in FIG. 2, a fetch request packet (packet without data) for reading out necessary processing target data is issued / transmitted from the CPU 10A, and the memory 20B holds the processing target data via the network 30. Is routed to the CPU 10B. The CPU 10B that has received the fetch request packet by the router 14B reads the data block including the requested processing target data from the memory 20B, generates a fetch response packet (packet with data), and transmits the fetch response packet to the CPU 10A.

  At this time, the format of the header (response header) of the fetch response packet generated by the CPU 10B is shown in FIG. As shown in FIG. 3, in the first embodiment, a 4-bit physical address pa [6: 3] capable of specifying unit data (processing target data) to be fetched is placed in the header of the fetch response packet. Yes. The 4-bit physical address pa [6: 3] is requested by the core 11A on the CPU 10A side out of which unit data (for example, 16 8-byte data) in the data block included in the fetch response packet. This is information for identifying whether or not

  When the CPU 10B generates the fetch response packet, the 4-bit physical address pa [6] that can specify the unit data to be fetched from the physical address PA (see FIG. 18A) included in the header of the fetch request packet. : 3] is taken out. By including the extracted physical address pa [6: 3] in the header described above with reference to FIG. 18B, a response header having a format shown in FIG. 3 is generated. The fetch response packet having the response header generated in this way is routed and transmitted to the CPU 10A that is the issuer of the fetch request, as shown in FIG.

  The fetch response packet received on the CPU 10A side is first written to the reception buffer 141 provided in the router 14A once for each unit data by the writing unit 142 (see FIGS. 1 and 4). Thereafter, by controlling the RP value (address of the unit data to be read) in the reading unit 143 ′, the processing target data requested by the core 11A out of the packet written in the reception buffer 141 is received from the reception buffer 141. Read preferentially. FIG. 4 is a block diagram showing a reception buffer 141 included in router 14A in CPU 10A shown in FIG. 1 and a configuration (writing unit 142 and reading unit 143) relating to packet writing / reading processing with respect to reception buffer 141.

  As shown in FIG. 4, the writing unit 142 of the first embodiment has the same WDR, HDWP, and WP as the configuration related to the packet writing process for the reception buffer 141 of the related technology shown in FIG. In addition to the same RDR and RP as the configuration related to the packet writing process with respect to the reception buffer 141 of the related technique shown in FIG. 19, the reading unit 143 of the first embodiment includes an HDRP (Header Read Pointer). , Length register and CycleCT (Cycle Counter).

  The WDR is a register that temporarily stores write target data (one unit data; for example, 8-byte data) to be written in the reception buffer 141. The WP controls writing of a write target packet, and is a pointer that specifies a write destination address in the reception buffer 141 of write target data stored in the WDR. WP is set to 0 in the initial state, and is incremented by 1 every cycle when the write target packet is written to the reception buffer 141. The write target data stored in the WDR is written at an address specified by the WP. HDWP is a pointer that specifies the address of the header of the write target packet, and is set to 0 in the initial state.

  The RDR is a register that temporarily stores read data (one unit data; for example, 8-byte data) read from the reception buffer 141. The RP controls reading of data from the reception buffer 141 and is a pointer for designating an address of data read from the reception buffer 141. RP is set to 0 in the initial state, and is incremented by 1 every cycle when data is read from the reception buffer 141. Data at the address specified by the RP is read from the reception buffer 141, temporarily stored in the RDR, registered in the shared cache 12A as described above, and transmitted to the core 11 that has made the fetch request.

  HDRP is a pointer indicating the address of the header of the packet being read from the reception buffer 141, and is set to 0 in the initial state. In the Length register, the data length (packet length) Length of the packet being read from the reception buffer 141 is set. The data length Length set in the Length register is generated and set from the Opcode (packet type) in the header by the Length generator 143a (see FIG. 5) when the header is read from the reception buffer 141. CycleCT is a counter indicating what unit data the unit data of the packet being read from the reception buffer 141 is, and is incremented by 1 every cycle, that is, whenever one unit data is read.

  Next, the configuration related to the packet reading process shown in FIG. 4, that is, the reading unit 143 will be described in more detail with reference to FIG. FIG. 5 is a block diagram illustrating a detailed configuration of the reading unit 143. The reading unit 143 shown in FIG. 5 operates as described later with reference to FIGS. 6 and 7. As shown in FIG. 5, the reading unit 143 of the first embodiment includes a length generation unit 143a, 1 adders 143b and 143d, adders 143c, 143e and 143f, and a selector 143g.

  As described above with reference to FIG. 4, the Length generation unit 143 a generates the data length Length of the packet being read from the reception buffer 141 from the Opcode in the header when reading the header from the reception buffer 141. Set in the Length register.

  The 1 adder (+1) 143b adds 1 to a value indicated by HDRP (hereinafter referred to as HDRP).

  The adder 143c adds the data length Length in the Length register and the value HDRP + 1 from the 1 adder 143b, and sets the obtained value HDRP + Length + 1 to HDRP (see step S24 in FIG. 6). The operation timing of the adder 143c is the timing at which the value indicated by CycleCT (hereinafter referred to as CycleCT) becomes the data length Length and resets (initializes) CycleCT (see step S22 in FIG. 6 and timing T34 in FIG. 7). is there.

  The 1 adder (+1) 143d adds 1 to the value indicated by RP (hereinafter referred to as RP).

  The adder 143e adds the physical address pa [6: 3] specifying the processing target data requested by the core 11A and the value RP + 1 from the 1 adder 143d, and obtains the obtained value RP + pa [6: 3] +1. Is set to RP (see step S16 in FIG. 6). The physical address pa [6: 3] is read from the header of the packet being read through the RD-BUS (read bus). The operation timing of the adder 143e is the timing for reading the header from the fetch response packet (YES route in step S15 in FIG. 6; see timing T18 in FIG. 7). At this timing, the selector 143g performs a switching operation so that the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (see (1) in FIGS. 5 to 7).

  The adder 143f adds the data length Length in the Length register and the value HDRP + 1 from the 1 adder 143b, and sets the obtained value HDRP + Length + 1 to RP (see step S23 in FIG. 6). The operation timing of the adder 143f is the timing at which CycleCT becomes the data length Length and resets (initializes) CycleCT (step S22 in FIG. 6; see timing T34 in FIG. 7). At this timing, the selector 143g performs a switching operation so that the value HDRP + Length + 1 obtained by the adder 143f is set to RP (see (4) in FIGS. 5 to 7).

  The selector 143g performs a switching operation so as to set the value RP + 1 obtained by the 1 adder 143d to RP (see (2) in FIGS. 5 to 7). The timing for performing the switching operation is when the Opcode of the header is not a fetch response (see the NO route in step S15 in FIG. 6), or when the RP does not match HDRP + Length (the NO route in step S19 in FIG. 6; FIG. 7). Timing T19 to T23, T25 to T33).

  Further, the selector 143g performs a switching operation so as to set the value HDRP + 1 obtained by the 1 adder 143b to RP (see (3) in FIGS. 5 to 7). The timing for performing the switching operation is the timing at which RP matches HDRP + Length (YES route in step S19 in FIG. 6; see timing T24 in FIG. 7).

  Note that the functions as the writing unit 142 and the reading unit 143 described above may be realized by being incorporated into the CPU 10A in hardware by a logic gate or the like, or incorporated into the CPU 10A as software by executing a program. May be realized.

  Next, the operations of the writing unit 142 and the reading unit 143 configured as described above will be described with reference to FIGS. FIG. 6 is a flowchart for explaining the operation of the configuration (reading unit 143) related to the packet reading process shown in FIG. FIG. 7 is a time chart showing an operation when the configuration (reading unit 143) related to the packet reading process shown in FIGS. 4 and 5 first reads the 10th data (DTA) according to the flowchart shown in FIG.

  The packet writing operation by the writing unit 142 of the first embodiment is the same as the operation of the related art described above with reference to FIG. On the other hand, the packet reading operation by the reading unit 143 of the first embodiment is different from the operation of the related art described above with reference to FIG.

  Here, according to the flowchart shown in FIG. 6 (steps S11 to S24), the packet reading operation by the reading unit 143 of the first embodiment will be described with reference to FIGS.

  The router 14A determines whether or not the RP value matches the HDWP value (step S11). If the RP value matches the HDWP value (YES route in step S11), the router 14A determines that the write target packet is being written, and returns to the process in step S11.

  If the RP value and the HDWP value do not match (NO route in step S11), the router 14A determines that the writing of the write target packet has been completed, and starts reading the packet from the reception buffer 141 (FIG. 7 timing T18). That is, the entry (one unit data) of the reception buffer 141 designated by RP is read from the reception buffer 141 via RDR (step S12). Then, it is determined whether or not the read entry is a header (HD) (step S13).

  At the start of packet reading, the header of the packet is read first, so that the read entry is determined to be a header (YES route in step S13). In this case, the Opcode of the read header is referred to, the data length Length of the packet being read from the reception buffer 141 is generated based on the Opcode (packet type), and the generated data length Length is generated by the reading unit 143. It is set in the Length register (step S14).

  Thereafter, it is determined whether or not the Opcode is a fetch response (step S15). If it is a fetch response (YES route in step S15), the selector 143g performs a switching operation so as to select (1) in FIG. Thus, the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (step S16), and CycleCT is incremented by 1 (step S17). Then, the entry (data DTA) designated by the value (address) set in RP is read (from the NO route in step S11 to step S12). That is, when the header of the packet is read, the address RP + pa [6: 3] +1 of the reception buffer 141 corresponding to the data requested by the core 11A becomes RP based on the physical address pa [6: 3] of the header. Is set. In the example shown in FIG. 7, 11 indicating the address corresponding to the tenth data DTA is set in the RP.

  Thereafter, in the next cycle, the entry read out next to the header is data. In this case (NO route in step S13), it is determined whether or not the value of CycleCT has reached the data length (packet length) Length. (Step S18). That is, it is determined whether or not all data of the read target packet has been read. FIG. 7 shows an example in which Length = 16.

  If CycleCT = Length is not satisfied (NO route of step S18), it is determined whether or not the value of RP has reached the value HDRP + Length (value 16 in FIG. 7) (step S19). If RP = HDRP + Length is not satisfied (NO route in step S19), or if the Opcode of the header is not a fetch response (NO route in step S15), the selector 143g performs a switching operation so as to select (2) in FIG. Thus, every time one unit data is read until the value of RP reaches the value HDRP + Length (see timings T19 to T23 in FIG. 7), the value of RP is incremented by 1 (step S20) and CycleCT is incremented by 1. (Step S17), the process returns to Step S11.

  When the value of RP reaches the value HDRP + Length (YES route in step S19), the selector 143g performs a switching operation so as to select (3) in FIG. Thus, the value HDRP + 1 obtained by the 1 adder 143b is set to RP (step S21), and CycleCT is incremented by 1 (step S17). For example, at timing T24 in FIG. 7, since HDRP = 0, 1 is set in RP. Thereafter, the process returns to step S11.

  In each cycle after setting the value HDRP + 1 in RP (see timings T25 to T33 in FIG. 7), the selector 143g until the value of CycleCT reaches the data length Length, that is, until all the data of the read target packet is read. Performs the switching operation so as to select (2) in FIG. Thus, every time one unit data is read out until the value of CycleCT reaches the data length Length, the value of RP is incremented by 1 (step S20), and after the CycleCT is incremented by 1 (step S17), the process proceeds to step S11. Return to.

  When the value of CycleCT reaches the data length Length (YES route in step S18; see timing T34 in FIG. 7), the value of CycleCT is reset to 0 (step S22). The selector 143g performs a switching operation so as to select (4) in FIG. As a result, the value HDRP + Length + 1 (value 17 in FIG. 7) obtained by the adder 143f is set to RP as the address of data to be read next (step S23). Further, the value HDRP + Length + 1 (value 17 in FIG. 7) obtained by the adder 143c is set to HDRP as the header address of the packet to be read next (step S24). Thereafter, the process returns to step S11.

  With the above operation, in the first embodiment, the data DTA can be read 10 cycles earlier than in the related art shown in FIG. 22, and the latency is shortened.

  In the above-described operation, the order of data to be read is uniquely determined by the physical address pa [6: 3]. Therefore, the core 11A that has received the packet can easily determine which physical address data other than the data read first from the packet in the reception buffer 141 is.

[4] Information Processing Apparatus According to Second Embodiment Next, an information processing apparatus (multiprocessor system) 1 ′ as a second embodiment of the present invention will be described with reference to FIGS. 1 and 8 to 13. The second embodiment described here is a technique corresponding to a case where a plurality of pieces of processing target data exist at a predetermined interval Interval within one data block. That is, as described above, the second embodiment is a technique corresponding to a case where a plurality of necessary unit data (processing target data) exist in one packet with data in stride access generated by matrix calculation or the like. It is. For example, in the example shown in FIG. 13, there are four processing target data DT2, DT6, DTA, and DTE in a packet including 16 pieces of 8-byte data DT0 to DTF with a predetermined interval Interval = 4. explain.

  As shown in FIG. 1, the information processing apparatus 1 ′ of the second embodiment also includes a plurality (two in FIG. 1) of CPUs 10 </ b> A and 10 </ b> B, similarly to the information processing apparatus 1 of the first embodiment. Also in the second embodiment, the CPU 10A and the CPU 10B are connected to be communicable with each other via the network 30 based on high-speed serial transmission.

  The CPUs 10A and 10B in the information processing apparatus 1 ′ are also configured similarly to the CPUs 10A and 10B in the information processing apparatus 1 described above with reference to FIGS. However, in the information processing apparatus 1 ′ according to the second embodiment, as described below, the function as the first communication unit of the router 14A of the CPU 10A and the function as the second communication unit of the router 14B of the CPU 10B. Some changes will be made. In the information processing apparatus 1 ′ according to the second embodiment, the reading unit 143 in the CPU 10A (router 14A) is changed to a reading unit 143 ′ (see FIGS. 1, 10, and 11) as described below. ing.

  Similarly to the first embodiment, the router (first communication unit) 14A in the CPU 10A of the second embodiment also sends a fetch request packet generated by one core 11A to a fetch request packet (see FIGS. 9 and 17A). To the CPU 10B. Further, the router (first communication unit) 14A receives from the CPU 10B a fetch response packet (see FIGS. 9 and 17B) attached with a data block including data to be processed corresponding to the fetch request.

  However, the header of the fetch request packet transmitted from the router (first communication unit) 14A in the CPU 10A of the second embodiment to the CPU 10B has a format as shown in FIG. That is, the header of the fetch request packet includes information related to the predetermined interval (here, a value Interval indicating the predetermined interval) in addition to the OPC, RQID, and physical address PA described above with reference to FIG. It is.

  Further, the router (second communication unit) 14B in the CPU 10B of the second embodiment reads a response header having a format as shown in FIG. 8B from a fetch response packet (DIMM 20B or the like) transmitted to the CPU 10A. Data block). As shown in FIG. 8B, in the response header, the address information pa [of the first process target data extracted from the address information (see PA in FIG. 8A) included in the header of the fetch request packet is included. 6: 3] and a predetermined interval Interval are recorded. The router (second communication unit) 14B transmits the data block with the response header to the CPU 10A as a fetch response packet (see FIGS. 9 and 17B).

  Furthermore, the router (first communication unit) 14A in the CPU 10A of the second embodiment includes a reception buffer 141, a writing unit 142, and a reading unit 143 ′. In the second embodiment, the reception buffer 141, the writing unit 142, and the reading unit 143 ′ are provided in the router 14A of the CPU 10A, but may be provided in the CPU 10A. Since the reception buffer 141 and the writing unit 142 are configured in the same manner as the reception buffer 141 and the writing unit 142 of the first embodiment described above with reference to FIGS. 1 and 4, description thereof is omitted.

  The reading unit 143 ′ refers to the physical address pa [6: 3] of the first process target data and the predetermined interval Interval recorded in the response header attached to the data block (fetch response packet). Based on the physical address pa [6: 3] and the predetermined interval Interval, the reading unit 143 ′ first reads a plurality of processing target data requested by the core 11A from the reception buffer 141, and then Unit data other than the processing target data is sequentially read from the reception buffer 141. The reading unit 143 ′ in the second embodiment is configured as described later with reference to FIGS. 10 and 11, and operates as described later with reference to FIGS.

  In the second embodiment, the CPU 10A has a function as a first communication unit and functions as a reception buffer 141, a writing unit 142, and a reading unit 143 ′, and the CPU 10B serves as a second communication unit. The case of having the function is described. However, each of the CPUs 10A and 10B may have a function as the first and second communication units and a function as the reception buffer 141, the writing unit 142, and the reading unit 143 ′.

  Here, referring to FIG. 9, in the information processing apparatus 1 ′ of the second embodiment, packet routing when issuing a fetch request related to stride access to the memory data of another CPU 10B from the core 11A of one CPU 10A will be described. To do.

  In this case, as shown in FIG. 9, a fetch request packet (packet without data) for reading out necessary processing target data is issued / transmitted from the CPU 10A, and the memory 20B holds the processing target data via the network 30. Is routed to the CPU 10B. At this time, as shown in FIG. 8A, the header of the fetch request packet includes at least address information PA of data to be processed and a predetermined interval Interval related to stride access.

  On the other hand, the CPU 10B that has received the fetch request packet by the router 14B reads the data block including the requested processing target data from the memory 20B, generates a fetch response packet (packet with data), and transmits the fetch response packet to the CPU 10A. To do. At this time, as shown in FIG. 8B, the header (response header) of the fetch response packet generated by the CPU 10B has a 4-bit value that can identify the head unit data (processing target data) to be stride accessed. The physical address pa [6: 3] is listed. Further, as shown in FIG. 8B, a predetermined interval Interval related to stride access is also placed in the header.

  When the CPU 10B generates the fetch response packet, the 4-bit physical address pa [that can specify the head unit data to be fetched from the physical address PA (see FIG. 8A) included in the header of the fetch request packet. 6: 3] is taken out. Further, a predetermined interval Interval related to stride access is extracted from the header. By including the extracted physical address pa [6: 3] and the predetermined interval Interval in the response header, a response header having a format as shown in FIG. 8B is generated. The fetch response packet having the response header generated in this way is routed and transmitted to the CPU 10A that is the issuer of the fetch request, as shown in FIG.

  As described above, in the second embodiment, the interval indicating the address interval when the core 11A performs stride access to the memory 20B is added to both the header of the fetch request packet and the header of the fetch response packet. Here, for example, when the number of unit data (8-byte data) included in the data block (128-byte data) is 16, the value of the predetermined interval Interval is an integer in the range of 0 <Interval <16. This is because when Interval = 0, the same unit data is selected, whereas when Interval = 16, the range of data blocks (16 unit data) included in the packet is exceeded. .

  The fetch response packet received on the CPU 10A side is first written for each unit data by the writing unit 142 (see FIGS. 1 and 10) into the reception buffer 141 provided in the router 14A. After that, by controlling the value of RP (address of unit data to be read) in the reading unit 143 ′, the processing target data requested by the core 11A has priority from the receiving buffer 141 among the packets written in the receiving buffer 141. Read out automatically.

  In particular, the reading unit 143 ′ in the second embodiment performs a plurality of processes requested by the core 11A based on the physical address pa [6: 3] of the first process target data and the predetermined interval Interval recorded in the response header. After the target data is read from the reception buffer 141, other data is sequentially read from the reception buffer 141.

  Hereinafter, the configuration of the second embodiment for realizing the above-described function will be described with reference to FIGS. 10 and 11. FIG. 10 is a block diagram illustrating a reception buffer 141 included in the router 14A in the CPU 10A of the second embodiment and a configuration (a writing unit 142 and a reading unit 143 ′) related to packet writing / reading processing with respect to the reception buffer 141. is there. FIG. 11 is a block diagram showing in detail the configuration (reading unit 143 ′) related to the packet reading process shown in FIG.

  As shown in FIG. 10, the writing unit 142 in the second embodiment has the same WDR, HDWP, and WP as the writing unit 142 shown in FIG.

  Further, the reading unit 143 ′ of the second embodiment includes an Interval register in addition to the RDR, RP, HDRP, Length register, and CycleCT similar to the reading unit 143 shown in FIG. Since the WDR, HDWP, WP, RDR, RP, HDRP, Length register, and CycleCT are the same as those already described, description thereof is omitted.

  In the Interval register added in the second embodiment, when a header (response header) of a fetch response packet is read from the reception buffer 141, a predetermined interval Interval recorded in the header is set. For packets whose packet type is other than the fetch response packet, 1 is set as the value of Interval.

  Next, the configuration related to the packet reading process shown in FIG. 10, that is, the reading unit 143 ′ will be described in more detail with reference to FIG. As shown in FIG. 11, the reading unit 143 ′ of the second embodiment includes a length generator 143a, 1 adders 143b and 143d, adders 143c, 143e and 143f, and a selector similar to the reading unit 143 of the first embodiment. In addition to 143g, it has an adder 143h and a calculator 143i.

  Similar to the first embodiment, when the header is read from the reception buffer 141, the Length generation unit 143a generates the data length Length of the packet being read from the reception buffer 141 from the Opcode in the header, and sets it in the Length register. To do.

  The 1 adder (+1) 143b adds 1 to the value indicated by HDRP, as in the first embodiment.

  Similarly to the first embodiment, the adder 143c adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to HDRP (see step S45 in FIG. 12). ). The operation timing of the adder 143c is the timing at which the value indicated by CycleCT becomes the data length Length to reset (initialize) CycleCT (see step S43 in FIG. 12 and timing T34 in FIG. 13).

  The 1 adder (+1) 143d adds 1 to the value indicated by RP as in the first embodiment.

  Similarly to the first embodiment, the adder 143e adds the physical address pa [6: 3] that specifies the first processing target data requested by the core 11A and the value RP + 1 from the one adder 143d. The value RP + pa [6: 3] +1 is set to RP (see step S37 in FIG. 12). The physical address pa [6: 3] is read via the RD-BUS from the header of the packet being read. The operation timing of the adder 143e is the timing for reading the header from the fetch response packet (YES route in step S36 in FIG. 12; see timing T18 in FIG. 13). At this timing, the selector 143g performs a switching operation so that the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (see (1) in FIGS. 11 to 13).

  Similarly to the first embodiment, the adder 143f adds the data length Length in the Length register and the value HDRP + 1 from the one adder 143b, and sets the obtained value HDRP + Length + 1 to RP (see step S44 in FIG. 12). ). The operation timing of the adder 143f is the timing at which CycleCT becomes the data length Length and resets (initializes) CycleCT (step S43 in FIG. 12; see timing T34 in FIG. 13). At the timing, the selector 143g performs a switching operation so as to set the value HDRP + Length + 1 obtained by the adder 143f to RP (see (4) in FIGS. 11 to 13).

  The adder 143h added in the second embodiment adds the predetermined interval Interval in the Interval register and the value of RP, and sets the obtained value RP + Interval to RP (see step S41 in FIG. 12). The operation timing of the adder 143h is the timing when the Opcode of the header is not a fetch response (see the NO route in step S36 in FIG. 12), or the timing when RP + Interval is equal to or less than HDRP + Length (NO route in step S40 in FIG. Timings T19 to T21, T23 to T25, T27 to T29, and T31 to T32). At the timing, the selector 143g performs a switching operation so as to set the value RP + Interval obtained by the adder 143h to RP (see (2) in FIGS. 11 to 13).

  The computing unit 143i added in the second embodiment is based on the value HDRP + [(RP−HDRP + 1)% Interval based on the predetermined interval Interval in the Interval register, the value HDRP + 1 from the 1 adder 143b, and the value of RP. ] Is set to RP (see step S42 in FIG. 12). The operation timing of the calculator 143i is a timing at which RP + Interval exceeds HDRP + Length (YES route in step S40 in FIG. 12; see timings T22, T26, and T30 in FIG. 13). At the timing, the selector 143g performs a switching operation so as to set the value obtained by the calculator 143i to RP (see (3) in FIGS. 11 to 13). Note that% in the above value is a symbol used for calculation to give a remainder, and is defined as remainder = dividend number% divisor. For example, 16% 4 = 4, 17% 4 = 1, and 14% 4 = 2.

  Note that the functions as the writing unit 142 and the reading unit 143 ′ described above may be realized by being incorporated in the CPU 10A in hardware by a logic gate or the like, or may be realized in the CPU 10A by software by executing a program. It may be implemented by being incorporated.

  Next, the operations of the writing unit 142 and the reading unit 143 ′ configured as described above will be described with reference to FIGS. FIG. 12 is a flowchart for explaining the operation of the configuration (reading unit 143 ′) related to the packet reading process shown in FIG. 13 shows that the configuration (reading unit 143 ′) related to the packet reading process shown in FIGS. 10 and 11 stores the second, sixth, tenth, and fourteenth data (DT2, DT6, DTA, DTE) according to the flowchart shown in FIG. It is a time chart which shows operation | movement in the case of reading previously.

  The packet writing operation by the writing unit 142 of the second embodiment is the same as the operation of the related art described above with reference to FIG. On the other hand, the packet reading operation by the reading unit 143 ′ of the second embodiment is partially different from the operation of the reading unit 143 of the first embodiment described above with reference to FIG.

  A packet reading operation by the reading unit 143 ′ of the second embodiment will be described with reference to FIGS. 11 and 13 according to the flowchart shown in FIG. 12 (steps S31 to S45).

  The router 14A determines whether or not the RP value matches the HDWP value (step S11). If the RP value matches the HDWP value (YES route of step S31), the router 14A determines that the write target packet is being written, and returns to the process of step S31.

  If the RP value and the HDWP value do not match (NO route of step S31), the router 14A determines that the writing of the write target packet has been completed, and starts reading the packet from the reception buffer 141 (FIG. 13 timing T18). That is, the entry (one unit data) of the reception buffer 141 designated by the RP is read from the reception buffer 141 via RDR (step S32). Then, it is determined whether or not the read entry is a header (HD) (step S33).

  At the start of packet reading, the header of the packet is first read, so that the read entry is determined to be a header (YES route in step S33). In this case, the predetermined interval Interval of the read header is referred to, and the value of the Interval from the header is set in the Interval register of the reading unit 143 ′ (step S34). Further, the Opcode of the read header is referred to, the data length Length of the packet being read from the reception buffer 141 is generated based on the Opcode (packet type), and the generated data length Length is generated by the reading unit 143 ′. It is set in the Length register (step S35).

  Thereafter, it is determined whether or not the Opcode is a fetch response (step S36). If it is a fetch response (YES route in step S36), the selector 143g performs a switching operation so as to select (1) in FIG. Thus, the value RP + pa [6: 3] +1 obtained by the adder 143e is set to RP (step S37), and CycleCT is incremented by 1 (step S38). Then, the entry (data DT2) designated by the value (address) set in RP is read (from the NO route in step S31 to step S32). That is, when reading the header of the packet, based on the physical address pa [6: 3] of the header, the address RP + pa [6: 3] of the reception buffer 141 corresponding to the data (first unit data) requested by the core 11A. ] +1 is set to RP. In the example shown in FIG. 13, 3 indicating the address corresponding to the second data DT2 is set in the RP.

  Thereafter, in the next cycle, the entry read next to the header is data. In this case (NO route in step S33), it is determined whether or not the value of CycleCT has reached the data length (packet length) Length. (Step S39). That is, it is determined whether or not all data of the read target packet has been read. FIG. 13 shows an example in which Length = 16.

  If CycleCT = Length is not satisfied (NO route of step S39), it is determined whether or not the value RP + Interval exceeds the value HDRP + Length (value 16 in FIG. 13) (step S40). When RP + Interval is equal to or less than HDRP + Length (NO route of step S40), or when the Opcode of the header is not a fetch response (NO route of step S36), the selector 143g performs the switching operation so as to select (2) in FIG. Do.

  Thus, every time one unit of data is read out until the value of RP + Interval exceeds the value HDRP + Length, the value Interval (Interval = 4 in FIG. 13) is added to the value of RP (Step S41), and CycleCT is incremented by 1 After that (step S38), the process returns to step S31. Note that the execution timing of the process in step S41 corresponds to the timings T19 to T21, T23 to T25, T27 to T29, and T31 to T33 in FIG.

  When the value of RP + Interval exceeds the value HDRP + Length (YES route in step S40), the selector 143g performs a switching operation so as to select (3) in FIG. As a result, the value HDRP + [(RP−HDRP + 1)% Interval] obtained by the calculator 143i is set to RP (step S42), and CycleCT is incremented by 1 (step S38).

  For example, at the timing T22 in FIG. 13, since the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(15−0 + 1)% 4] = 16% 4 = 4, 4 is set in RP. Further, at the timing T26 in FIG. 13, since the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(16−0 + 1)% 4] = 17% 4 = 1, 1 is set in the RP. Similarly, at the timing T30 in FIG. 13, since the value HDRP + [(RP−HDRP + 1)% Interval] = 0 + [(13−0 + 1)% 4] = 14% 4 = 2, 2 is set in RP. . Thereafter, the process returns to step S31.

  Thereafter, when the value of CycleCT reaches the data length Length (YES route in step S39; see timing T34 in FIG. 13), the value of CycleCT is reset to 0 (step S43). Then, the selector 143g performs a switching operation so as to select (4) in FIG. As a result, the value HDRP + Length + 1 (value 17 in FIG. 13) obtained by the adder 143f is set to RP as the address of data to be read next (step S44). Further, the value HDRP + Length + 1 (value 17 in FIG. 7) obtained by the adder 143c is set to HDRP as the header address of the packet to be read next (step S45). Thereafter, the process returns to step S31.

  With the above operation, in the second embodiment, the data DT2, DT6, DTA, and DTE are read before other data, and the latency is shortened.

  In the above-described operation, the order of data to be read is uniquely determined by the physical address pa [6: 3] of the first process target data and the predetermined interval Interval. Therefore, the core 11A that has received the packet can easily determine the physical address of the data other than the data group previously read from the packet in the reception buffer 141.

  The first embodiment described above with reference to FIGS. 1 to 7 corresponds to the case where the value of the predetermined interval Interval of the second embodiment described above with reference to FIGS.

[5] Others While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.

[6] Supplementary Notes The following supplementary notes are further disclosed with respect to the embodiments including the above embodiments.

(Appendix 1)
An arithmetic processing device connected to another arithmetic processing device,
A processing unit for generating a read request for processing target data;
A communication unit that transmits the read request generated by the processing unit to the other arithmetic processing device and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device;
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the communication unit to the buffer;
And a reading unit that preferentially reads out the processing target data that is at least one of the plurality of unit data from the buffer.

(Appendix 2)
The reading unit
Refer to the address information of the processing target data recorded by the other arithmetic processing unit in the response header attached to the data block;
After reading the processing target data corresponding to the address information from the buffer,
The arithmetic processing apparatus according to appendix 1, wherein unit data other than the processing target data is sequentially read from the buffer.

(Appendix 3)
When a plurality of the processing target data exists at predetermined intervals in the plurality of unit data,
The communication unit is
Transmitting the read request including information on the predetermined interval to the other arithmetic processing unit;
The reading unit
With reference to the address information of the processing target data at the beginning recorded by the other arithmetic processing device in the response header attached to the data block and the information on the predetermined interval,
After reading the plurality of processing target data from the buffer based on the address information and the predetermined interval,
The arithmetic processing apparatus according to appendix 1, wherein unit data other than the plurality of data to be processed is sequentially read from the buffer.

(Appendix 4)
A first arithmetic processing unit;
A second arithmetic processing unit connected to the first arithmetic processing unit,
The first arithmetic processing unit includes:
A processing unit for generating a read request for processing target data;
A first request for transmitting the read request generated by the processing unit to the second arithmetic processing unit and receiving a data block including the processing target data corresponding to the transmitted read request from the second arithmetic processing unit. The communication department of
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the first communication unit to the buffer;
A reading unit that preferentially reads out the processing target data that is at least one of the plurality of unit data from the buffer;
The second arithmetic processing unit includes:
A second communication unit that receives the read request from the first arithmetic processing unit and transmits the data block including the processing target data corresponding to the received read request to the first arithmetic processing unit; An information processing apparatus.

(Appendix 5)
The second communication unit in the second arithmetic processing unit is:
A response header that records the address information of the processing target data extracted from the address information included in the read request is attached to the data block,
The information processing apparatus according to appendix 4, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus.

(Appendix 6)
The reading unit in the first arithmetic processing unit is:
Referring to the address information of the processing target data recorded in the response header attached to the data block;
After reading the processing target data corresponding to the address information from the buffer,
The information processing apparatus according to appendix 5, wherein unit data other than the processing target data is sequentially read from the buffer.

(Appendix 7)
When a plurality of the processing target data exists at predetermined intervals in the plurality of unit data,
The first communication unit in the first arithmetic processing unit is:
Transmitting the read request including information on the predetermined interval to the second arithmetic processing unit;
The second communication unit in the second arithmetic processing unit is:
Attaching a response header to the data block, which is recorded with address information of the processing target data extracted from the address information included in the read request, and information regarding the predetermined interval extracted from the read request,
The information processing apparatus according to appendix 4, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus.

(Appendix 8)
The reading unit in the first arithmetic processing unit is:
With reference to the address information of the processing target data at the head recorded in the response header attached to the data block and the information about the predetermined interval,
Based on the address information and the predetermined interval, after reading the plurality of data to be processed from the buffer,
The information processing apparatus according to appendix 7, wherein unit data other than the plurality of data to be processed is sequentially read from the buffer.

(Appendix 9)
A method for controlling an information processing apparatus, comprising: a first arithmetic processing device; and a second arithmetic processing device connected to the first arithmetic processing device,
The first arithmetic processing unit includes:
Sending a read request for processing target data to the second arithmetic processing unit;
The second arithmetic processing unit includes:
When the read request is received from the first arithmetic processing unit, the data block including the processing target data corresponding to the received read request is transmitted to the first arithmetic processing unit,
The first arithmetic processing unit includes:
Receiving a data block including the processing target data corresponding to the read request from the second arithmetic processing unit;
A plurality of unit data included in the received data block are sequentially written to the buffer,
A method for controlling an information processing apparatus, wherein the processing target data that is at least one of the plurality of unit data is preferentially read from the buffer.

(Appendix 10)
The second arithmetic processing unit includes:
A response header that records the address information of the processing target data extracted from the address information included in the read request is attached to the data block,
The control method of the information processing apparatus according to appendix 9, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus.

(Appendix 11)
The first arithmetic processing unit includes:
Referring to the address information of the processing target data recorded in the response header attached to the data block;
After reading the processing target data corresponding to the address information from the buffer,
11. The information processing apparatus control method according to appendix 10, wherein unit data other than the processing target data is sequentially read from the buffer.

(Appendix 12)
When a plurality of the processing target data exists at predetermined intervals in the plurality of unit data,
The first arithmetic processing unit includes:
Transmitting the read request including information on the predetermined interval to the second arithmetic processing unit;
The second arithmetic processing unit includes:
Attaching a response header to the data block, which is recorded with address information of the processing target data extracted from the address information included in the read request, and information regarding the predetermined interval extracted from the read request,
The control method of the information processing apparatus according to appendix 9, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus.

(Appendix 13)
The first arithmetic processing unit includes:
With reference to the address information of the processing target data at the head recorded in the response header attached to the data block and the information about the predetermined interval,
Based on the address information and the predetermined interval, after reading the plurality of data to be processed from the buffer,
13. The information processing apparatus control method according to appendix 12, wherein unit data other than the plurality of data to be processed is sequentially read from the buffer.

1,1 'information processing device (multiprocessor system)
10, 10A, 10B CPU (arithmetic processing unit, multi-core processor)
11, 11A, 11B core (processing unit)
12, 12A, 12B Shared cache (tertiary cache)
13, 13A, 13B MAC
14 router 14A router (first communication unit)
14B router (second communication unit)
141 Receive buffer (buffer)
142 writing unit 143, 143 'reading unit 143a length generation unit 143b, 143d 1 adder (+1)
143c, 143e, 143f, 143h Adder 143g Selector 143i Operation unit 20, 20A, 20B DIMM (main memory)
30 network

Claims (8)

An arithmetic processing device connected to another arithmetic processing device,
A processing unit for generating a read request for processing target data;
A communication unit that transmits the read request generated by the processing unit to the other arithmetic processing device and receives a data block including the processing target data corresponding to the transmitted read request from the other arithmetic processing device;
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the communication unit to the buffer;
And a reading unit that preferentially reads out the processing target data that is at least one of the plurality of unit data from the buffer. The reading unit
Refer to the address information of the processing target data recorded by the other arithmetic processing unit in the response header attached to the data block;
After reading the processing target data corresponding to the address information from the buffer,
The arithmetic processing apparatus according to claim 1, wherein unit data other than the processing target data is sequentially read from the buffer. When a plurality of the processing target data exists at predetermined intervals in the plurality of unit data,
The communication unit is
Transmitting the read request including information on the predetermined interval to the other arithmetic processing unit;
The reading unit
With reference to the address information of the processing target data at the beginning recorded by the other arithmetic processing device in the response header attached to the data block and the information on the predetermined interval,
After reading the plurality of processing target data from the buffer based on the address information and the predetermined interval,
The arithmetic processing apparatus according to claim 1, wherein unit data other than the plurality of processing target data is sequentially read from the buffer. A first arithmetic processing unit;
A second arithmetic processing unit connected to the first arithmetic processing unit,
The first arithmetic processing unit includes:
A processing unit for generating a read request for processing target data;
A first request for transmitting the read request generated by the processing unit to the second arithmetic processing unit and receiving a data block including the processing target data corresponding to the transmitted read request from the second arithmetic processing unit. The communication department of
A buffer for storing the data block;
A writing unit for sequentially writing a plurality of unit data included in the data block received by the first communication unit to the buffer;
A reading unit that preferentially reads out the processing target data that is at least one of the plurality of unit data from the buffer;
The second arithmetic processing unit includes:
A second communication unit that receives the read request from the first arithmetic processing unit and transmits the data block including the processing target data corresponding to the received read request to the first arithmetic processing unit; An information processing apparatus. The second communication unit in the second arithmetic processing unit is:
A response header that records the address information of the processing target data extracted from the address information included in the read request is attached to the data block,
The information processing apparatus according to claim 4, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus. When a plurality of the processing target data exists at predetermined intervals in the plurality of unit data,
The first communication unit in the first arithmetic processing unit is:
Transmitting the read request including information on the predetermined interval to the second arithmetic processing unit;
The second communication unit in the second arithmetic processing unit is:
Attaching a response header to the data block, which is recorded with address information of the processing target data extracted from the address information included in the read request, and information regarding the predetermined interval extracted from the read request,
The information processing apparatus according to claim 4, wherein the data block with the response header is transmitted to the first arithmetic processing apparatus. The reading unit in the first arithmetic processing unit is:
With reference to the address information of the processing target data at the head recorded in the response header attached to the data block and the information about the predetermined interval,
Based on the address information and the predetermined interval, after reading the plurality of data to be processed from the buffer,
The information processing apparatus according to claim 6, wherein unit data other than the plurality of data to be processed is sequentially read from the buffer. A method for controlling an information processing apparatus, comprising: a first arithmetic processing device; and a second arithmetic processing device connected to the first arithmetic processing device,
The first arithmetic processing unit includes:
Sending a read request for processing target data to the second arithmetic processing unit;
The second arithmetic processing unit includes:
When the read request is received from the first arithmetic processing unit, the data block including the processing target data corresponding to the received read request is transmitted to the first arithmetic processing unit,
The first arithmetic processing unit includes:
Receiving a data block including the processing target data corresponding to the read request from the second arithmetic processing unit;
A plurality of unit data included in the received data block are sequentially written to the buffer,
A method for controlling an information processing apparatus, wherein the processing target data that is at least one of the plurality of unit data is preferentially read from the buffer.

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