WO2014206232A1

WO2014206232A1 - Consistency processing method and device based on multi-core processor

Info

Publication number: WO2014206232A1
Application number: PCT/CN2014/080169
Authority: WO
Inventors: 张轮凯; 范东睿; 叶笑春; 王达
Original assignee: 华为技术有限公司
Priority date: 2013-06-26
Filing date: 2014-06-18
Publication date: 2014-12-31
Also published as: CN104252423A; CN104252423B

Abstract

A consistency processing method and device based on a multi-core processor. According to the number of second cores which share target shared data in a multi-core processor, consistency processing is performed on the target shared data by using a directory protocol or a snooping protocol, so that the consistency processing can be performed on the target shared data by using an appropriate protocol. In addition, because using the same protocol to perform the consistency processing on all the target shared data in the multi-core processor is avoided, one part of the shared data uses the snooping protocol, and the other part of the shared data uses the directory protocol, so that not only the directory entry occupied by the shared data which uses the directory protocol in a sparse directory is saved, but also broadcast messages produced by the shared data which uses the directory protocol when performing the consistency processing is saved compared with the prior art, thus the consistency processing efficiency is improved.

Description

Multi-core processor-based consistency processing method and apparatus The present application claims to be submitted to the Chinese Patent Office on June 26, 2013, application number 201310260830.3, and the invention name is "multi-core processor-based consistency processing method and apparatus" Priority of the Chinese Patent Application, the entire contents of which are incorporated herein by reference.

Technical field

The present invention relates to data storage technologies, and more particularly to a consistency processing method and apparatus based on a multi-core processor.

Background technique

A multi-core processor refers to the integration of multiple cores in a single processor. The multi-core processor is connected to an off-chip memory for storing each shared data, and the off-chip memory includes a plurality of data pages, each of which includes a plurality of data blocks. The cores of multicore processors are connected to each other over a network that is used to pass messages between cores. Each core in a multi-core processor includes a processor core, an on-chip cache, a Translation Lookaside Buffer (TLB), and a sparse directory. Before the kernel operates on the shared data in the off-chip memory, the shared data needs to be cached into the kernel's on-chip cache. If at least two cores have the same shared data in the on-chip memory, the on-chip cache is cached. After a kernel writes the cached shared data, the shared data after the write operation is inconsistent with the shared data cached in the rest of the kernel. Therefore, the multi-core processor is required to maintain the consistency of the shared data.

In the prior art, a multi-core processor maintains the consistency of shared data using one of a directory protocol and a listening protocol. Since the directory protocol needs to store the directory entries in the sparse directory, the directory entry records the kernel of each shared data, thereby performing consistency processing on the shared data stored in the kernel according to the directory entries in the sparse directory, thereby causing the use of the directory protocol. Multi-core processors have high storage overhead and are less efficient to process consistently; in addition, although the listening protocol does not have to store directories in a sparse directory Item, but because the interception protocol needs to use the broadcast message to know the kernel that caches the shared data, so that the shared data is processed consistently, which causes the multi-core processor signaling overhead of the listening protocol to be large, which also causes Consistency processing is less efficient.

Summary of the invention

Embodiments of the present invention provide a consistency processing method and apparatus based on a multi-core processor for improving consistency processing efficiency.

The first aspect provides a multi-core processor-based consistency processing method, including: receiving a consistency request message sent by a first kernel in a multi-core processor; the consistency request message is used to indicate that a consistency process is to be performed. The target shared data; according to the number of the second kernel in the multi-core processor, selecting one of a directory protocol or a listening protocol to perform consistency processing on the target shared data; the second kernel is sharing The target shares the core of the data.

In a first possible implementation manner of the first aspect, the target shared data is data in a target data page of off-chip memory; the off-chip memory is used to provide the target sharing for the multi-core processor data.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the selecting, according to the number of the second cores in the multi-core processor, The consistency processing of the target shared data by one of the directory protocol or the interception protocol includes: determining whether the number of the second kernel is greater than a predetermined shared threshold; the shared threshold is greater than zero and less than An integer of the number of cores of the multi-core processor; if the number of the second core is not greater than the shared threshold, the target shared data is consistently processed by the interception protocol; If the number of kernels is greater than the shared threshold, the directory sharing protocol is used to perform consistency processing on the target shared data.

In conjunction with the second possible implementation of the first aspect, in a third possible implementation manner of the first aspect, the selecting, according to the number of the second cores in the multi-core processor, selecting a directory protocol or a metric After performing consistency processing on the target shared data, the method includes: a network collision rate according to the multi-core processor and the multi-core processor Sparse directory replacement rate, updating the shared threshold; the network collision rate indicating a degree of congestion of a network for transmitting messages between cores of the multi-core processor; the sparse directory replacement rate indicating The storage space occupancy of the sparse directory in the multi-core processor; if the data in the first data page of the off-chip memory is cached in the kernel of the multi-core processor, deleting the kernel cache of the multi-core processor The data in the first data page, so that the sparse directory in the multi-core processor deletes a directory entry corresponding to the first data page; the directory entry corresponding to the first data page is used to record a a kernel in which data in each data block of the first data page is cached; the first data page satisfies the number of cores that cache data in the first data page is greater than the updated shared threshold.

In conjunction with the third possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, the updating the shared threshold according to the network conflict rate and the sparse directory replacement rate, The method includes: if the network conflict rate is higher than the first threshold, and the sparse directory replacement rate is lower than the third threshold, determining that the updated shared threshold is twice the shared threshold; If the network conflict rate is lower than the second threshold, and the sparse directory replacement rate is higher than the fourth threshold, determining that the updated shared threshold is half of the shared threshold.

With reference to the third possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the network conflict rate is a difference between an actual transit time and a theoretical transit time, and the theoretical transit time Ratio between the two; the theoretical delivery time is a total time required for the at least one test message to be transmitted in the network when the state of the network is unblocked; the actual delivery time is a statistically obtained location The total time at which the at least one test message is actually delivered in the network.

In conjunction with the third possible implementation of the first aspect, in a sixth possible implementation manner of the first aspect, the sparse directory replacement rate is a number of times that the sparse directory performs a read operation at a specified time, The ratio between the number of times the free storage space of the sparse directory is zero in a specified time.

The second aspect provides a multi-core processor-based consistency processing apparatus, including: a receiving module, configured to receive a consistency request message sent by a first core in a multi-core processor; the consistency request message is used to Indicate the target shared data to be processed consistently; a processing module, configured to perform consistency processing on the target shared data by using one of a directory protocol or a listening protocol according to the number of the second kernels in the multi-core processor; the second kernel is shared The target shares the core of the data.

In a first possible implementation manner of the second aspect, the target shared data is data in a target data page of off-chip memory; the off-chip memory is used to provide the target sharing for the multi-core processor data.

With reference to the second aspect, or the first possible implementation manner of the second aspect, in the second possible implementation manner of the second aspect, the processing module includes:

a determining unit, configured to determine whether the number of the second core is greater than a predetermined shared threshold; the shared threshold is greater than zero and less than an integer of the number of cores of the multi-core processor;

a first processing unit, configured to: if the number of the second kernel is not greater than the shared threshold, use a listening protocol to perform consistency processing on the target shared data;

And a second processing unit, configured to perform consistency processing on the target shared data by using a directory protocol if the number of the second cores is greater than the shared threshold.

In conjunction with the second possible implementation of the second aspect, in a third possible implementation of the second aspect, the consistency processing device of the multi-core processor further includes:

And an update module, configured to update the shared threshold according to a network collision rate of the multi-core processor and a sparse directory replacement rate of the multi-core processor; the network conflict rate is indicated for being used in the multi-core a degree of congestion of a network that communicates messages between cores of the processor; the sparse directory replacement rate indicating a storage space occupancy of a sparse directory in the multi-core processor;

a deleting module, configured to: if the data in the first data page of the off-chip memory is cached in a kernel of the multi-core processor, deleting the first data page of the kernel cache of the multi-core processor Data, such that the sparse directory in the multi-core processor deletes a directory entry corresponding to the first data page; the directory entry corresponding to the first data page is used to record each data block of the first data page The core of the data is cached; the first data page satisfies the number of kernels that cache data in the first data page is greater than the updated shared threshold. With reference to the third possible implementation of the second aspect, in a fourth possible implementation manner of the second aspect, the updating module includes:

a first updating unit, configured to determine, if the network conflict rate is higher than a first threshold, and the sparse directory replacement rate is lower than a third threshold, determining that the updated sharing threshold is the shared threshold Doubled;

a second updating unit, configured to determine that the updated sharing threshold is the shared threshold if the network collision rate is lower than a second threshold, and the sparse directory replacement rate is higher than a fourth threshold Half of it.

With reference to the third possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the network conflict rate is a difference between an actual transit time and a theoretical transit time, and the theoretical transit time Ratio between the two; the theoretical delivery time is a total time required for the at least one test message to be transmitted in the network when the state of the network is unblocked; the actual delivery time is a statistically obtained location The total time at which the at least one test message is actually delivered in the network.

With reference to the third possible implementation of the second aspect, in a sixth possible implementation manner of the second aspect, the sparse directory replacement rate is a number of times that the sparse directory performs a read operation at a specified time, The ratio between the number of times the free storage space of the sparse directory is zero in a specified time.

The multi-core processor-based consistency processing method and apparatus provided by the embodiments of the present invention, according to the number of second cores sharing the target shared data in the multi-core processor, using the directory protocol or the interception protocol to share the data with the target Consistent processing is performed, so that the target shared data can be processed consistently by using a suitable protocol, and the shared data is partially shared by avoiding the same protocol for all shared data in the multi-core processor. Using the listening protocol, another part of the shared data uses the directory protocol, so that compared with the prior art, not only the directory items occupied by the shared data of the listening protocol in the sparse directory are saved, but also the directory protocol is saved. The shared data is generated by the broadcast message generated during the consistency processing, thereby improving the consistency processing efficiency. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings to be used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are Some embodiments of the present invention may also be used to obtain other drawings based on these drawings without departing from the prior art.

1 is a schematic flowchart of a multi-core processor-based consistency processing method according to an embodiment of the present invention;

2 is a schematic flowchart of a multi-core processor-based consistency processing method according to another embodiment of the present invention;

3 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to an embodiment of the present invention;

4 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to another embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to still another embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is a partial embodiment of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative work are within the scope of the present invention.

FIG. 1 is a schematic flowchart of a multi-core processor-based consistency processing method according to an embodiment of the present invention. As shown in FIG. 1, the embodiment may include the following steps:

101. Receive a consistency request message sent by a first core in the multi-core processor.

The consistency request message is used to indicate target shared data to be processed consistently. 102. According to the number of the second kernel in the multi-core processor, select one of a directory protocol or a listening protocol to perform consistency processing on the target shared data.

The second core is a kernel that shares the target shared data, and specifically may be a kernel that operates on the target shared data, and the operations include a read operation and a write operation.

Optionally, determining whether the number of the second kernel is greater than a predetermined shared threshold, and if the number of the second kernel is not greater than the shared threshold, using the interception protocol to perform consistency on the target shared data. Processing, if the number of the second kernel is greater than the shared threshold, the directory protocol is used to perform consistency processing on the target shared data. Where the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor. The shared threshold is determined according to a network collision rate of the multi-core processor and a sparse directory replacement rate of the multi-core processor. The network collision rate indicating a degree of congestion of a network for transmitting a message between cores of the multi-core processor; the sparse directory replacement rate indicating storage space occupation of a sparse directory in the multi-core processor degree.

In this embodiment, according to the number of second cores shared by the target shared data in the multi-core processor, the target shared data is consistently processed by using a directory protocol or a listening protocol, and the target shared data can be used appropriately. The protocol is processed consistently, and since all the shared data in the multi-core processor is avoided, the same protocol is used for consistency processing, the shared data is used for the listening protocol, and the other part is shared with the directory protocol. Therefore, compared with the prior art, not only the directory items occupied by the shared data of the listening protocol in the sparse directory are saved, but also the broadcast message generated when the shared data of the directory protocol is used for consistency processing is saved, thereby improving Consistency processing efficiency.

2 is a schematic flowchart of a multi-core processor-based consistency processing method according to another embodiment of the present invention. The target shared data in this embodiment is data in a target data page of off-chip memory, as shown in FIG. 2 . This embodiment may include the following steps:

201. Receive a consistency request message sent by a first core in the multi-core processor.

The consistency request message is used to indicate the target shared data to be processed consistently.

Before the first kernel needs to read or write the target shared data, if the first If the kernel does not cache the target shared data, a consistency request message is sent to obtain the target shared data and the kernel that knows that the target shared data is cached. If the first kernel caches the target shared data or the first kernel acquires the target shared data, the first kernel sends a consistency request message to learn the kernel that caches the target shared data, so that the first kernel shares the target. After the data is written, the target shared data in the kernel with the target shared data cached is deleted, and the consistency processing is completed.

202. Query the shared list stored in the TLB of the first kernel, and obtain the number of the second kernel in the multi-core processor.

The shared list is used to record the identity of the kernel that shares data in each data page of the off-chip memory. The second kernel is a kernel that shares the target shared data.

Optionally, the kernel that performs the read or write operation on the target shared data in the multi-core processor is used as the second kernel that shares the target shared data, and the query is based on the storage address of the target shared data in the off-chip memory. The shared list stored in the TLB of the first kernel acquires the kernel identifier corresponding to the storage address, and thereby acquires the number of second cores sharing the target shared data in the multi-core processor. The shared list can be obtained by adding a page share list in the page table entry in the TLB. The shared list includes: a virtual address of the data page, a valid bit of the data page, a physical address of the data page, and a page share list of the data page, and the page share The list is used to record the kernel ID that operates on the data in the data page.

203. Determine whether the number of the second kernel is greater than a predetermined shared threshold. If the execution is 205, execute 204.

Wherein, the shared threshold is an integer that is greater than zero and less than the number of cores of the multi-core processor. It can be determined that the initial sharing threshold is 1, that is, only when the state of the target data page is exclusive, that is, when the number of the second kernel is 1, the listening protocol is used, otherwise the directory protocol is used.

204. If the number of the second kernel is not greater than the shared threshold, the target shared data is consistently processed by using a listening protocol.

Optionally, if the number of the second core is not greater than the shared threshold, the multicast message is multicast to each of the second cores, so that the second core of the second core that caches the target shared data is sent to the first core. Cache the target shared data, and the target shared data is not cached The second core sends a response message to the first kernel indicating that the target shared data is not cached, so that the first kernel acquires the target shared data. If the operation performed by the first kernel on the acquired target shared data is a write operation, after the first kernel operates the acquired target shared data, the target shared data cached in the second kernel of the cached target shared data is deleted, and is sparse The second kernel of the cache target shared data recorded in the directory is updated to complete the consistency processing. Because the listening protocol is used to consistently process the target shared data, the storage capacity of the target shared data occupying the sparse directory is avoided.

205. If the number of the second kernel is greater than the shared threshold, use the directory protocol to perform consistency processing on the target shared data.

Optionally, if the number of the second kernel is greater than the shared threshold, determining, according to the sparse directory, the second kernel of the cache target shared data, where the sparse directory is used to record the cache target when the number of the second kernel is greater than the shared threshold The second kernel that shares data. A data request message is sent to the second core of the cache target shared data, so that the second core of the cache target shared data sends the cached target shared data to the first core, thereby acquiring the target shared data. If the operation performed by the first kernel on the acquired target shared data is a write operation, after the first kernel operates the acquired target shared data, the target shared data cached in the second kernel of the cached target shared data is deleted, and is sparse The second kernel of the cache target shared data recorded in the directory is updated to complete the consistency processing.

206. Calculate the network collision rate of the multi-core processor and the sparse directory replacement rate of the multi-core processor.

Among them, the network collision rate indicates the degree of congestion of the network used to transfer messages between the cores of the multi-core processor. A sparse directory replacement rate indicating the amount of storage space occupied by sparse directories in the multi-core processor.

Optionally, after performing 204 or 205, the network conflict rate is a ratio between the actual transit time and the theoretical transit time, and the theoretical transfer time. The theoretical delivery time is a total time required for the at least one test message to be delivered in the network when the state of the network is unblocked; the actual delivery time is the statistically obtained at least one test message. The total time actually used for delivery in the network. Sparse directory replacement rate The ratio of the number of times the read operation is performed to the sparse directory at a specified time, and the number of times the free storage space of the sparse directory is zero within a specified time.

207. Update the shared threshold according to the network conflict rate of the multi-core processor and the sparse directory replacement rate of the multi-core processor.

Optionally, after the target shared data is consistently processed by using a directory protocol or a listening protocol, if the network conflict rate is higher than the first threshold, for example: 80%, and the sparse directory replacement rate is lower than the third width The value, for example: 1%, determines that the updated sharing threshold is twice the shared threshold, if the network collision rate is lower than the second threshold, for example: 2%, and the sparse directory replacement rate is higher than The fourth threshold, for example: 15%, determines that the updated shared threshold is half of the shared threshold, otherwise, no update is performed. The multi-core processor in this embodiment determines the sharing threshold according to the degree of network congestion and the spatial occupancy of the sparse directory, and dynamically adjusts the proportion of the directory protocol and the listening protocol to achieve an optimal balance point, thereby making the network Congestion levels and sparse directory space occupancy levels are dynamically balanced, improving consistency efficiency and improving multi-core processor performance.

It should be noted that the shared threshold update can also be performed after the clock cycle of the specified multi-core processor.

208. Delete data in the first data page cached in a kernel of the multi-core processor.

The first data page satisfies the number of cores that cache data in the first data page is greater than the updated shared threshold.

Optionally, if the data in the first data page of the off-chip memory is cached in the kernel of the multi-core processor, the data in the first data page stored in the kernel of the multi-core processor is deleted, so that the multi-core is The sparse directory in the processor correspondingly deletes the directory entry corresponding to the first data page, wherein the directory entry corresponding to the first data page is used to record a kernel that caches data in each data block of the first data page.

In this embodiment, according to the number of second cores shared by the target shared data in the multi-core processor, the target shared data is consistently processed by using a directory protocol or a listening protocol, and the target shared data can be used appropriately. Protocol for consistency processing, and because It avoids the consistency processing of all shared data in the multi-core processor, the same protocol for the shared data, and the shared data using the directory protocol, so that it saves compared with the prior art. The use of the shared data of the listening protocol in the directory directory occupied by the sparse directory, and the broadcast message generated when the shared data of the directory protocol is used for consistency processing is saved, thereby improving the consistency processing efficiency.

FIG. 3 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to an embodiment of the present invention. As shown in FIG. 3, the method includes: a receiving module 31 and a processing module 32.

The receiving module 31 is configured to receive a consistency request message sent by the first core in the multi-core processor.

The processing module 32 is connected to the receiving module 31, and is configured to perform consistency processing on the target shared data by using one of a directory protocol or a listening protocol according to the number of the second cores in the multi-core processor.

The second kernel is a kernel that shares the target shared data.

Optionally, determining whether the number of the second kernel is greater than a predetermined shared threshold, and if the number of the second kernel is not greater than the shared threshold, using the interception protocol to perform the target shared data. Consistency processing, if the number of the second kernel is greater than the shared threshold, the directory protocol is used to perform consistency processing on the target shared data. Wherein, the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor.

The functional modules of the multi-core processor-based coherency processing device provided in this embodiment may be used to execute the process of the multi-core processor-based coherent processing device method shown in FIG. 1 , and the specific working principle is not described again. See the description of the method embodiment.

FIG. 4 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to another embodiment of the present invention. As shown in FIG. 4, on the basis of the previous embodiment, the processing module 32 in this embodiment includes : a judging unit 321, a first processing unit 322, and a second processing unit 323.

The determining unit 321 is configured to determine whether the number of the second kernel is greater than a predetermined shared threshold; the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor;

The first processing unit 322 is connected to the determining unit 321 , configured to: if the number of the second core is not greater than the shared threshold, use the interception protocol to perform consistent processing on the target shared data;

The second processing unit 323 is connected to the determining unit 321 for performing consistency processing on the target shared data by using a directory protocol if the number of the second cores is greater than the shared threshold.

Further, the target shared data is data in a target data page of off-chip memory.

The off-chip memory is connected to the multi-core processor and is used to store the target shared data. Based on this, the multi-core processor-based coherency processing device further includes: an update module 33 and a delete module 34.

The update module 33 is coupled to the processing module 32 for updating the shared threshold according to the network collision rate of the multi-core processor and the sparse directory replacement rate of the multi-core processor.

The network collision rate indicates a degree of congestion of a network for transmitting messages between cores of the multi-core processor; a sparse directory replacement rate indicating a storage space occupancy of a sparse directory in the multi-core processor.

The deleting module 34 is connected to the update module 33, and configured to delete the kernel cache of the multi-core processor if the data in the first data page of the off-chip memory is cached in the kernel of the multi-core processor Decoding the data in the first data page to enable the multi-core processor The sparse directory deletes the directory entry corresponding to the first data page.

The directory entry corresponding to the first data page is configured to record a kernel that caches data in each data block of the first data page; the first data page is configured to cache data in the first data page. The number of cores is greater than the updated shared threshold.

Further, the update module 33 includes a first update unit 331 and a second update unit 332. The first update unit 331 is configured to determine that the updated sharing threshold is twice the sharing threshold if the network collision rate is higher than a first threshold, and the sparse directory replacement rate is lower than a third threshold. .

Wherein, the network collision rate is the ratio between the actual delivery time and the theoretical delivery time, and the ratio of the theoretical delivery time. The theoretical delivery time is calculated by the total time required for at least one test message to be delivered in the network when the state of the network is unblocked; the actual delivery time is the statistically obtained at least one test message in the The total time actually used for delivery in the network. The sparse directory replacement rate is the ratio of the number of times the sparse directory performs a read operation at a specified time to the number of times the free storage space size of the sparse directory is zero within a specified time.

a second updating unit 332, configured to determine, if the network conflict rate is lower than a second threshold, and the sparse directory replacement rate is higher than a fourth threshold, determining that the updated sharing threshold is the shared width Half of the value.

The functional modules of the multi-core processor-based coherency processing device provided in this embodiment may be used to execute the process of the multi-core processor-based coherent processing device method shown in FIG. 2, and the specific working principle is not described again. See the description of the method embodiment.

In this embodiment, according to the number of second cores shared by the target shared data in the multi-core processor, the target shared data is consistently processed by using a directory protocol or a listening protocol, and the target shared data can be used appropriately. The protocol is processed consistently, and since all the shared data in the multi-core processor is avoided, the same protocol is used for consistency processing, the shared data is used for the listening protocol, and the other part is shared with the directory protocol. Therefore, compared with the prior art, not only the directory items occupied by the shared data of the listening protocol in the sparse directory are saved, but also the shared data of the directory protocol is saved for consistency. The broadcast message generated during processing increases the efficiency of the consistency processing.

FIG. 5 is a schematic structural diagram of a multi-core processor-based consistency processing apparatus according to another embodiment of the present invention. As shown in FIG. 5, the method includes: a communication interface 51, a processor 52, and a memory 53.

The communication interface 51 is configured to receive a consistency request message sent by the first core in the multi-core processor.

The memory 53 is used to store the program. In particular, the program can include program code, the program code including computer operating instructions. Memory 53 may contain high speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

The processor 52 is configured to execute a program stored in the memory 53, configured to: select, according to the number of second cores in the multi-core processor, use one of a directory protocol or a listening protocol to share data with the target Perform consistency processing.

The second kernel is a kernel that shares the target shared data.

Optionally, determining whether the number of the second kernel is greater than a predetermined shared threshold, and if the number of the second kernel is not greater than the shared threshold, using the interception protocol to perform consistency on the target shared data. Processing; if the number of the second kernel is greater than the shared threshold, the directory protocol is used to perform consistency processing on the target shared data. Where the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor.

Based on this, the processor 52 is further configured to: update a sharing threshold according to a network collision rate of the multi-core processor and a sparse directory replacement rate of the multi-core processor; if the multi-core processor has a cache in the kernel Data in the first data page of the off-chip memory, deleting data in the first data page of the kernel cache of the multi-core processor, to delete the sparse directory in the multi-core processor The directory entry corresponding to the first data page.

The directory entry corresponding to the first data page is used to record each of the first data pages. The kernel in the data block is cached; the first data page satisfies the number of kernels that cache data in the first data page is greater than the updated shared threshold. The network conflict rate is the ratio between the actual transit time and the theoretical transit time, and the theoretical transfer time; the theoretical transit time is calculated and obtained when the state of the network is unblocked, at least one test message is in the The total time required for delivery in the network; the actual delivery time is the total time actually used by the statistically obtained delivery of the at least one test message in the network. The sparse directory replacement rate is a ratio between the number of times the sparse directory performs a read operation at a specified time and the number of times the free storage space size of the sparse directory is zero within the specified time.

It will be understood by those skilled in the art that all or part of the steps of implementing the above method embodiments may be performed by hardware related to the program instructions. The aforementioned program can be stored in a computer readable storage medium. When the program is executed, the steps including the foregoing method embodiments are performed; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk. The invention is not limited thereto; although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions described in the foregoing embodiments may be modified, or some or all of them may be modified. Technical features for equivalent replacement; and this The modifications and substitutions do not depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

Claim

A consistency processing method based on a multi-core processor, comprising: receiving a consistency request message sent by a first kernel in a multi-core processor; the consistency request message is used to indicate consistency to be performed The target of the processing shares data;

Selecting, according to the number of the second kernels in the multi-core processor, selecting one of a directory protocol or a listening protocol to perform consistency processing on the target shared data; and the second kernel is sharing the target shared data. Kernel.

2. The multi-core processor-based consistency processing method according to claim 1, wherein the target shared data is data in a target data page of off-chip memory; and the off-chip memory is used for The multi-core processor provides the target shared data.

The multi-core processor-based consistency processing method according to claim 1 or 2, wherein the selecting a directory protocol or listening according to the number of second cores in the multi-core processor One of the protocols performs consistency processing on the target shared data, including:

Determining whether the number of the second kernel is greater than a predetermined shared threshold; the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor;

If the number of the second kernel is not greater than the shared threshold, the target shared data is consistently processed by using a listening protocol;

If the number of the second kernel is greater than the shared threshold, the directory sharing protocol is used to perform consistency processing on the target shared data.

The multi-core processor-based consistency processing method according to claim 3, wherein the selecting the directory protocol or the listening protocol according to the number of the second kernels in the multi-core processor After performing consistency processing on the target shared data, the method includes:

Updating the shared threshold according to a network collision rate of the multi-core processor and a sparse directory replacement rate of the multi-core processor; the network collision rate is indicated for a kernel in the multi-core processor The degree of congestion of the packet, the network, the sparse directory replacement rate, indicating the storage space occupancy of the sparse directory in the multi-core processor; if the kernel of the multi-core processor is cached The first data page of off-chip memory Data, deleting data in the first data page of the kernel cache of the multi-core processor, such that a sparse directory in the multi-core processor deletes a directory entry corresponding to the first data page; a directory entry corresponding to the first data page is used to record a kernel that caches data in each data block of the first data page; the first data page satisfies a number of cores that cache data in the first data page Greater than the updated shared threshold.

The multi-core processor-based consistency processing method according to claim 4, wherein the updating the shared threshold according to the network conflict rate and the sparse directory replacement rate comprises:

If the network conflict rate is higher than the first threshold, and the sparse directory replacement rate is lower than the third threshold, determining that the updated sharing threshold is twice the sharing threshold;

And if the network conflict rate is lower than the second threshold, and the sparse directory replacement rate is higher than the fourth threshold, determining that the updated shared threshold is half of the shared threshold.

The multi-core processor-based consistency processing method according to claim 4, wherein the network collision rate is a ratio between an actual delivery time and a theoretical delivery time, and a ratio between the theoretical transmission time and the theoretical transmission time. The theoretical delivery time is a calculated total time required for at least one test message to be delivered in the network when the state of the network is unblocked; the actual delivery time is the at least one obtained by statistics The total time that the test message was actually used for delivery in the network.

The multi-core processor-based consistency processing method according to claim 4, wherein the sparse directory replacement rate is the number of times the sparse directory performs a read operation at a specified time, and the specified time The ratio between the number of times the free storage space of the sparse directory is zero.

A consistency processing device based on a multi-core processor, comprising: a receiving module, configured to receive a consistency request message sent by a first kernel in a multi-core processor; the consistency request message is used a target shared data indicating consistency processing; a processing module, configured to select one of a target directory protocol or a listening protocol to perform the target shared data according to the number of second cores in the multi-core processor Consistency processing; the second kernel is a kernel that shares the target shared data.

9. The multi-core processor-based consistency processing apparatus according to claim 8, The feature is that the target shared data is data in a target data page of off-chip memory; the off-chip memory is used to provide the target shared data for the multi-core processor.

The multi-core processor-based consistency processing device according to claim 8 or 9, wherein the processing module comprises: a determining unit, configured to determine whether the number of the second kernel is greater than a predetermined a shared threshold; the shared threshold is an integer greater than zero and less than the number of cores of the multi-core processor;

The multi-core processor-based coherency processing device according to claim 10, wherein the multi-core processor-based coherency processing device further comprises: an update module, configured to: according to the multi-core Updating a shared threshold of a network collision rate of the processor and a sparse directory replacement rate of the multi-core processor; the network collision rate indicating a network for transmitting messages between cores of the multi-core processor The degree of congestion; the sparse directory replacement rate indicating the storage space occupancy of the sparse directory in the multi-core processor;

a deleting module, configured to: if the data in the first data page of the off-chip memory is cached in a kernel of the multi-core processor, deleting the first data page of the kernel cache of the multi-core processor Data, such that the sparse directory in the multi-core processor deletes a directory entry corresponding to the first data page; the directory entry corresponding to the first data page is used to record each data block of the first data page The core of the data is cached; the first data page satisfies the number of kernels that cache data in the first data page is greater than the updated shared threshold.

The multi-core processor-based consistency processing device according to claim 11, wherein the updating module comprises: a first updating unit, configured to: if the network conflict rate is higher than a first threshold And determining, by the sparse directory replacement rate, that the updated sharing threshold is twice the shared threshold; a second updating unit, configured to determine that the updated sharing threshold is the shared threshold if the network collision rate is lower than a second threshold, and the sparse directory replacement rate is higher than a fourth threshold Half of it.

13. The multi-core processor-based consistency processing apparatus according to claim 11, wherein the network collision rate is a ratio between an actual delivery time and a theoretical delivery time, and a ratio between the theoretical delivery time and the theoretical delivery time. The theoretical delivery time is a calculated total time required for at least one test message to be delivered in the network when the state of the network is unblocked; the actual delivery time is the at least one obtained by statistics The total time that the test message was actually used for delivery in the network.

14. The multi-core processor-based consistency processing apparatus according to claim 11, wherein the sparse directory replacement rate is a number of times the sparse directory performs a read operation at a specified time, and the specified time The ratio between the number of times the free storage space of the sparse directory is zero.