WO2018082695A1

WO2018082695A1 - Cache replacement method and device

Info

Publication number: WO2018082695A1
Application number: PCT/CN2017/109553
Authority: WO
Inventors: 陈明宇; 潘海洋; 刘宇航; 阮元; 陈少杰
Original assignee: 华为技术有限公司
Priority date: 2016-11-07
Filing date: 2017-11-06
Publication date: 2018-05-11
Also published as: CN108073527A; CN108073527B

Abstract

A cache replacement method and a device, for application in a computer system; the computer system comprises a memory controller, a first tier storage and second tier storage, the method comprising: the memory controller receiving a first access request, wherein a first target address is carried in the first access request, and the first target address is an address of to-be-accessed first data of the first access request, which is in the second tier storage (S101); when determining, according to the first target address, that the first access request does not hit a first region and a second region in the first tier storage, the memory controller acquiring first data from the second tier storage according to the first target address, wherein the first tier storage comprises a first region, a second region and a third region, the first region being for use in caching hot data, the second region being for use in caching cold data, and the third region being for use in caching an address, which is in the second tier storage, of data which is from the second region and which is replaced (S102); when determining, according to the first target address, that the first access request does not hit the third region, the memory controller determining, in the second region, a first cache block to be replaced (S103); and the memory controller replacing data from the first cache block with the first data (S104).

Description

Method and device for cache replacement

Technical field

The present invention relates to the field of data processing technologies, and in particular, to a method and device for cache replacement.

Background technique

The computer system may include a memory controller, a dynamic random access memory (DRAM), and a non-volatile memory (NVM). Wherein, the DRAM includes one or more cache blocks for storing data. After the memory controller receives the access request, if the access request misses the DRAM and the DRAM is full, the data to be accessed is obtained from the NVM, and a cache block in the DRAM is randomly used as the cache block to be replaced, and will be The data in the replacement cache block is replaced with the data to be accessed.

In the cache replacement method provided above, the memory controller randomly uses one cache block in the DRAM as the cache block to be replaced, so that it is possible to replace the data with high access frequency, which reduces the cache hit ratio.

Summary of the invention

Embodiments of the present invention provide a method and apparatus for cache replacement to improve cache hit ratio.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In one aspect, a method of cache replacement is provided for use in a computer system including a memory controller and hybrid memory. The hybrid memory includes a first level memory and a second level memory. The first level of memory is used to cache data in the second level of memory, the first level of memory supports cache access, and the second level of memory is NVM. The method may include: the memory controller receiving the first access request carrying the first target address, wherein the first target address is an address of the first data to be accessed by the first access request in the second level memory; The memory controller determines, according to the first target address, that the first access request misses the first area and the second area in the first level memory, and acquires the first data from the second level memory according to the first target address, where the first The level memory includes a first area for buffering hot data, a second area for buffering cold data, and a third area for buffering data that is replaced from the second area. An address in the second level memory; subsequently, when the memory controller determines that the first access request misses the third area according to the first target address, determining the first cache block to be replaced in the second area; and finally, the memory controller The data in the first cache block is replaced with the first data.

In the technical solution, when the access request misses the first level memory, the memory controller acquires the first data requested by the access request from the second level memory, and then, the memory controller according to the first carried in the access request When the target address determines that the first access request misses the third zone, the first cache block to be replaced is determined in the second zone. The first area is for buffering hot data, the second area is for buffering cold data, and the third area is for recording an address in the second level memory of data that is replaced from the second area. That is to say, in the technical solution provided by the embodiment of the present invention, if the probability of the third zone miss is high, the probability that the cached cold data in the first zone is replaced is increased, so that the first level cache is More cached hot data. Therefore, the cache hit ratio can be improved as compared with the cache block to be replaced that is randomly determined in the first level buffer provided in the prior art.

In one possible design, the second level of memory is a non-volatile memory NVM.

In a possible design, after the memory controller replaces the data in the first cache block with the first data, the method may further include: the memory controller storing the address of the data in the first cache block in the third In the district. The possible design is used to determine whether to determine the cache block to be replaced from the first zone during the subsequent cache replacement process. The cache block to be replaced is determined from the second zone. Specifically, if the memory controller determines that the first target address is stored in the third area, the first data is considered to be hot data, and the cache block to be replaced is determined in the first area; if it is determined that the first area is not stored in the third area The target address is considered to be cold data, and the cache block to be replaced is determined in the second area.

In a possible design, the method may further include: the memory controller receiving the second access request carrying the second target address, and the second target address being the second access request to access the second data in the second level memory Address; then, when determining that the second access request misses the first region and the second region in the first level memory according to the second target address, the memory controller is from the second level memory according to the second target address Obtaining the second data; subsequently, when determining that the second access request hits the third region according to the second target address, the memory controller determines the second cache block to be replaced in the first region; finally, the memory controller will use the second cache The data in the block is replaced with the second data.

In one possible design, the first zone is larger than the second zone. The number of cache blocks included in the first zone may be greater than the number of cache blocks included in the second zone, that is, the area in which the hot data is stored may be larger than the area in which the cold data is stored. Since the hit rate of hot data access is higher than the hit rate of cold data access, expanding the area of hot data can increase the cache hit rate.

In a possible design, the memory controller determines the first cache block to be replaced in the second area, and may include: the memory controller writes any data in the second area or is first written into the first level memory The cache block in which the data is located is determined as the first cache block to be replaced.

In one possible design, the third zone is less than or equal to a predetermined threshold. In the embodiment of the present invention, the value of the preset threshold is not limited. Generally, the preset threshold is small, that is, the storage space of the third area is small, so that as much cold data as possible stored in the second area is replaced. The hot data stored in the first area is replaced as little as possible, thereby improving the cache hit rate. The specific analysis process can be referred to below.

In another aspect, a computing device is provided, the computing device can include a memory controller and a hybrid memory, the mixed memory including a first level memory and a second level memory, wherein the first level memory is used to cache data in the second level memory, The first level of memory supports the cache access, and the memory controller is configured to: receive the first access request, where the first access request carries the first target address, and the first target address is the first data to be accessed by the first access request. An address in the second level memory; when determining that the first access request misses the first area and the second area in the first level memory according to the first target address, acquiring the first from the second level memory according to the first target address Data, wherein the first level memory comprises a first area for buffering hot data, a second area for buffering cold data, and a third area for buffering from the second area An address of the replaced data in the second level memory; when it is determined that the first access request misses the third area according to the first target address, determining the to-be-replaced in the second area A cache block; replaces data in the first cache block is a first data.

In a possible design, the memory controller is further configured to: store the address of the data in the first cache block in the third zone.

In a possible design, the memory controller is further configured to: receive a second access request, where the second access request carries a second target address, and the second target address is a second access request to be accessed by the second data. An address in the secondary storage device; when determining that the second access request misses the first region and the second region in the first level memory according to the second target address, acquiring the second data from the memory according to the second target address; When the second target address determines that the second access request hits the third area, the second cache block to be replaced is determined in the first area; the data in the second cache block is replaced with the second data.

In one possible design, the first zone is larger than the second zone.

In a possible design, the memory controller is specifically configured to: determine, as the first cache block to be replaced, the cache block in which any data in the second area or the data that is first written into the first level memory is located.

In one possible design, the third zone is less than or equal to a predetermined threshold.

In another aspect, an embodiment of the present invention provides a memory controller, where the memory controller includes modules for performing the foregoing first aspect and the method shown in each possible implementation manner of the first aspect.

In still another aspect, a computer readable storage medium is provided, wherein computer executable instructions are stored, wherein when the at least one processor of the computing device executes the computer to execute the instructions, the computing device performs the above aspects or any of the above aspects A possible implementation of the cache replacement method provided.

In another aspect, a computer program product is provided, the computer program product comprising computer executable instructions stored in a computer readable storage medium; at least one processor of the computing device can read the computer readable storage medium The computer executes the instructions, and the at least one processor executes the computer to execute the instructions such that the computing device implements the cache replacement method provided by the above aspects or any of the possible implementations of the above aspects.

It can be understood that any of the computing devices or computer storage media provided above are used to perform the cache replacement method provided above, and therefore, the beneficial effects that can be achieved can be referred to the corresponding cache replacement provided above. The beneficial effects of the method are not repeated here.

DRAWINGS

1 is a structural diagram of a computer system to which an embodiment of the present invention is applied;

2 is a schematic structural diagram of a cache system according to an embodiment of the present invention;

FIG. 3 is a flowchart of a method for cache replacement according to an embodiment of the present invention;

4 is a structural diagram of a first level memory according to an embodiment of the present invention;

FIG. 5 is a structural diagram of another first level memory according to an embodiment of the present disclosure;

FIG. 6 is an interaction diagram of a method for cache replacement according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a memory controller according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of another memory controller according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a computing device according to an embodiment of the present invention.

detailed description

The technical solution provided by the embodiment of the present invention can be applied to the computer system architecture shown in FIG. 1. The computer system shown in FIG. 1 can include a processor, a memory controller, and a hybrid memory. Among them, the processor is the control center of the computer system. The hybrid memory includes a first level memory and a second level memory. The first level of memory is used to cache data in the second level of memory and is also used to support cache access. In a DRAM-NVM memory system, DRAM can be used as the first level of memory in the computer system provided in FIG. 1, and NVM can be used as the second level of memory in the computer system provided in FIG.

The technical solution provided by the embodiment of the present invention can also be applied to the cache system architecture shown in FIG. 2. The cache system shown in FIG. 2 can include a processor, a cache, a cache controller, a memory controller, and a memory. Among them, the processor is the control center of the cache system. Cache is a high-speed memory between the processor and memory, mainly used for Improve the read and write performance of the system. The cache controller is used to manage the data in the cache. The data in the cache can be part of the data in memory. Further, if the cache contains data to be accessed, the processor can obtain the data to be accessed from the cache without acquiring the data to be accessed from the memory, thereby speeding up the reading speed.

It should be noted that the functions performed by the memory controller in FIG. 1 can be analogized to the functions performed by the cache controller in FIG. 2. The first level of memory in Figure 1 can be analogized to the cache in Figure 2. The second level of memory in Figure 1 can be analogized to the memory in Figure 2.

The terms "first" and "second" and the like are used herein to distinguish different objects, rather than to describe a particular order of the objects. The term "plurality" as used herein refers to two or more. The character "/" in this article indicates that the contextual object is an "or" relationship.

As shown in FIG. 3, a flowchart of a cache replacement method according to an embodiment of the present invention may be applied to a computer system architecture as shown in FIG. 1. The computer system may include a processor, a memory controller, and a first Level memory and second level memory. The first level of memory includes a first zone, a second zone, and a third zone. The first area is for buffering hot data, the second area is for buffering cold data, and the third area is for buffering addresses in the second level memory of data that is replaced from the second area. In the embodiment of the present invention, the data stored in the first area is considered to be hot data, and the data stored in the second area is cold data. The locations of the cache blocks included in the first zone, the second zone, and the third zone may be continuous or discontinuous.

Based on this, the method may include the following steps S101-S104:

S101: The memory controller receives the first access request. The first access request carries a first target address, where the first target address is an address of the first data to be accessed by the first access request in the second level memory.

Specifically, S101 may include: the memory controller receiving the first access request sent by the processor. The first access request may be any one of the access requests sent by the processor.

Before S101, the method may further include: determining, by the memory controller, whether the first access request hits any one of the first zone and the second zone in the first level memory according to the first target address.

S102: When determining that the first access request misses the first area and the second area in the first level memory according to the first target address, the memory controller acquires the first data from the second level memory according to the first target address.

The first data may be any data stored in the hybrid memory; and the first data may be data stored in the first level memory or may not be data stored in the first level memory.

Optionally, after the memory controller partitions the first level memory, the first area may include one or more cache blocks, the second area may include one or more cache blocks, and the third area may include one or more cache blocks. . The number of cache blocks included in the first area may be greater than the number of cache blocks included in the second area, that is, the area where the hot data is stored may be larger than the area where the cold data is stored. Since the hit rate of hot data access is higher than the hit rate of cold data access, expanding the area of hot data can increase the cache hit rate.

The obtaining the first data from the second level memory in S102 may include: the memory controller transmitting the first access request to the second level memory; the second level memory receiving the first access request, and sending the access to the memory controller And a response message, wherein the access response message carries the first data; the memory controller receives the access response message.

S103: When determining that the first access request misses the third area according to the first target address, the memory controller determines the first cache block to be replaced in the second area.

If the memory controller determines that the first access request misses the third area according to the first target address, the first data is considered to be cold data, and the first data is to be placed in the second area, that is, determined in the second area. The first cache block that is replaced.

In S103, the determining, by the memory controller, the first cache block to be replaced in the second area may include: the memory controller randomly determining, in the second area, the cache block where the data in the second level memory is located according to a random algorithm. The first cache block to be replaced; or, according to the first-in first-out algorithm, the first cache block to be replaced is determined by the cache block in which the data originally written in the first-level memory is located. The specific content of the random algorithm and the first-in first-out algorithm can refer to the prior art.

S104: The memory controller replaces the data in the first cache block with the first data.

The memory controller obtains the first data from the second level memory according to the first target address if it is determined that the first access request misses the first area and the second area in the first level memory. If the first level memory is full and the third area does not store the first target address, then in this case, the memory controller preferentially determines the first cache block to be replaced in the second area, and the first cache block The data is replaced with the first data. Since the second area stores cold data, the embodiment of the present invention ensures that the cold data is preferentially replaced, thereby improving the cache hit ratio.

By way of example, assume that the first level of memory includes six cache blocks, each of which stores data and an address of the data. The first level of memory includes a first zone, a second zone, and a third zone. The data block 3 and the address 3 are stored in the cache block 1 of the first area, the data 4 and the address 4 are stored in the cache block 2, the data 5 and the address 5 are stored in the cache block 3, and the data 1 and the address are stored in the cache block 4 of the second area. 1. Cache block 5 stores data 2 and address 2, and the cache block 6 of the third area does not store an address, as shown in FIG. If the first access request received by the memory controller at the first time includes the address 6, after the cache is replaced, the information stored in the cache block 4 of the second area may be data 6 and address 6, and the cache block 6 of the third area may be Store address 1, as shown in Figure 5.

In a specific implementation, if the first level memory is not full, the memory controller may write the first data into any of the free cache blocks.

In the technical solution provided by the embodiment of the present invention, when the access request misses the first level memory, the memory controller acquires the first data requested by the access request from the second level memory, and then, the memory controller according to the access request When the carried first target address determines that the first access request misses the third area, the first cache block to be replaced is determined in the second area. The first area is for buffering hot data, the second area is for buffering cold data, and the third area is for recording an address in the second level memory of data that is replaced from the second area. That is to say, in the technical solution provided by the embodiment of the present invention, if the probability of the third zone miss is high, the probability that the cached cold data in the first zone is replaced is increased, so that the first level cache is More cached hot data. Therefore, the cache hit ratio can be improved as compared with the cache block to be replaced that is randomly determined in the first level buffer provided in the prior art.

In the prior art, the memory controller can add a flag bit to each cache block included in the DRAM and set an initial value of each cache block. If the DRAM controller determines that the data to be accessed is stored in the DRAM, that is, the hit, the DRAM controller sends an access response message including the data to be accessed to the processor, and updates the to-be-accessed data information. Updating the data information to be accessed may include, but is not limited to, zeroing the value of the flag bit of the cache block in which the data to be accessed is located, and increasing the value of the flag bit of all cache blocks in the DRAM from which the cache block is removed. In specific implementation, the initial value of the set cache block and the magnitude of the value of the added flag bit are not limited. For example, suppose the memory controller sets the initial value of each cache block to 1. If the cache hits, the value of the flag bit of the cache block where the data to be accessed is located may be updated from "1" to "0", and The initial value of the flag bit of all cache blocks in the DRAM except the cache block is updated from "1" to "2".

Based on this, in the technical solution provided in the embodiment of the present invention, if the cache hits, the memory controller processes the The device sends an access response message including the data to be accessed, and does not need to update the data information to be accessed, so that the overhead of updating the data information to be accessed when hitting can be eliminated as compared with the prior art.

Optionally, the method may further include: the memory controller receives the second access request, where the second access request carries the second target address, and the second target address is the second access request to be accessed. The address in the secondary storage. When determining that the second access request misses the first area and the second area in the first level memory according to the second target address, the memory controller acquires the second data from the memory according to the second target address. When it is determined that the second access request hits the third region according to the second target address, the memory controller determines the second cache block to be replaced in the first region. The memory controller replaces the data in the second cache block with the second data. It should be noted that the second access request may be any access request sent by the processor. The first access request and the second access request may be the same and may be different. The first cache block to be replaced and the second cache block to be replaced may be the same and may be different. The embodiment of the present invention is described as an example in which the first access request and the second access request are the same, and the first cache block and the second cache block are the same.

Optionally, after S104, the method may further include: the memory controller storing the address of the data in the first cache block in the third area. The address of the data in the cache block can include an address portion that can be used to tag the address of the data. The memory controller stores the address of the data in the first cache block in the third area, and specifically includes: the memory controller stores the address of the data in the first cache block in the third area. In this way, if the memory controller determines that the address is stored in the third area, the data is considered to be hot data, and the second cache block to be replaced is determined in the first area; if it is determined that the address is not stored in the third area, The data is cold data, and the first cache block to be replaced is determined in the second zone.

Alternatively, the third zone is less than or equal to a preset threshold. In the embodiment of the present invention, the value of the preset threshold is not limited. Generally, the preset threshold is small, that is, the storage space of the third area is small. Since the third area is used to buffer the address in the second level memory of the data that is replaced from the second area, if the storage space of the third area is large, the first access request may continuously hit the third area due to In the embodiment of the present invention, the first area is considered to store hot data, and in this case, a lot of hot data is replaced. Therefore, the storage space of the third area should be made small so as to store as much as possible in the second area. The cold data is replaced, so that the hot data stored in the first zone is replaced as little as possible, thereby improving the cache hit ratio.

The method of cache replacement provided above is explained by a specific example below.

FIG. 6 is an interaction diagram of a method for cache replacement according to an embodiment of the present invention. The following is an example of "the processor sends a pending access request to the memory controller, and the pending access request carries the data address to be accessed" as an example. The method shown in Figure 6 includes:

S201: The processor sends a to-be-access request to the memory controller. The to-be-accessed request carries the to-be-accessed data address, and the to-be-accessed data address is the address of the to-be-accessed data in the second-level memory.

S202: The memory controller receives the to-be-accessed request, and determines, according to the to-be-accessed data address, whether the to-be-accessed request hits the first zone and the second zone in the first-level memory.

If yes, execute S203; if no, execute S204.

S203: The memory controller sends an access response message to the processor, where the access response message includes data to be accessed.

After executing S203, it ends.

S204: The memory controller sends a to-be-access request to the second-level memory.

S205: The second level memory receives the to-be-accessed request, and sends an access response message to the memory controller, where the access response message includes data to be accessed.

S206: The memory controller receives the to-be-accessed data, and determines whether the to-be-accessed request hits the third zone.

If yes, execute S207; if no, execute S208.

S207: The memory controller determines the cache block to be replaced in the first area, and replaces the data in the cache block to be replaced with the data to be accessed.

After executing S207, it ends.

S208: The memory controller determines the cache block to be replaced in the second area, replaces the data in the cache block to be replaced with the data to be accessed, and then stores the address of the data in the cache block to be replaced in the third area.

After executing S208, it ends.

The solution provided by the embodiment of the present invention is mainly introduced from the perspective of a memory controller. It can be understood that in order to implement the above various functions, the memory controller includes hardware structures and/or software modules corresponding to the execution of the respective functions. Those skilled in the art will readily appreciate that the present invention can be implemented in a combination of hardware or hardware and computer software in combination with the modules and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods for implementing the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

The embodiment of the present invention may divide the function module into the memory controller according to the foregoing method example. For example, each function module may be divided according to each function, or two or more functions may be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of the module in the embodiment of the present invention is schematic, and is only a logical function division, and the actual implementation may have another division manner.

In the case of using various functional modules divided by respective functions, FIG. 7 shows a schematic structural diagram of a memory controller 7. The memory controller 7 may include a receiving module 701, an obtaining module 702, a determining module 703, and a replacement module 704. Optionally, the memory controller 7 further includes: a cache module 705. The function of each of the functional modules may be inferred according to the steps in the method embodiments provided above, or may refer to the content provided in the above content of the invention, and details are not described herein again. .

In the case of adopting an integrated module, the above-mentioned obtaining module 702, determining module 703, replacing module 704 and cache module 705 can all be integrated into one processing module in the memory controller 7. Both the receiving module 701 and the transmitting module described above can be integrated into one communication module in the memory controller 7. A storage module 706 may also be included in the memory controller 7.

FIG. 8 is a schematic structural diagram of a memory controller 8 according to an embodiment of the present invention. The memory controller 8 may include a processing module 801 and a communication module 802. The processing module 801 is used to control and manage the operation of the memory controller 8. For example, the processing module 801 is configured to support the memory controller 8 to execute S102-S104 in FIG. 3, S202 and S206-S208 in FIG. 6, and the like. And/or other processes for the techniques described herein. The communication module 802 is configured to support communication between the memory controller 8 and other network entities. For example, the communication module 802 is configured to support the memory controller 8 to execute S101 in FIG. 3, S201 and S203-S206 in FIG. 6, etc., and/or Other processes of the techniques described herein. In addition, the memory controller 8 may further include: a storage module 803. The storage module 803 is configured to store a corresponding method of the memory controller 8 to perform any of the cache replacements provided above. Program code and data.

FIG. 9 is a schematic structural diagram of a computing device 9 according to an embodiment of the present invention. The computing device 9 can include a processor 901, a memory controller 902, a first level memory 903, a second level memory 904, a transceiver 905, and a bus 906. The processor 901, the memory controller 902, and the first level memory 903 The second level memory 904 and the transceiver 905 are connected to each other through a bus 906. The processor 901 can be a CPU, a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or Other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It is possible to implement or carry out the various illustrative logical blocks, modules and circuits described in connection with the present disclosure. The processor may also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like. The bus 906 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 9, but it does not mean that there is only one bus or one type of bus.

The steps of the method or algorithm described in connection with the present disclosure may be implemented in a hardware manner, or may be implemented by a processing module executing software instructions. The software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC.

Those skilled in the art will appreciate that in one or more examples described above, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored in a computer readable medium or transmitted as one or more instructions or code on a computer readable medium. Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage medium may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments of the present invention have been described in detail with reference to the preferred embodiments of the present invention. protected range.

Claims

A method of cache replacement, the method being applied to a computer system, the computer system comprising a memory controller and a hybrid memory, the hybrid memory comprising a first level memory and a second level memory, the A primary memory is used to cache data in the second level of memory, the first level of memory supports cache access, and the method includes:

The memory controller receives a first access request, where the first access request carries a first target address, and the first target address is the first data to be accessed by the first access request at the second level The address in the memory;

When determining that the first access request misses the first area and the second area in the first level memory according to the first target address, the memory controller is from the first target address according to the first target address Acquiring the first data in the secondary memory, wherein the first level memory includes the first area, the second area, and a third area, where the first area is used to cache hot data, the first The second area is for buffering cold data, and the third area is for buffering an address in the second level memory of data that is replaced from the second area;

When determining that the first access request misses the third area according to the first target address, the memory controller determines a first cache block to be replaced in the second area;

The memory controller replaces data in the first cache block with the first data.
The method according to claim 1, wherein after the memory controller replaces the data in the first cache block with the first data, the method further includes:

The memory controller stores an address of the data in the first cache block in the third zone.
The method according to claim 1 or 2, wherein the method further comprises:

The memory controller receives a second access request, where the second access request carries a second target address, and the second target address is the second access request to be accessed second data at the second level The address in the memory;

When determining that the second access request misses the first area and the second area in the first level memory according to the second target address, the memory controller is from the second target address according to the second target address Acquiring the second data in the secondary storage;

When determining that the second access request hits the third area according to the second target address, the memory controller determines a second cache block to be replaced in the first area;

The memory controller replaces data in the second cache block with the second data.
The method according to any one of claims 1 to 3, wherein the first zone is larger than the second zone.
The method according to claim 1, wherein the memory controller determines the first cache block to be replaced in the second area, including:

The memory controller determines any of the data in the second zone or a cache block in which the earliest data to be written is located as the first cache block to be replaced.
The method according to any one of claims 1 to 5, wherein the third zone is less than or equal to a preset threshold.
A computing device, characterized in that the computing device comprises a memory controller and a hybrid memory. The hybrid memory includes a first level memory for buffering data in the second level memory, and a first level memory supporting cache access, the memory controller to:

Receiving a first access request, where the first access request carries a first target address, where the first target address is an address of the first data to be accessed by the first access request in the second level memory;

Obtaining, according to the first target address, that the first access request misses the first area and the second area in the first level memory, acquiring from the second level memory according to the first target address The first data, wherein the first level memory includes the first area, the second area, and a third area, the first area is used to cache hot data, and the second area is used to cache Cold data, the third area is for buffering an address in the second level memory of data that is replaced from the second area;

Determining, in the second area, a first cache block to be replaced when determining that the first access request misses the third area according to the first target address;

The data in the first cache block is replaced with the first data.
The computing device of claim 7, wherein the memory controller is further configured to:

The address of the data in the first cache block is stored in the third zone.
The computing device according to claim 7 or 8, wherein the memory controller is further configured to:

Receiving a second access request, where the second access request carries a second target address, where the second target address is an address of the second data to be accessed by the second access request in the second level memory;

When determining that the second access request misses the first area and the second area in the first level memory according to the second target address, acquiring from the second level memory according to the second target address The second data;

Determining, in the first area, a second cache block to be replaced when determining that the second access request hits the third area according to the second target address;

The data in the second cache block is replaced with the second data.
The computing device of any of claims 7 to 9, wherein the first zone is larger than the second zone.
The computing device of claim 7, wherein the memory controller is specifically configured to:

The cache block in which any of the second area or the oldest data is located is determined as the first cache block to be replaced.
The computing device of any of claims 7 to 11, wherein the third zone is less than or equal to a predetermined threshold.