JPH05224881A - Fifo buffer circuit - Google Patents

Abstract

PURPOSE:To preferentially output urgent data as well as the operation of first-in first-out (FIFO). CONSTITUTION:A write data detection part 25 detects whether data to be written in a memory part 24 are normal data or preferential data. Write pointers WP 26 and 27 count up at the same time and designate the write addresses of the normal data and preferential data. At the time when inputting the preferential data, the WP26 is set on standby temporarily at that address and with the standby address of the WP26 as a reference, the WP27 designates the write address from there. An output data detection part 29 detects whether data are normal data or preferential data, a read pointer RP30 designates a normal read address, and a read pointer RP31 is immediately started after write is completed in the case of the preferential data and designates the read address with the standby address of the WP26 as a reference. A comparator part 33 compares the outputs of the WP and RP and detects whether any preferential data exists or not, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a FIFO buffer circuit for performing data communication between multiprocessors operating asynchronously.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration example of a conventional FIFO buffer circuit. In FIG. 3, 1 is FI
The FO buffer circuits 2 and 3 are respectively composed of a microprocessor and the like, and are a write side control unit for writing data into the FIFO buffer circuit 1 and a read side control unit for reading out data. The FIFO buffer circuit 1 has a write side and a read side separately and is capable of asynchronous write access and read access from a microprocessor (hereinafter referred to as a memory section) 4 and a data transfer to the memory section 4. A write pointer (hereinafter referred to as WP) 5 for designating a write address and a read pointer (hereinafter referred to as RP) for designating a data read address
6 and the output of WP5 and the output of RP6 are compared, and when the held data in the memory unit 4 is in the "empty" state, or
It is composed of a comparison unit 7 which outputs a signal which becomes effective when it is in a "full" state.

Hereinafter, for ease of understanding, the write side control unit 2 and the read side control unit 3 handle 8-bit width data, and the maximum number of data stored in the memory unit 4 (hereinafter referred to as depth) is set. 4096 words. Therefore, W
The address width of the memory section 4 output by P5 and RP6 is 12 bits.

The WP 5 includes a write side control unit 2 to a memory unit 4
The ring type up-counter is enabled by the selection signal 10 when writing data to and is sequentially counted up by the write signal 9, and its output holds the data from the write-side control unit 2 in the memory unit 4. Used as an address. WP5 and RP6 are reset by the set signal 12 from the write side control unit 2 before the first write access to the memory unit 4, and the output thereof is "000h (hexadecimal number, the same applies below)". .. Therefore, the write data from the write-side control unit 2 via the data bus 8 is held in the memory unit 4 in ascending order from the lower address, and WP5 is counted up to the maximum value "FFFh" and then rotated at the next update clock. Then, the output becomes "00h" again, and the write data from the write side control unit 2 via the data bus 8 is held in the memory unit 4 again in ascending order from the lower address. Therefore, in the case of the conventional example where the depth of the memory unit 4 is 4096 words, the WP
The output of 5 is the number of times data is written by the write-side controller 2 X-40
96x (x: number of rotations of WP, that is, 000h → FFFh →
The number of times up to 000h) is shown.

The RP6 is composed of an up-counter similar to the WP5, and its output is used as an address for the read side control section 3 to read the data held in the memory section 4, and a reset signal from the write side control section 2 is used. It is reset at the same time as WP5 by 12 and its output is the initial output "0.
00h ". RP6 becomes valid by the selection signal 15 when the read side control section 3 reads data from the memory section 4, and its output is sequentially counted up by the read signal 14. Therefore, the read side control section By the read access of 3, the data held in the memory unit 4 is output in ascending order from the lower address to the data bus 13. After counting up to the maximum value "FFFh", RP6 rotates when the next update clock comes. , Its output is also "000
Then, the held data is output again in ascending order from the lower address of the memory unit 4. Therefore, the output of RP6 is the number of data read times Y-4096y (y: RP of the read side control unit 3 read from the memory unit 4). Number of rotations, x-1 ≤
The value of y ≦ x) is shown.

WP5 output value (x-4096x) and R
When the output value of P6 (Y-4096y) is the same, the comparison unit 7 determines that the memory unit 4 is not holding valid data waiting to be read from the read-side control unit 3, that is, the memory unit 4 is The empty state is detected, and the read side control unit 3 is notified by the empty signal 18. Also,
Output of WP5 + 1 value (X + 1-4069x) and RP6
When the output value (Y-4096y) becomes the same, the comparison unit 7 detects that the write data from the write-side control unit in the memory unit 4 is in the “full” state, and the full signal 17 is output. Notify the write control unit 2.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When communication between multiprocessors that operate asynchronously using the IFO buffer circuit 1 is performed, when there is still held data in the memory unit 4 inside the FIFO buffer circuit, the write side control unit 2 transfers to the read side control unit 3. When urgent transmission data occurs, the read-side control unit 3 can receive the urgent data only after reading all the held data in the memory unit 4 with only one FIFO buffer circuit. Therefore, in order for the read-side control unit 3 to preferentially read the emergency data, it is necessary to use a plurality of FIFO buffer circuits such as a normal data FIFO buffer circuit and a priority data FIFO buffer circuit. There has been a problem that the read side control unit 3 has to be aware of the port depending on the type of data, because there are a plurality of input / output ports for communication between multiprocessors.

The present invention solves the above problem and distinguishes normal data and priority data with one buffer, and the read side control section reads out emergency data from the write side control section without distinguishing the port. It is an object of the present invention to provide a FIFO buffer circuit capable of realizing the above.

[0009]

In order to achieve the above object, a FIFO buffer circuit of the present invention includes a write data detection unit for detecting whether write data from a write side control unit is normal data or priority data, and a priority A second write pointer unit that generates a data write address, a write pointer selection unit that selects whether the write address is a normal data write address or a priority data write address, and data that is output to the read-side control unit is normal data. Output data detection unit for detecting whether the read address is normal data or a priority data read address, and a second read pointer unit for generating a priority data read address from the read-side control unit. Compare the output of the read pointer selection part that selects the and the output of the write pointer part and the read pointer part The Rukoto, in which a comparison unit for detecting the presence or absence of presence and priority data of the data held in the FIFO buffer circuit.

[0010]

With the above configuration, the write data detection unit detects whether the write data from the write side control unit is normal data or priority data, and when the write data from the write side control unit is the priority data, the second data When the write pointer selection unit starts counting up and the address indicated by the second write pointer unit is selected by the write pointer selection unit, the priority data is sequentially written to the address indicated by the second write pointer unit. At the same time, the read side control unit and the write side control unit are notified that the priority data is held in the FIFO buffer circuit. Then, immediately after the priority data is written, the output data detection unit activates the second read pointer unit, and at the same time, the read pointer selection unit selects the address indicated by the second read pointer, whereby the read-side control unit Priority data is output to. Further, the comparator detects the presence / absence of data held in the FIFO buffer circuit and the presence / absence of priority data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a FIFO buffer circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 21 is a FIFO buffer circuit, and 22 and 23 are respectively a write-side control section and a read-side control section which are constituted by a microprocessor or the like, as in the conventional example described above. FIFO
The buffer circuit 21 includes a memory unit 24 similar to the conventional example, a write data detection unit 25 that detects whether the write data from the write-side control unit 22 is normal data or priority data, and normal data in the write data detection unit 25. If judged, the memory section 24
When the write data detection unit 25 determines that the normal data write address to the WP 26 has the same function as the WP 5 shown in the conventional example and the write data detection unit 25 determines the priority data write address, the priority data write address to the memory unit 24 is specified. , The WP5 shown in the conventional example is provided with a function for setting input data as an output, and the address indicated by WP26 when the write data to the memory section 24 is normal data, the write data to the memory section 24 has priority. In the case of data, the same function as the RP7 shown in the conventional example for selecting the address indicated by the WP27 and designating the WP selecting section 28 for outputting to the memory section 24 and the read address of the normal data held in the memory section 24 is provided. Have R
P30, an RP31 having a function of setting input data as an output to the RP6 shown in the conventional example for designating a read address of the priority data when the priority data is written in the memory section 24, and the memory section 24 Immediately after the priority data is written in the output data detection unit 29 for activating the RP31.
When the data held in the memory unit 24 is only normal data, the address indicated by RP30 is selected, and immediately after the priority data is written in the memory unit 24, the address indicated by RP31 is selected and output to the memory unit 24. RP selector 32 and WP26, W
It comprises a comparator for detecting the presence / absence of data held in the memory unit 24 and the presence / absence of priority data by comparing the outputs of P27, WP30 and WP31.

First, in order to facilitate the description of the operation in the FIFO buffer circuit 21, the operation of the comparison section 33 will be described. The first operation is a value (B-4096b) <B: output value of WP27 indicating the final address of write priority data.
Priority data write count, b: WP27 rotation count>, and output value of RP30 indicating the start address of read normal data (C-4096c) <C: Normal data read count, c:
RP30 rotations> and if they are the same, the comparison section
33 detects that the memory section 24 is "empty",
The read side control unit 23 is notified by the empty signal 54 which becomes effective at the “L” level.

The second operation is the output +1 value (B + 1-4069) of WP27 indicating the final address of the write priority data.
b) and RP30 indicating the start address of the read normal data
When the output value (C-4096c) becomes the same, the comparison unit 33 detects that the write data from the write-side control unit 22 in the memory unit 24 is in the "full" state, and the "L" level is obtained. The write side control unit 22 is notified by the full signal 53 that is valid at the level. In the first operation and the second operation, WP
Although the output value of 27 and the value of RP30 are compared, this is as will be described later. The retention address of the priority data retention data always comes after the normal data retention address and is retained at a higher address. Sagging that has a
The "empty" and "full" states of the memory unit 24 are detected by comparing the priority data write final address and the normal data read final address, that is, the outputs of WP27 and RP30.

The third operation is the value (A-4096a) of the output of WP26 indicating the final address of the write normal data,
The value (B-4069b) of the output of WP27 indicating the final address of the write priority data is compared, and if they are not equal, it is detected that there is retained priority data in the memory unit 24, and a valid priority data present signal at the "L" level. 52 is generated and output to the WP 27, the output data detection unit 29, the RP 31, and the RP selection unit 32, and the write side control unit 22 and the read side control unit 23 are notified.

Next, regarding the write operation from the write side control section 22 and the read operation from the read side control section 23, the flow chart shown in FIG. 2 and the write data detection section 25 shown in [Table 1] and [Table 2]. This will be described with reference to the truth table showing the relationship between the input and output of the read data detection unit 29 and the read data detection unit 29.

[0016]

[Table 1]

[0017]

[Table 2]

When normal data is written from the write side control unit 22 to the memory unit 24 (FIG. 2: state A), first the FIFO
The WP26, WP27, RP30, and RP31 in the buffer circuit 21 are reset by the reset signal 37 from the write-side control unit 22 and have an initial value of "000H (hexadecimal number)".
After that, the write side control unit 22 receives the "H" level priority signal 38 and the "L" level valid selection signal 36 from the write side control unit 22. When these signals are input to the write data detector 25, the write data detector 25
Normally detects a data write state, and simultaneously outputs the selection signal 39 and the selection signal 40 which are valid at the "L" level to WP26 and WP27 (Table 1: state 2). As a result, WP26 and WP27, which are simultaneously effective, are sequentially counted up simultaneously by the write signal 35. At this time, WP
The selection unit 28 selects the WP output 41, which is the output of the WP 26, when the priority signal 38 of the “H” level is input, whereby the output of the WP 26 is output to the memory unit 24 as the write address of the normal data, Normal data is sequentially written to the address indicated by WP26.

At this time, since the output of WP27 is also counted up at the same time as the output of WP26, the normal data write operation is repeated and the output of WP27 is output as shown in the second operation of the comparison unit 33. +1 value (B + 1-4
096b) and the value of the output of RP30 (C-4096c) become equal, the comparing section 33 detects the "full" state of the memory section 24, and the write side control section is activated by the full signal 53 which becomes effective at the "L" level. Notify 22.

When the normal data held in the memory section 24 is read from the read side control section 23 (FIG. 2: state B), first, the output data detecting section 29 in the FIFO buffer circuit 21 is read by the read side. The control unit 23 inputs the selection signal 45 which becomes valid at the “L” level, and the comparison unit 33 inputs the priority data presence signal 52 at the “H” level. When these signals are input to the output data detection unit 29, the output data detection unit 29 detects the normal data read state and outputs the selection signal 48 which becomes valid at the “L” level to the RP 30 (Table 2: State 6). ). The RP 30 that has become valid by this is sequentially counted up by the read signal 44. At this time, the RP selector 32 is "H".
The RP output 50, which is the output of the RP 30, is selected by inputting the level priority data present signal 52, whereby the output of the RP 30 is output to the memory unit 24 as the read address of the normal data, and the address indicated by the RP 30 It is read out sequentially.

As described in the first operation of the comparison unit 33, the normal data read operation is repeated and the output value of WP27 (B-4096b) and the output value of RP30 (C-
4096c) are equal, the comparing unit 33 detects the "empty" state of the memory unit 24 and notifies the write side control unit 23 of the empty signal 54 which becomes valid at the "L" level.

When the memory section 24 in the FIFO buffer circuit 21 is not in the "empty" state, that is, the write side control section 22.
If the priority data is written from the write-side control unit 22 to the memory unit 24 in the state before all the normal data is read from the read-side control unit 23 (FIG. 2: state C), first write The data detection unit 25 includes a write-side control unit 22.
From the priority signal 38 that becomes valid at the "L" level,
Selection signal 36 from the light side control unit 22 that becomes valid at the level
Is entered. When the write data detector 25 inputs these signals, the write data detector 25 detects the priority data write state and selects the "H" level selection signal 39 and "L".
The level selection signal 40 is output to WP26 and WP27 (Table 1: State 4). The WP 26, to which the selection signal 39 of "H" level is input, becomes inactive and stops counting up, and waits at the value of the normal data write final address + 1. In addition, when the “L” level selection signal 40 is input,
P27 becomes valid and is sequentially counted up by the write signal 35 based on the address indicated by WP26. At this time, the WP selecting section 28 inputs the "L" level priority signal 38 to select the WP output 42 which is the output of the WP 27, whereby the output of the WP 27 is stored in the memory section 24 as the write address of the priority data. The priority data is output and sequentially written to the address indicated by WP27. At this time, the area from the address indicated by WP26 on standby to the counted up address indicated by WP27 is the area in which the priority data is written.

As described in the third operation of the comparison unit 33, if the comparison unit 33 detects that the output value of WP26 and the output value of WP27 are not equal at this time, the priority data present signal 52 Becomes valid at the "L" level and notifies the read side control unit 23 and the write side control unit 22 that the priority data has been written. In addition, here, as in the case of normal data writing, the value of the output of WP27 + 1 (B + 1-
4096b) and the value of the output of RP30 (C-4096c) become equal, the comparator section 33 detects the "full" state of the memory section 24, and the full signal 53 becomes effective at the "L" level.
Is output to the light side control unit 22. Further, the comparison unit 33 also causes the write data write side control unit 52 to have the priority data presence signal 52 of the “L” level while the priority data is held in the memory unit 24.
However, the write-side control unit 22 cannot write new normal data while the priority data presence signal 52 is at the "L" level. Here, since the priority data is immediately read from the read-side control unit, the memory unit 24 holds the priority data for a very short time, so that the communication efficiency does not deteriorate.

When priority data is held in addition to normal data in the memory section 24 in the FIFO buffer circuit 21,
When the priority data held in the memory unit 24 is read from the read-side control unit 23 (FIG. 2: state D), the output data detection unit 29 determines that the read-side control unit 23 is valid at the “L” level. Selection signal 45 and the signal with priority data from the comparison unit 33
52 is entered. When these signals are input to the output data detection unit 29, the output data detection unit 29 detects priority data read and outputs the "H" level selection signal 48 and the "L" level selection signal 49 to RP30 and RP31. Yes (Table 2:
State 7). RP30 which input the selection signal 48 of "H" level
Becomes an invalid state, and by stopping the count-up, it waits at the value of the normal data read final address + 1. In addition, the RP31 inputting the selection signal 49 of "L" level
Becomes valid and is sequentially counted up by the read signal 44. At this time, the RP selecting section 32 receives the priority data presence signal 52 of "L" level, and the RP31
The RP output 51, which is the output of, is selected.
The output of RP31 is output to the memory unit 24 as the read address of the priority data, and the priority data is sequentially read from the address indicated by RP31.

At this time, the RP 31 which receives the output of the WP 26 as a data input receives the priority data present signal 52 which is output from the comparison section 33 and is at the “L” level while the priority data is held in the memory section 24 as a load input. Therefore, by setting the data input as output data at the falling edge of the priority data present signal 52, the address indicated by WP26,
That is, the count-up is started from the top address of the written priority data. Therefore, when the priority data is written in the memory unit 24, the read-side control unit 23 receives a notification that the priority data is held, and immediately outputs the priority data in the memory unit 24 without providing a port for the priority data. Can be read first.

When all the retained priority data in the memory section 24 have been read and the output value of WP26 and the output value of WP27 become equal (FIG. 2: state E), the priority data present signal 52
Becomes "H" level and output to WP27 and RP31,
It also notifies the read-side control unit 23 and the write-side control unit 22 that the retention priority data in the memory unit 24 has run out.
At this time, WP27 that uses the output of WP26 as data input
By setting the priority data present signal 52 as the load input,
By outputting the data input at the rising edge of the priority data presence signal 52, the output value of WP27 becomes the same as the output value of WP26, and as described above, the write side control unit 22 performs the normal data write operation and read side control. The unit 23 starts the normal data read operation.

[0027]

As described above, according to the present invention, one FIFO buffer circuit can mix and distinguish normal data and priority data, and the priority data can be transmitted first, so that the FIFO buffer circuit can be transmitted first. When performing data communication between multiprocessors using, it is not necessary to have multiple ports for normal data and priority data, so the reading side does not need to be aware of the port even when urgent transmission data occurs. Emergency data can be received, and the processing efficiency of communication software can be greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO buffer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a flow of operations in the FIFO buffer circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional FIFO buffer circuit.

[Explanation of symbols]

 21 FIFO buffer circuit 22 Write side control section 23 Read side control section 24 Memory section 25 Write data detection section 26 Write pointer section (WP) 27 Write pointer section (WP) 28 Write pointer selection section 29 Output data detection section 30 Read pointer section (RP) 31 Read pointer section (RP) 32 Read pointer selection section 33 Comparison section 35 Write signal 36 Selection signal 37 Reset signal 38 Priority signal 39,40 Selection signal 41,42 WP output 44 Read signal 45 Selection signal 48,49 selection Signal 50,51 RP output 52 Signal with priority data 53 Full signal 54 Empty signal

Claims (1)

[Claims] 1. A first processor and a second processor which operate asynchronously or a circuit similar thereto (hereinafter, referred to as a second processor).
(Which is referred to as a "processor"), and delivers data in a first-in / first-out format.
An IFO buffer circuit, a memory unit for temporarily holding data to be sent from the first processor to the second processor, and writing for determining whether write data from the first processor is normal data or priority data When the data detection unit and the write data detection unit determine that the data is normal data, the first write pointer unit that manages the write address of the normal data to the memory unit and the write data detection unit determine that the data is priority data. When the write data is written to the memory unit, the second write pointer unit that manages the write address of the priority data and the address indicated by the first write pointer unit when the write data to the memory unit is normal data, A write point for selecting the address indicated by the second write pointer section when the write data to the memory section is priority data. A selection unit, an output data detection unit for outputting priority data to a second processor when priority data is written in the memory unit, and a first read for managing a read address of normal data of the memory unit. A pointer section, a second read pointer section for managing a priority data read address of the memory section, and a read pointer selection section for selecting a priority data read address when priority data is written to the memory section, A comparison unit for detecting the presence / absence of retained data in the memory unit and the presence / absence of priority data by comparing the outputs of the write pointer unit and the read pointer unit described above, and If the data written in is only normal data, the first-in / first-out operation is performed. When the priority data in the memory unit from the first processor in the course of this operation is written, and notifies the second processor regardless of whether the data held in the memory unit, the second receiving the notification
The FIFO buffer circuit can read out the priority data first without reading all the normal data written in the memory.