JPH05289847A - Ring buffer control device - Google Patents

Abstract

PURPOSE:To quickly generate an address and a read/write permission status for write to and read from a ring buffer. CONSTITUTION:A data processor 1, a storage device 2 capable of random access, a holding means 3-1 where the number of effective bits of the ring buffer is held, a write pointer holding means 3-2, a read pointer holding means 3-3, write and read pointer incrementing means 3-4 and 3-5 which can designate the operation bit width, a subtractor 306, and a status generating means 3-7 are provided. The data processor 1 reads out pointers and the number of effective bits as control data of the ring buffer from the storage device 2 and sets values to respective holding means, and the status is generated based on these values, and values held in pointer holding means are incremented and are written in the storage device 2 when the data processor 1 writes pointers in the storage device 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to generating a read pointer, a write pointer and a buffer state for controlling a buffer memory having a ring structure used in a data processing device. The present invention relates to a ring buffer management device that stores a plurality of pointer sets in a randomly accessible storage device and manages the storage device in common with the data processing device.

[0002]

2. Description of the Related Art In a data processing device, a buffer memory having a ring structure is used in various processing steps. As shown in FIG. 9, this ring buffer uses two pointers, a write pointer holding an address to write data and a read pointer holding an address to read data, and an ordinary RAM is used to store data in a FIFO.
(First In First Out) Configure memory.

In a data processing apparatus using a large number of ring buffers, installing pointer-dedicated hardware causes an increase in the amount of hardware and causes inconvenience. Therefore, the pointer itself is usually stored in the RAM. When accessing the ring buffer, it is necessary to judge the buffer status such as whether there is room for writing or read data by the difference between both pointers.

FIG. 10 shows a process of writing as an example of a process of accessing the ring buffer.

In the writing process, the write pointer and the read pointer are read from the RAM, and when the difference between the read pointer and the write pointer is not "1", there is room for writing (write permission), and the data is written at the position indicated by the write pointer, and thereafter, Increment the write pointer and write back to RAM. Here, it will be described in the following example that it takes a lot of processing time to increment the pointer and calculate the difference.

The size of the ring buffer is set to 8 which is a power of 2 for easy calculation, and the following situation is assumed.

Number of buffer entries: 8 (number of effective bits = 3 bits) Effective range of pointer: 1000h to 1007h (h
Indicates a hexadecimal number) Write pointer value: 1007h Read pointer value: 1001h Pointer difference is made only for the lower 3 bits, which is the effective bit number. That is, the operation of (read pointer-write pointer) =-6 (FFFAh) is performed, and "2" is obtained by setting the digit of the effective bit number or more to "0".
In the operation for setting the upper bit to “0”, “1” is set for the number of valid bits from the least significant bit.
It is sufficient to perform a logical product with h. The numerical value that makes this upper level "0" is simply called "range".

In order to increment the write pointer, the calculation of 1007h + 1h = 1008h is performed, the range and the logical product are calculated, and only the number of effective bits is left to "0".
000h ”and derive the minimum value of the effective range (1000
In addition to h), the increment result is 1000h.

In the reading process, the difference between the two pointers is "
The description is omitted because the procedure is almost the same except that the reading is prohibited when it is "0".

[0010]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The minimum address is stored in RAM along with the pointer, and a very large number of memory accesses occur. Further, correction by the range is always necessary for incrementing the read / write pointer and calculating the difference. Therefore, there is a problem that the processing time of the pointer is long and the program execution speed is reduced.

Further, the hardware implementation of these pointers not only increases the circuit scale but also limits the number of ring buffers, which is a constraint in software design.

The present invention solves the above problems,
It is an object of the present invention to provide a ring buffer management device that rapidly generates an address for writing and reading to the ring buffer and a read / write permission status.

[0013]

In order to achieve the above object, the present invention is a first invention for holding a write pointer of a buffer memory having a ring structure read from a storage device.
Holding means, second holding means for holding the read pointer of the buffer memory read from the storage device, and third holding means for holding the number of entries of the buffer memory indicating the effective range of the write pointer and the read pointer. The difference between the holding means and the write pointer held by the first holding means and the read pointer held by the second holding means is based on the number of entries of the buffer memory held by the third holding means. Calculating means for calculating the remaining entry capacity of the buffer memory, status means for instructing read / write of the buffer memory based on the remaining entry quantity calculated by the calculating means, and the status Means indicating that the buffer memory is accessible, a write pointer or a read After the buffer memory is accessed using a pointer composed of an updating means for updating the write pointer or read pointer, giving the updated value in the storage device.

[0014]

The data processing device sequentially reads the effective bit number, the read pointer, and the write pointer from the storage device. These values are stored in the corresponding holding means, and the computing means obtains the difference by the number of effective bits (the number of entries in the buffer memory), and the read-prohibited and write-prohibited statuses are generated as a result. The data processing device reads the generated status and determines whether or not the ring buffer can be used.

As a result, the data processing device does not need to operate the pointer. Furthermore, after writing / reading data to / from the storage device using the write pointer or the read pointer, the pointer must be updated and written back to the storage device. However, the updating means is updated by issuing an instruction to write back the pointer. It outputs a pointer value, which is written to storage. As a result, the data processing device does not need the pointer update operation.

Therefore, the management load of the buffer memory in the data processing device is significantly reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a ring buffer management device according to an embodiment of the present invention.

In the figure, the configuration of the present embodiment includes a data processing device 1, a randomly accessible storage device 2,
Effective bit number holding means 3-1 for holding the effective bit number of the ring buffer read from the storage device 2, and means 3-2 for holding the write pointer read from the storage device 2
And a means 3-3 for holding the read pointer read from the storage device 2.

Further, an incrementing means 3-4 for incrementing the write pointer and an incrementing means for incrementing the read pointer, which are incrementing means whose operation bit width is designated by the value indicated by the valid bit number holding means 3-1. The operation bit width is designated by the value indicated by the means 3-5 and the effective bit number holding means 3-1, and the outputs of the subtracter 3-6 and the subtractor 3-6 for obtaining the difference between the write pointer and the read pointer are " The status generating means 3-7 generates the write prohibition as the status when it is "1" and the read prohibition when it is "0".

Further, the function designating means 3-8 indicating that the function accessed by the data processing device 1, that is, the number of effective bits, the write pointer, the read pointer, and the status are accessed, and the data processing device 1 designates the write pointer. When writing to the storage device 2, the output of the write pointer increment means 3-4 is selected, and when writing the read pointer to the storage device 2, the output of the read pointer increment means 3-5 is selected. The write data selecting means 3-9 for selecting the data output by the data processing device 1 and the status generating means 3-7 for reading the status by the data processing device 1 are selected, and the storage device 2 in other cases. Read data selection means 3-10 for selecting the data read from.

The function designating means 3-8 identifies the accessed object as follows. The address width output by the data processing device 1 is 16 bits A
<15: 0>, and when A <15> = 1, A <1:
0> is decoded, and the data processing device 1 controls
A signal indicating the access function is generated by the read / write mode signal output using the bus as follows.

In read mode A <1: 0> = 0 Effective bit number set signal (RANGE
SET) A <1: 0> = 1 Write pointer set signal (WPTRS
ET) A <1: 0> = 2 Read pointer set signal (RPTRS
ET) A <1: 0> = 3 Status read signal (STATU
SR) In write mode A <1: 0> = 0 Use prohibited A <1: 0> = 1 Write pointer write-back signal (WPT
RW) A <1: 0> = 2 Read pointer write-back signal (RPT
RW) A <1: 0> = 3 Prohibition of use When A <15> = 0, it is assumed that the normal access of the storage device 2 is selected, and the above signal is not output.

The total address range of the storage device 2 is 0000h
~ 32FF of 7FFFh, address A <1
4: 0> is given. The data bus width is 16 bits.

The status generating means 3-7 is a subtractor 3-6.
When the output is "0", the reading is prohibited, and when it is "1", the writing is prohibited, and the data is output to the bit positions shown in FIG.

The subtractor 3-6 performs the operation of (read pointer-write pointer), and is configured as shown in FIG. 3 so that the digit higher than the designated effective bit number always outputs "0". In this embodiment, the upper limit of the number of entries is 256 and the number of effective bits is 8 bits. Therefore, only the lower 8 bits of both pointers are subject to calculation. Also, since the minimum number of entries is 4, the lower 2 bits are "
It is not necessary to set 0 ".

In FIG. 3, when the effective number of bits is given, the decoder 3-7A outputs logical values to the Y2 to Y7 terminals as shown in the truth diagram of FIG. Subtractor 3
-7B is an 8-bit full subtractor, and the output is 8-bit. The output of the upper 5 bits of the output of the subtractor 3-7B is A
The ND element 3-7C is connected, and the output of the decoder 3-7A is connected to the other input. The pointer difference is output by the output of the AND element 3-7C and the lower 2 bits of the output of the subtractor 3-7B.

With this configuration, when the number of effective bits = 3 is input, the decoder 3-7A outputs "1" only to the Y2 output, and "0" is output to Y3 to Y7. It Therefore, "0" is always output to the bit 3 to bit 7 of the pointer difference output, and the difference is output to the bit 0 to bit 2. For example, as described above, the read pointer is 1001h and the write pointer is 1007h.
Then, the pointer subtraction result is FAh, but <
Since "0" is output to the 7: 3> bit, the subtractor 3-
The output of 6 is 02h, and the correct pointer difference is obtained.

The increment means 3-4 and 3-5 perform an operation of +1 on the input value, but are configured as shown in FIG. 5 so as not to carry carry to a digit higher than the designated effective bit number. It

In FIG. 5, the decoder 3-4A has the same function as the decoder 3-7A. The increment is performed by the half adder 3-4B. The input X of the half adder 3-4B is a pointer value. Input Y of the least significant bit is "
1 ”is connected. Since the minimum number of entries is 4, the carry of bit 0 is directly connected to the input Y of bit 1. The output of the AND element 3-4C is input to the input Y of bit 2 to bit 7. Is connected to the first of the AND elements 3-4C.
Is connected to the output Y of the decoder 3-4A, and the second input is connected to the carry of the lower bits.

Since the maximum number of effective bits is 8, no half adder is provided for bits 8 to 15.

With the above-described structure, carry propagation to the bits having the number of effective bits or more is prevented, and the upper bits are not incremented. For example, as described above, when the write pointer is 1007h and the number of effective bits = 3, since there is no carry propagation to bit 3, the increment result is 1000h, and a correct pointer value is obtained. FIG. 6 shows the configuration of the half adder 3-4B.

Next, the operation of this embodiment having the above configuration will be described.

The data storage area of the ring buffer is 100.
8 words from 0h to 1007h and the number of entries are 8. The number of effective bits, which is the management information of the ring buffer, and the storage addresses of the write pointer and the read pointer are set to 3000h, 3001h, and 3002h, respectively.

The data processing device 1 initializes the management information before using the ring buffer. Since the number of entries is 8, the number of effective bits is 3 (= log ₂ 8), so 3 is assigned to address 3000h and 3001h and 3002.
At the address h, the beginning 1000h of the ring buffer is written.

A process in which the data processing device 1 writes data in the ring buffer will be described with reference to the flowchart of FIG.

First, the effective bit number, the write pointer, and the read pointer are read from the storage device 2, respectively, and at this time, the address A <15> = 1 is accessed. For example, the reading of the effective bit number is B000h (step 701). Here, A <14: 0> is stored in the storage device 2.
Since it is only given, the effective bit number of 3000h is read. Further, since A <15> = 1, the function instructing means 3-8 decodes A <1: 0> to RANG.
The ESET signal is output, and the valid bit number holding means 3-1 takes in the read valid bit number.

Similarly, when the write pointer reads B001h, the function instructing means 3-8 outputs the WPTRSET signal, and the write pointer holding means 3-2 has the storage device 2 of 3
The contents read from the address 001h are held (step 702).

By reading B002h as the read pointer, the function instructing means 3-8 outputs the RPTRSET signal, and the read pointer holding means 3-3 in the storage device 2 is 3002h.
The contents read from the address are held (step 70).
3).

Next, in order to check the write permission, the status is read from the address B003h (step 70).
4). At this time, since the function instructing means 3-8 outputs the STATUSR signal, the read data selecting means 3-10 outputs the STATUS signal output by the status generating means 3-7 to the data bus D. Therefore, the data read by the data processing device 1 is not the output of the storage device 2 but the status of the ring buffer. Here, the status generation means 3-
If the value output from the subtractor 3-6 is "1", the 7 outputs write prohibition (step 706). When the data processing device 1 confirms that writing is not prohibited, it writes the data to the address pointed to by the previously read write pointer (step 707).

The update of the write pointer is performed in the following procedure.

When the data processing device 1 writes to the address B001h for writing the write pointer, the function instructing means 3-8 outputs the WPTRW signal. Therefore, the write data selecting means 3-9 is in the write pointer incrementing means 3-. The data output by 4 is output to the write data bus WD. As a result, the value obtained by incrementing the write pointer is written in the storage device 2 (step 70).
8).

Next, a procedure for reading data will be described.

The reading of the number of valid bits, the write pointer, the read pointer, and the status is the same as the writing procedure, and the description thereof is omitted. If the status is checked and reading is not prohibited, that is, if the output of the subtractor 3-6 is not "0", the data at the address indicated by the read pointer is read. The read pointer is updated by writing to the address B002h. Since the function instruction means 3-8 outputs the RTPRW signal, the read pointer increment means 3 is stored in the storage device 2.
The -5 output is written.

Since the incrementing means 3-4 and 3-5 increment only the bit range based on the number of effective bits, the data processing device 1 can perform the correction based on the number of entries.
Does not have to be done.

Although the number of entries is 8 in the above description, since means for instructing the number of effective bits is provided,
A ring buffer having a desired power of 2 can be realized.

Next, a second embodiment according to the present invention will be described with reference to FIG.
Will be explained. Note that, in FIG. 8, elements having the same functions as those of the first embodiment are assigned the same reference numerals and explanations thereof are omitted.

The present embodiment is an embodiment in which the data processing device 1 operates by distinguishing the mode for accessing the storage device 2 and the mode for accessing the ring buffer management means as a normal operation, and particularly the former access. Is a memory access mode and the latter access is an I / O access mode.

In FIG. 8, the function instructing means 3-11 is used when the ring buffer access signal RBACCSS output from the address generating means 4 is valid.
Receiving the control signal CONTROL-P output from the controller and the lower 2 bits A <1: 0> of the address to generate a function selection signal. Since the generated signal is the same as that of the function instructing means 3-8, its explanation is omitted.

The address generating means 4 comprises a decoder 4-1, a control signal generating means 4-2, a base address holding means 4-3 and an address selector 4-4.

The decoder 4-1 has the I / O
The RBACCSS signal is output when the address for accessing the ring buffer management means is being output in the O access mode. It also decodes the address to be written in the base address holding means 4-3 and outputs a BAW signal. Here, for clarity of explanation, the I / O address used for access by the ring buffer management means is 02.
It is assumed that there are four words from 00h to 0203h, and the RBACCSS signal is output to any address. The BAW signal is output when there is a write at 0300h.

The control signal generating means 4-2 is an RBA.
When the CCSS signal is not output, the CONTROL-P signal output by the data processing device 1 is directly output as C
It is transmitted to the storage device 2 as an ONTOL-M signal. on the other hand,
When the RBACCSS signal is output, CONTR
The OL-P signal indicates the I / O access mode,
A control signal in the memory access mode is output to the CONTROL-M signal. The access end signal output from the storage device 2 is from CONTOL-M to CONTR.
The data is propagated to the OL-P signal and input to the data processing device 1.

The base address holding means 4-3 holds the base value of the address stored in the storage device 2 by a pointer or the like. As described later, the data processing device 1 to the lower 2
Since the bits are provided, the lower 2 bits of the address are not retained.

The address selector 4-4 is RBACCSS.
When no signal is output, the address A <15: 0> output by the data processing device 1 is set to ADDRESS-M <
15: 0>. On the other hand, when the RBACCSS signal is output, ADDRESS-M <15: 2
>, 14 bits output by the base address means 4-3 are output, and A <1: 0> is output to ADDRESS-M <1: 0>. That is, when accessing the ring buffer management means, the lower 2 bits of the address output by the data processing device 1 and the 14 bits of the base address are combined 1
The 6-bit address is output to the storage device 2.

Next, the operation of this configuration will be described.

The data processing device 1 sets the initial value of the ring buffer management data in the storage device 2. The address of this management data is set to 8000h to 8002h.

The data processor 1 sets the base address in the base address holding means 4-3 in order to specify the management data when accessing the ring buffer. In this example, 8000h is written to the I / O address of 0300h. The decoder 4-1 outputs a BAW signal, and the base address holding means 4-3 fetches and holds the data output by the data processing device 1 from the data bus D <15: 2>.

Next, in order to read the effective bit number, the data processing device 1 reads the I / O address = 0200h. The decoder 4-1 decodes the address and RBA
Output CCSS signal. Control signal generation means 4
-2 receives the RBACCSS signal and receives CONTROL-P
CONTROL-M the I / O read signal through which the signal propagates
The signal is output as a memory read signal. The address selector 4-4 combines the base address and A <1: 0> and outputs 8000h to the ADDRESS-M bus.
The storage device 2 outputs to the data read read data bus RD of the address 8000h. The function instructing unit 3-11 receives the RBACCSS signal, A <1: 0> and the read mode signal and outputs the RANGESET signal. As a result, the data on the RD bus is set in the valid bit number holding means 3-1.

Similarly, both pointers are read from the storage device 2 and set. Table 1 shows the relationship between the I / O address and the memory address.

[0060]

[Table 1] When the status is read, the memory address 8
003h is given to the storage device 2, and the address 8003h is read, but the read data selection means 3-10 is STA.
It is discarded because it selects TUS.

After the data processor 1 writes the data in the ring buffer, the write pointer needs to be updated. In this case as well, the write is performed at the I / O address = 0201h. The control generation means 4-2 is CONTRO
The I / O write mode is received from the LP signal, and the CONTO
The memory write mode is output to the RL-M signal. The address selector 4-4 is 8001h based on the base address.
To the ADDRESS-M bus. Function instruction means 3
-11 outputs the WPTRW signal. The write data selection means 3-9 is the write pointer increment means 3-4.
The increment value output by the write data bus WD
Output to. As a result, the storage device 2 can write the updated write pointer at the address 8001h.

The writing of the read pointer is performed in the same procedure, and the description thereof will be omitted.

In this embodiment, when accessing another ring buffer, it is only necessary to change the base address, and the same I / O address is used, so that the program of the data processing device is simplified. ..

Since the I / O address and the memory address are used separately, the memory can be arranged in the entire memory address space.

As a combination of the first embodiment and the second embodiment, the memory access and the buffer management means access are identified by a part of the address bus, and the base processing means is used to allow the data processing device 1 to manage the buffer. It is also possible to access different management data while keeping the same output address when accessing the means.

In both of the embodiments, the effective bit number is used to indicate the range of the pointer. However, the decoded signal as shown in FIG. 4 is stored in the storage device 2, and the effective bit number holding means is used. It may be stored in 3-1. In this case, the subtractor 3-7A and the increment means 3-4 to 3-5 do not have to perform the decoding. Whether to hold the effective number of bits or the decoding result depends on the technical choice.

[0067]

As described above, the availability of access to the ring buffer is determined by sequentially reading out the effective number of bits, the write pointer, the read pointer, and the four words of the status. After accessing the ring buffer, either the write or read pointer is accessed. Since the pointer is updated by the operation of writing one, the processing to be performed by the data processing device is extremely simplified, and the program can be executed at high speed.

Further, since the management information of the ring buffer can be held in the storage device, a large number of ring buffers can be managed, and the number of ring buffers can be managed by software, and the hardware can be changed. It has the advantage of not requiring it.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a structure of status data output by a status generation unit.

FIG. 3 is a configuration diagram of a subtracter that obtains a pointer difference in consideration of the number of effective bits.

FIG. 4 is a diagram showing a truth value of a decoder having an effective bit number.

FIG. 5 is a diagram showing an increment circuit in consideration of the number of effective bits.

FIG. 6 is a diagram showing a configuration of a half adder.

FIG. 7 is a diagram showing a write process of a ring buffer in the first embodiment.

FIG. 8 is a block diagram showing a second embodiment of the present invention.

FIG. 9 is a diagram showing a structure of a ring buffer.

FIG. 10 is a diagram showing a write process of a ring buffer according to a conventional method.

[Explanation of symbols]

 1 Data Processing Device 2 Storage Device 3-1 Effective Bit Holding Means 3-2 Write Pointer Holding Means 3-3 Read Pointer Holding Means 3-4 Write Pointer Incrementing Means 3-5 Read Pointer Incrementing Means 3-6 Subtractor 3-7 Status generation means 3-8 Read data selection means 3-9 Write data selection means 4 Address generation means 4-1 Decoder 4-2 Control signal generation means 4-3 Base address holding means 4-4 Address selector

Claims (2)

[Claims] 1. A first holding means for holding a write pointer of a buffer memory having a ring structure read from a storage device, and a second holding means for holding a read pointer of the buffer memory read from a storage device. And third holding means for holding the number of entries in the buffer memory indicating the valid range of the write pointer and the read pointer, the write pointer held by the first holding means, and the second holding means. The difference between the read pointer and the read pointer is calculated based on the number of entries in the buffer memory held in the third holding means, and the calculating means calculates the remaining number of entries in the buffer memory; Status that indicates whether to read or write in the buffer memory based on the remaining number of entries And the status means indicates that the buffer memory is accessible, the write pointer or the read pointer is updated after the buffer memory is accessed using the write pointer or the read pointer, and the updated value is updated. A ring buffer management device, comprising: an updating unit for giving to a storage device. 2. A fourth holding means for holding a write pointer, a read pointer, and a base address of a storage structure in the number of entries of the buffer memory, which are stored in the storage area, and when the buffer memory is accessed by an offset value. 2. The ring buffer according to claim 1, further comprising: address generating means for generating an access address in the buffer memory from the offset value and the base address held by the fourth holding means and giving it to the storage device. Management device.