JP3476104B2 - Digital control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital control device in which an arithmetic unit sequentially reads out instructions forming a processing program from a memory and processes the processing program.

[0002]

2. Description of the Related Art Some conventional general-purpose MPUs (microprocessor units) include a cache memory. A general-purpose MPU equipped with this cache memory stores, for example, a portion of a processing program that is locally repeated due to conditional branching or the like in advance from the memory in the cache memory and sequentially reads the instructions of the stored processing program. By processing this, the delay in memory access when reading an instruction from the memory outside the MPU is eliminated and the processing speed is increased.

When the conventional general-purpose MPU receives an entry request for a processing program that is not stored in the cache memory, it starts to access a processing instruction to an external memory, and the processing program is internally stored in the cache. I'm trying to get it into.

[0004]

In a general-purpose MPU having such a conventional cache memory, a portion that is locally repeated in a processing program due to conditional branching or the like is stored in advance from the memory in the cache memory. Although the processing speed of the processing program is certainly increased,
Nevertheless, when an entry request for a processing program that is not stored in the cache memory is received, it is necessary to start accessing the external memory and load the processing program into the cache. There was a problem that it occurred.

In particular, a program controller (hereinafter, P
The ladder program used for the LC) is different from the processing program generally used by the general-purpose MPU,
There is almost no conditional branching, and the feature is that the program is executed sequentially from the beginning to the end.
Therefore, the M including the cache memory that constitutes the PLC
The PU has a problem that it does not work effectively unless the entire area of the program is cached.

Therefore, the present invention has been made in view of the above problems.
By incorporating several instructions that are always needed,
An object of the present invention is to provide a digital device which eliminates waiting for access time when fetching a processing program into the cache and performs high-speed processing.

[0007]

[0008]

In order to achieve the above-mentioned object, the invention according to claim 1 is such that the arithmetic unit sequentially reads out the instructions constituting the processing program on the memory and processes the processing program. in the control device, de
Data storage means, address comparison means, and address generation means
And the data storage means is processed by the arithmetic unit.
If there are a plurality of instruction storage areas in which the instructions to be stored are stored in advance,
Both of the above instructions are stored in each of these multiple instruction storage areas.
Address storage area that stores the address value in memory
And whether the instruction has already been read by the arithmetic unit
Provided with a flag storage area that stores a flag indicating whether or not
If the flag in the above flag storage area is checked,
As a result, there are few flags that indicate that the data has been read by the calculation unit.
If there is at least one, the instruction corresponding to that flag
Information that the storage area exists as an empty area is displayed above.
It is output to the dress generation unit, and the address comparison means
When the arithmetic unit receives an instruction to process, the address of that instruction is received.
Address value and the address of the instruction stored in the above data storage
The address generation means compares the address value with the address value.
As a result of comparison by the address comparison means, the above two address values match.
If there is not, the address value shown by the above calculation unit is unchanged.
Address value to access the above memory
On the other hand, if the above two address values match, the above data
There is a free area in the above instruction storage area from the storage means.
While there is information to that effect, the instruction storage area in that empty area is saved.
Address to access the above memory to store instructions
Is generated .

[0009]

According to a second aspect of the present invention, in the first aspect of the present invention, the address generation means includes address value storage means for storing an address value for accessing the memory, When the address comparison unit receives information indicating that the address value indicated by the arithmetic unit does not match the address value of the instruction read by the data storage unit, the address value indicated by the arithmetic unit is stored in the address value storage unit. If there is information indicating that there is a free area from the data storage means when the values are stored and coincides, a value obtained by adding 1 to the address value stored in the address value storage means is obtained,
An address addition / storing means for storing again in the address value storing means is provided.

The invention according to claim 3 is the same as claim 1 or
Is used in a programmable controller.

[0012]

According to the present invention as described above, when the address comparing unit receives information indicating that the address value indicated by the arithmetic unit does not match the address value of the instruction stored in the data storing unit, the address generating unit generates the address. While the address value indicated by the arithmetic unit is directly accessed to the memory by the means, when the information indicating the coincidence is received, the arithmetic operation is continued until the information indicating that the empty area exists from the data storage means is continued. The unit generates an address value of an instruction to be processed, and accesses it to a memory. Then, the instruction read from the memory is stored in the empty area of the data storage means.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment showing a digital controller according to the present invention.

The digital control device of this embodiment comprises a memory 1, a calculation unit 2, a data storage unit 3, an address comparison unit 4, an address generation unit 5 and a memory timing control unit 6.

The memory 1 is a RAM (Randam Access Memo).
ry), a ROM (Read Only Memory), and the like, and stores a processing program processed by the arithmetic unit 2.

The arithmetic unit 2 has a built-in program counter (not shown) indicating the address value of the next instruction to be executed stored in the memory 1, and the program counter value is used for the address comparison unit 4 which will be described later. It is configured to be output to a data storage unit 3 to be described later via the, to read the instruction from the data storage unit 3 and process the instruction.

The data storage unit 3 stores the instruction to be processed by the arithmetic unit 2 in advance before outputting it to the address comparison unit 4, and as shown in FIG. And a data read control circuit 32.

This storage buffer 31 has already been operated by the arithmetic unit 2.
Read determination flag storage area 31a having a read determination flag indicating whether or not data has been read, an address storage area 31b for storing the address value stored in the memory 1, and an instruction storage area for storing an instruction. Three
1c and.

Incidentally, 1 is set in the read determination flag storage area 31a at the location where the instruction is read to the arithmetic unit 2, while 0 remains at the location where the instruction is not yet read. .

The access method of the storage buffer 31 is a ring format. That is, in the storage buffer 31, the access targets of the stored data are connected in the order of addresses (addresses that the storage buffer 31 has), and after the last address is accessed, the first address (address 0) is returned again. It is supposed to be accessed.

The data read control circuit 32 monitors the read determination flag storage area 31a of the storage buffer 31 and detects the read determination flag (1) indicating that the instruction has already been read by the arithmetic unit 2. Information indicating that there is a free area for receiving a new command is output to the address generator 5.

By doing so, the data read control circuit 32 assigns the instruction read from the memory 1 and the address value of the instruction read from the memory timing control unit 6 to the empty area. It can be stored in the instruction storage area 31c and the address storage area 31b. At this time, the data read control circuit 32 sets a read determination flag (0) indicating that it has not been read from the arithmetic unit 2 in the read determination flag storage area 31a.

Further, when the data read control circuit 32 receives the next instruction request signal from the address comparison section 4 which will be described later,
A flag (1) indicating that there is an empty area for receiving a new instruction is set in the read determination flag storage area 31a in the instruction read by the arithmetic unit 2. By doing this, the storage buffer 31 stores in the arithmetic unit 2
I always try to secure instructions to read.

Further, the data read control circuit 32 has information (that is, the storage buffer 31) indicating that the requests from the address comparison unit 4 to be described later from the operation unit 2 are not continuous.
(Information for newly storing instructions in all of the above), a flag (1) indicating that there is an empty area for receiving new instructions is set in all of the read determination flag storage areas 31a. . By doing so, an instruction can be newly stored in all the storage buffers 31. This corresponds to the case where the address jumps, such as interrupt processing or cyclic processing performed by PLC.

The address comparison unit 4 has the address value requested by the calculation unit 2 and the storage buffer 3 of the data storage unit 3.
1 is compared with the head address value of the data stored in 1, and information indicating whether or not they match is output to the data storage unit 3 and the address generation unit 5.

Here, the head address value of the data stored in the storage buffer 31 is the address value having the smallest address value in which 0 is stored in the read determination flag area 31a.

The address generation unit 5 uses the address requested by the arithmetic unit 2 and the information of the free space of the data storage unit 3 to the memory 1 to store the data in this free space. The address is designated through the control circuit 51, and is composed of a control circuit 51, a multiplexer 52, an address register 53 and an adder 54, as shown in FIG.

When the control circuit 51 receives from the address comparison unit 4 the information indicating that the addresses indicated by the arithmetic unit 2 and the addresses in the data storage unit 3 do not match,
The multiplexer 52 is instructed to set the address value of the instruction processed by the arithmetic unit 2 in the address register 53. Further, the control circuit 51 receives information on whether or not there is a free area in the buffer 31 of the data storage unit 3, and outputs that fact to the multiplexer 52.

The multiplexer 52 forms an address to access the memory 1, and the address register 53
Is output to the address register 53.
An address value for accessing the memory 1 is set.

The adder 54 adds the value 1 added to the address value stored in the address register to the data storage unit 3
Until the information that there is no free area in the control circuit 51,
It outputs to the multiplexer 52.

The memory timing control unit 6 is configured to access the memory 1 with timing of the address generated by the address generation unit 5.

Next, the operation of the digital controller will be described.

First, at the start of processing, when the digital control device of the present application is reset, the arithmetic unit 2 sets the built-in program counter to the start address of the processing program stored in the memory 1, This program counter value is output to the address comparison unit 4, and 1 is added to the program counter.

The address comparison unit 4 compares the program counter value with the start address value of the instruction stored in the storage buffer 31 of the data storage unit 3 and determines whether they match or not. The following operations are performed with.

(1) In case of coincidence When the program counter value and the start address value of the instruction stored in the storage buffer 31 of the data storage unit 3 coincide with each other, information to this effect is stored in the data. Output to the storage unit 3.

Then, the arithmetic unit 2 reads the instruction from the data storage unit 3 and processes it, and again performs the same processing as described above.

On the other hand, in the data storage unit 3, when the storage buffer 31 has a free area, information indicating that there is a free area in the address generation unit 5 even when the arithmetic unit 2 is reading an instruction. Is output.

The address generation unit 5 has a control circuit 5 which contains information indicating that there is a free area from the data storage area 3.
When it is received at 1, the control circuit 51 outputs information indicating that there is a free area in the data storage unit 3 to the multiplexer 52. The multiplexer 52 forms an address value to access the memory 1, and outputs this to the address register 53.

Here, the address value output from the multiplexer 52 is the address value obtained by adding 1 to the address value previously stored in the address register 53 by the adder 54.

The address value stored in the address register 53 is output to the memory timing control unit 6. The memory timing control unit 6 outputs the address value generated by the address generation unit 5 to the data storage unit 3 while timingally accessing the memory 1.

The data storage unit 3 stores the instruction read from the memory 1 and the address value from the memory timing control unit 6 in the instruction storage area 31c and the address storage area 31b in the empty area of the storage buffer 31. Then, the read determination flag area 31a flag corresponding to this is set to (0).

The same processing operation as above is performed by the data storage unit 3.
While outputting the information that the storage buffer 31 has a vacant area from the address generation unit 4, the data storage unit 3 stores the instruction to be processed by the arithmetic unit 2.

(2) When they do not match When the program counter value and the start address value of the instruction stored in the storage buffer 31 of the data storage unit 3 do not match, for example, interrupt processing or PLC is performed. When the address jumps as in the cyclic processing, the address comparison unit 4 compares the program counter value with
Information indicating that the start address value of the instruction stored in the storage buffer 31 of the data storage unit 3 is not continuous (that is, information for newly storing the instruction in all of the storage buffer 31) is stored in the data storage unit 3 And output to the address generator 5.

Then, the data read control circuit 32 of the data storage unit 3 sets a flag (1) indicating that there is an empty area for receiving a new instruction in all the read determination flag storage areas 31a, and Similarly, the instructions are stored in the data storage unit 3.

The digital control device described above is preferably applied to a programmable controller.

[0047]

As described above, according to the present invention, when the information indicating that the address value indicated by the arithmetic unit does not match the address value of the instruction stored in the data storage unit is received from the address comparison unit, While the address generating unit accesses the memory as it is, the address value indicated by the arithmetic unit, when the information indicating the coincidence is received, the information indicating that there is an empty area from the data storing unit continues to exist. Up to the address value of the instruction processed by the arithmetic unit,
This is accessed in memory. Then, since the instruction read from the memory is stored in the empty area of the data storage means, it is not necessary to directly access the memory having a slow external access speed.

Therefore, although the processing program is actually read from a memory having a slow external access speed, substantially the same performance as a high-speed memory can be obtained, and the arithmetic unit caches the processing program inside the cache. It is possible to eliminate waiting for access time when importing to.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a digital control device according to the present invention.

FIG. 2 is a block diagram showing the configuration of a data storage unit in FIG.

FIG. 3 is a block diagram showing a configuration of an address generation unit in FIG.

[Explanation of symbols]

1 memory 2 operation part 3 data storage 4 Address comparison unit 5 Address generator 6 Memory timing controller 31 storage buffer 32 data read control circuit 51 control circuit 52 multiplexer 53 Address Register 54 adder

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/38 G05B 19/02-19/05

Claims (3)

(57) [Claims] 1. A digital control device in which an arithmetic unit sequentially reads out instructions constituting a processing program on a memory and processes the processing program, in a digital storage device, a data storage means, an address comparison means, and an address generation.
Means for storing the instruction to be processed by the arithmetic unit in advance.
In addition to having multiple
And stores the address value of the above instruction on the memory.
It has already been read by the dress storage area and the above-mentioned calculation unit.
Flag case that stores a flag that indicates whether the instruction is
The storage area is provided, and as a result of checking the flag in the above flag storage area,
At least the flag indicating that it has been read by the arithmetic unit
If there is more than one, the instruction storage error corresponding to that flag
Information that the rear exists as a free area is the above address
When the address comparing means receives the instruction output by the generating section and processed by the calculating section , the address comparing section adds the instruction.
Response value and the instruction stored in the above data storage
The address generating means compares the address value with the address
If the values do not match, the address value indicated by the above calculation unit
Is the address value to access the above memory as it is
On the other hand, if the above two address values match,
From the data storage means
While there is information that it exists, the instruction storage
Access the above memory to store instructions in the rear
A digital control device characterized by generating an address value according to the above . 2. The address generating means does not match the address value storing means for storing the address value for accessing the memory, and the address value indicated by the arithmetic unit and the address value of the instruction read by the data storing means. When the information to the effect is received from the address comparison means, the address value indicated by the arithmetic unit is stored in the address value storage means, and if they match, it means that there is an empty area from the data storage means. while the information is present, according to claim 1, characterized in that it comprises an address adder / storage means a value obtained by adding 1 to the address value stored in the address value storing means, thereby again stored in the address value storage unit digital control unit according to. 3. The invention according to claim 1 or 2 ,
A digital controller characterized by being used in a programmable controller.