JPH0683581A - First-in first-out buffer circuit - Google Patents

Abstract

PURPOSE:To attain efficient data communication through the operation of a first-in first-out(FIFO) buffer circuit. CONSTITUTION:Three data counter sections 8, 9, 31 are provided in an FIFO buffer circuit 30, and a 1st count-down counter section 8 is used to count number of words of a memory section 4 in the FIFO buffer circuit, to detect packet data in one unit from a write side control section 2 and to inform a 2nd count- down counter section 31 of the detected data. An up-down counter section 9 is used to detect packet data in one unit from a read side control section 3 and to inform a 2nd count-down counter section 31 of the detected data, and the 2nd count-down counter section 31 receives a notice of the end of count by the 1st count-down counter section 8 and informs the output side of the number of read waiting packet data in the FIFO buffer detected by the up-down counter section 9 after receiving the notice of the end of count by the 1st count- down counter section 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a first-in first-out (FIFO) buffer circuit for performing packet data data communication between an input side and an output side between multiprocessors operating asynchronously.

[0002]

2. Description of the Related Art A FIFO buffer circuit is used between asynchronously operating multiprocessors to perform data communication.

A conventional FIFO buffer circuit will be described below with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of an example of a conventional FIFO buffer circuit. In FIG. 3, 1 is F
IFO buffer circuit, 2 write side control unit, 3 read side control unit, 4 dual port memory unit (hereinafter referred to as memory unit), 5 write pointer (hereinafter referred to as WP),
Reference numeral 6 is a read pointer (hereinafter, referred to as RP), 7 is a full state detection unit, 8 is a countdown counter unit (hereinafter, referred to as a first countdown counter unit in the present invention), and 9 is an up / down counter unit.

In FIG. 3, 14, 19, 25 and 28 are selection signals, 15 is a write signal, 16 and 18 are reset signals, 17,
21 is a data bus, 20 is a read signal, 22 is a write pointer output, 23 is a read pointer output, 24 is a full signal, 27 is a write end signal, and 29 is a read end signal.

FIG. 4 is a block diagram showing the internal configuration of the full state detecting section 7 of FIG. In FIG. 4, 10 is an adder,
11 is a comparator. FIG. 5 is a block diagram showing an internal configuration of the countdown counter section 8 of FIG. In FIG. 5, 12 is a 12-bit countdown counter, 13 is 12 inputs O
It is an R gate.

First, in FIG. 3, the memory section 4 of the FIFO buffer circuit 1 is a write-side control section 2 controlled by a first microprocessor on the write side and a read-side control section controlled by a second microprocessor on the read side. Read access and write access can be performed asynchronously with the unit 3. Further, WP5 designates a write address to the memory unit 4, and RP6 designates a read address of the memory unit 4.

As shown in FIG. 4, the full state detecting section 7 has a W
The output 22 obtained by adding (+1) to the pointer value of P5 by the adder 10 and R
When the output 23 of the pointer value of P6 is compared by the comparator 11 and coincides with each other, that is, when there is no free space in the memory unit 4, the full signal 24 that is effective is output. In the countdown counter unit 8, as shown in FIG. 5, the count value is decremented by 1 by the 12-bit countdown counter 12 every time the initial value is updated. The up / down counter unit 9 has two update clock inputs, one of which has a count number of (+1) by the update clock and the other of which has a count number of (-1) by the update clock.

Hereinafter, it is assumed that the write side control unit 2 and the read side control unit 3 have 8-bit width data and the maximum number of data stored in the memory unit 4 (hereinafter referred to as depth) is 4096 words. Therefore, the address width of the memory unit 4 output by WP5 and RP6 is 12 bits.

(1) When the memory section 4 is full.

The write control unit 2 outputs a selection signal 14 and a write signal 15 to the memory unit 4, and a reset signal 16 to the WP 5, respectively. The WP 5 composed of a ring type up counter is reset by the reset signal 16 from the write side control unit 2 before the first write access,
As a result, the initial output of WP5 is "000h (hexadecimal number, the same applies below)".

Next, the WP 5 is activated by the selection signal 14 at the time of writing data in the memory section 4, and is sequentially counted up by the write signal 15. The output of the WP 5 is the data from the write-side control unit 2 stored in the memory unit 4
It is used as an address to be stored and retained in. Therefore, the write data from the write side control unit 2 via the data bus 17 is held in the memory unit 4 in ascending order from the lower address, and the WP 5 counts up to the maximum value “FFFh”, and then at the next update clock. The data is circulated, the output becomes "000h" again, and the write data from the write-side control unit 2 via the data bus 17 circulates in the memory unit 4 again in ascending order from the lower address and is retained. Therefore, in the present example in which the depth of the memory unit 4 is 4096 words, the output of the WP 5 is the value of the number of cycles of X-4096. Is shown.

The RP6, which is a ring-type up counter, is reset by the reset signal 18 from the read side control unit 3 before the first read access, and as a result, the initial output of the RP6 becomes "000h". There is. Next, it is activated by the selection signal 19 when reading data from the memory unit 4, and the output is sequentially counted up by the read signal 20. Therefore, by the read access of the read side control unit 3, the data held in the memory unit 4 is output to the data bus 21 in ascending order from the lower address.
After counting up to the maximum value "FFFh", RP6 circulates at the next update clock, and its output is "00" again.
0h ", and again the retained data is circulated to the memory unit 4 in ascending order from the lower address and output. Therefore, if the number of times of reading data from the memory unit 4 of the read side control unit 3 is y, the output of RP6 is Y −4096 · yy: Number of rotations of RP, x−1 ≦ y ≦
The value of x is shown.

Therefore, in the comparator 11 of the full state detecting section 7,
(X + 1-4096 · x) of the value obtained by adding (10) to (X−4096 · x) of the output 22 of WP5 and the value of the output 23 of RP6
(Y-4096 · y), and when a match is detected, the memory unit 4 indicates that the read-wait packet data from the read-side control unit 3 is full, and the full-signal 24 causes the write-side control unit. 2 and the read-side control unit 3 are notified that the data is full.

(2) In the case of the FIFO operation of 1 unit of packet data (the memory unit 4 is not in the full state).

The packet data is composed of a fixed length packet per unit. The write-side control unit 2 receives the selection signal 25 before writing one unit of packet data in the memory unit 4.
5 selects the 12-bit countdown counter 12 shown in FIG. 5 in the countdown counter unit 8 and sets the data length of the packet data as the initial value by the write signal 15 to the 12-bit countdown counter 12 via the data bus 17. By writing, the initial value of the 12-bit countdown counter 12 is set.

When the write-side control unit 2 writes data to the memory unit 4 and becomes an updatable state, the 12-bit countdown counter 12 has the selection signal 14 valid and the write signal 15 written.
The counter output 26 of the 12-bit countdown counter 12 is decremented by (-1). After that, every time the write-side control unit 2 writes data to the memory unit 4, the count value of the 12-bit countdown counter 12 decreases, and when the count value becomes 0, that is, the number of data writes is one packet unit. When the data length matches, the counter output 26 becomes all "L" state,
The trailing edge of the write end signal 27, which is the output of the 12-input OR gate 13, changes, and the write end signal 27 of "L" level is output.

The up-down counter section 9 which receives the write end signal 27 as a clock input outputs the output of the up-down counter section 9 by (+1) at the falling edge of the write end signal 27.
To do. That is, the counter output indicates the number of packet data waiting to be read in the FIFO buffer after the writing of one unit of packet data is completed.

By the write end signal 27, the read side control unit 3
Select signal 28 before read access to the memory section 4.
Select the up / down counter section 9 with, and output the count value with the read signal 20 via the data bus 21, that is, read the number of read-wait packet data in the FIFO buffer, and know that there is read-wait packet data. , And read access to the memory unit 4. After the completion of reading the packet data of one unit, the read-side control unit 3 outputs the read end signal 29 of "L" level. The up / down counter section 9 which receives the read end signal 29 as a clock input outputs (-1) the output of the up / down counter section 9 at the falling edge of the read end signal 29. That is, the counter output is 1
The following shows the number of packets waiting to be read in the FIFO buffer (Table 1 below) after the unit packet data has been read.

[0020]

[Table 1]

The number of packets waiting to be read in the FIFO buffer, which has been counted as described above, is notified to the read-side control unit 3 every time the writing of one unit of packet data into the memory unit 4 is completed, and the read-side control unit 3 is notified. Can immediately perform processing in accordance with the number of read wait packet data in the FIFO buffer.

[0022]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the IFO buffer circuit 1, when the read-side control unit 3 reads the packet data from the FIFO buffer, the software of the read-side control unit 3 can detect one unit of packet data, and the reading of one unit of packet data is completed. By counting the signal and the writing end signal of one unit of packet data by the countdown counter unit 8,
It was possible to notify the read side control unit 3 of the number of read wait packet data in the memory.

However, in the case of performing communication by packet data having a long packet data length or using a large capacity FIFO buffer, the write side control unit 2 and the write side control unit 2 are used.
In the case of performing data communication between the read-side control units 3 whose operating speed is considerably slower than, the read-side control unit 3 cannot increase the execution speed due to the load of detecting one unit of packet data. There is a problem that the efficiency of data communication cannot be improved.

The present invention is to solve the above-mentioned problem, and when the read side control unit 3 reads the read-wait packet data in the FIFO buffer, the detection of the write end signal of one unit of packet data is realized by hardware. By
FIF capable of reducing the load on the read side control unit 3
It is intended to provide an O buffer circuit.

[0025]

According to the present invention, there is provided a memory section for storing data of a FIFO buffer between an input side and an output side which operate asynchronously, and an address for writing and reading data to and from the memory section. The write and read pointers to be generated, the full state detection unit that detects the free space of the memory unit from the address of the read pointer, and the data length of one unit of packet data is preset to the count value, and the memory unit 4 Each time data is written, the count value is decremented and updated, and when the count value becomes 0, the first countdown counter section that notifies the end of counting and the first countdown counter section are set. A count value of the data length of 1 unit of packet data is set, and each time the data is read from the memory unit, the count value is added or subtracted to be updated so that the count value is 0. Then, a second countdown counter section is added to the first-in first-out buffer circuit having an up / down counter section for notifying the end of counting, and the second countdown counter section has a count value of the data length of one unit of packet data. Every time the data is read from the memory unit, the count value of the second countdown counter unit is subtracted and updated, and when the count value becomes 0, a count end notification is output and the notification is given. The number of data waiting to be read is obtained from the count value of the first countdown counter unit when the data is received, and the number of data waiting to be read in the memory unit is notified to the output side.

[0026]

According to the present invention, before the writing of the packet data from the write-side control unit to the memory unit, the data length of the packet data to be written into the memory unit can be counted so that the depth of the memory unit can be counted. Up / down that can be set in the counter unit and can read the data length of the packet data read from the memory unit when reading the packet data from the memory unit to the read-side control unit. The second countdown counter sets the number of packet data of 1 unit detected by the first countdown counter unit and the number of packet data of 1 unit detected by the up / down counter unit. By counting, the number of packets waiting to be read in the FIFO buffer can be counted, and at the end of writing one unit of packet data Immediately, the number of the read waiting packet data FIFO buffer and to notify to the lead-side control unit.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 30 is a FIFO buffer circuit, 8 in this FIFO circuit 30 is a first countdown counter section (same configuration as in FIG. 5), 31 is a newly added second countdown counter section. is there. In addition, the same blocks as those in FIG. 3 are denoted by the same reference numerals. FIG. 2 is a block diagram showing the configuration of the second countdown counter section 31 of FIG. In FIG. 2, 33 is a 12-bit countdown counter and 36 is a 12-input OR gate.

(1) When the memory unit 4 is full.

The WP5, RP6 and full state detecting section 7 operate in the same manner as in the conventional example described above, and the write side control section 2 and the read side control section 3 indicate that the memory section 4 is in the full state. Notify that with a full signal 24.

(2) In the case of FIFO operation of 1 unit of packet data using the FIFO buffer circuit of the present invention As in the conventional example, the write side control unit 2 selects before writing 1 unit of packet data to the memory unit 4. The signal 25 selects the 12-bit countdown counter 12 shown in FIG. 5 in the first countdown counter unit 8, and the write signal 15 sets the data length of the packet data as an initial value via the data bus 17. .

The 12-bit countdown counter 12 is in an updatable state when the selection signal 14 is valid, that is, when the write-side control unit 2 writes data in the memory unit 4, and counts with the write signal 15 as a trigger. The output 26 of the container is set to (-1).

12-bit countdown counter shown in FIG.
When the count value of 12 becomes 0, that is, the number of times of writing data from the write-side control unit 2 to the memory unit 4 becomes the same as the number set as an initial value in the 12-bit countdown counter 12 before writing data. If so, the counter output 26 becomes all "L" state, the trailing edge of the write end signal 27 which is the output of the 12-input OR gate 13 changes, and the "L" level write end signal 27 is output. The up / down counter section 9 which receives the write end signal 27 as a clock input outputs (+1) the output of the up / down counter section 9 at the falling edge of the write end signal 27. That is, the counter output is
It shows the number of packet data waiting to be read in the FIFO buffer after the writing of one unit of packet data is completed.

In response to the write end signal 27, the read side control section 3 sends the selection signal before the read access to the memory section 4.
The up / down counter section 9 is selected by 28, and the count value is output by the read signal 20 via the data bus 21, that is, the FIFO.
The number of read waiting packet data in the buffer can be read and it can be known that there is read waiting packet data, and the read access to the memory unit 4 is performed.

When reading one unit of packet data from the memory unit 4, the read-side control unit 3 first reads only the packet data length in the header of the packet data, and uses the selection signal 32 as a second countdown counter. The 12-bit countdown counter 33 shown in FIG. 2 in the unit 31 is selected, and the data length of the packet data is set as an initial value by the write signal 34 via the data bus 21.

The 12-bit countdown counter section 33 shown in FIG. 2 is in the updatable state when the selection signal 19 is valid, that is, when the read side control section 3 reads data from the memory section 4, and the read signal is read. The counter output 35 is made (-1) by using the signal 20 as a trigger. When the count value of the countdown counter 33 shown in FIG. 2 becomes 0, that is, the number of times data is read from the memory unit 4 to the read-side control unit 3 is the number set as an initial value in the countdown counter 33 before data reading. When it becomes the same as, the counter output 33 is all "L".
As a result, the trailing edge of the read end signal 29, which is the output of the 12-input OR gate 36, changes and the read end signal 29 of "L" level is immediately output.

The read end signal 29 enables the read side control unit 3 to detect the end of the reading of one unit of packet data. In addition, the up / down counter unit 9 that uses the read end signal 29 as a clock input
At the falling edge of 29, the output of the up / down counter section 9 is decremented by (-1). That is, the counter output of the up / down counter section 9 is F after the completion of reading one unit of packet data.
Indicates the number of read wait packet data in the IFO buffer.

The number of packets waiting to be read in the FIFO buffer, which has been counted as described above, is notified to the read side control unit 3 every time one unit of packet data writing to the memory unit 4 is completed, and the read side control unit 3 According to the number of packet data waiting to be read in the FIFO buffer, the processing can be performed immediately.

The second countdown counter unit 31 added as described above detects one unit of packet data when the read side control unit 3 reads one unit of packet data from the memory unit 4, that is, It is possible to immediately notify the up / down counter unit 9 of the completion of the reading of one unit of packet data, and particularly between the write side control unit 2 and the read side control unit 3 which operates much slower than the write side control unit 2 between the processors. When performing the data communication of the read side control unit 3 itself,
Since it is not necessary to detect the end of reading of the unit packet data, the load on the read side control unit 3 is reduced, the operation of the read side control unit 3 can be speeded up accordingly, and the communication efficiency can be greatly improved.

In this embodiment, the dual port RAM is used as the data holding memory. However, even if the single port RAM is used for the time division in the write side control section and the read side control section, It has no effect on the effect of the present invention.

Although the present invention has been described with reference to packet communication data, it goes without saying that it can be applied to a similar system.

[0041]

As described above, the first-in first-out buffer circuit of the present invention has been realized so far by the software of the read side control unit when transmitting packet data.
Since the unit packet data is detected by hardware, the read side control unit does not need to detect one unit of packet data, the load on the read side control unit can be reduced accordingly, and the operation of the read side control unit can be reduced. Can be accelerated. Therefore, even when data communication is performed between the write-side control unit and the read-side control unit whose operation speed is considerably slower than that of the write-side control unit using the large capacity FIFO buffer, the communication arrival efficiency is good.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second countdown counter section of FIG.

FIG. 3 is a block diagram showing a configuration of an example of a conventional FIFO buffer circuit.

4 is a block diagram showing an internal configuration of a full state detection unit 7 of FIG.

5 is a block diagram showing an internal configuration of a countdown counter section 8 of FIG.

[Explanation of symbols]

1, 30 ... FIFO buffer circuit, 2 ... Write side control unit, 3 ... Read side control unit, 4 ... Dual port memory unit (memory unit), 5 ... Write pointer (WP), 6 ... Read pointer (RP), 7 ... Full state detection section, 8 ... First countdown counter section, 9 ... Up-down counter section, 10 ... Adder, 11 ... Comparator, 12, 33 ... 12-bit countdown counter, 13, 36 ... 12 inputs OR gate, 31 ... Second countdown counter section.

Claims (1)

[Claims] 1. A memory unit for storing data of a first-in first-out buffer between an input side and an output side which operate asynchronously,
A write and read pointer that generates each address for writing and reading to and from the memory unit, a full state detection unit that detects the free space of the memory unit from the address of the read pointer, and a data length of one unit of packet data A first countdown counter section that presets a count value, subtracts and updates the count value each time data is written to the memory section, and notifies the end of counting when the count value becomes 0; A count value of the data length of one unit of packet data set in the first countdown counter unit is set, and each time the data is read from the memory unit, the count value is added or subtracted to be updated to update the count value. A second countdown counter section is added to a first-in first-out buffer circuit having an up-down counter section for notifying the end of counting when the value becomes 0, and a second counter is added. A count value of the data length of one unit of packet data is set in the down count counter unit, and each time the data is read from the memory unit, the count value of the second count down counter unit is subtracted and updated. The count value is 0
Then, a count end notification is output, the number of data waiting to be read is obtained from the count value of the first countdown counter section when the notification is received, and the number of data waiting to be read from the memory section is output. A first-in first-out buffer circuit for notifying a user.