JPH08179998A - Multi-stage hardware timer - Google Patents

Abstract

PURPOSE: To provide a multi-stage hardware timer in which a timer is realized with a RAM and its control circuit and a circuit scale can be reduced in the case that many hardware timers are required to measure a time at each of many events generating independently. CONSTITUTION: This hardware timer is equipped with a RAM 21 provided at every event and in which a count value is stored, and a counter control part 20 which performs count-up control while the value of the RAM 21 is read and written in time division. Also, an adder 23, an address counter and an overflow flag 24, etc., for read data from the RAM 21 are provided in the counter control part 20. Therefore, load is applied to software processing in a software timer, however, in this case, since the timer is realized with hardware, the load on the software processing can be reduced, and also, the circuit scale can be reduced by constituting the multistage timer only of the RAM and its counter control part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage hardware timer used in a system which requires a large number of timers for each event for a plurality of independently occurring events.

[0002]

2. Description of the Related Art Conventionally, when a timer is required for each event for a plurality of independently occurring events, a method in which each timer is realized and processed by software, and a counter is provided for each event by hardware, There were two methods of realizing a hardware timer.

[0003]

However, when the number of independently generated events increases, the software timer method requires heavy software processing for timer control, resulting in a decrease in the processing capacity of the entire system. There was a problem of doing. Also, in the method of individually providing a hardware timer, if the number of counters increases,
There has been a problem that the circuit scale becomes large and a physical mounting space problem occurs, or a cost increases accordingly.

Therefore, an object of the present invention is to provide a multi-stage hardware timer capable of reducing the circuit scale when a large number of hardware timers are required to measure the time for each of a large number of independently occurring events. And

[0005]

To this end, the present invention stores a plurality of counter values for realizing each timer in a system which requires a timer for each event for a plurality of independently occurring events. Memory, memory address counter, adder that adds 1 to the count value read from this memory, comparator that determines whether or not this count result indicates an overflow, which is a timeout, externally indicates that this overflow has occurred. It has a counter control unit consisting of an overflow flag for notifying the user and an access timing generation circuit for the memory, and sets an arbitrary counter load value that determines the timeout time until the overflow to an arbitrary memory address counter. The memory can be stored by providing the setting means. It is obtained so as to achieve the amount content independent timers.

[0006]

With the above structure, a large number of timers can be centralized in a memory and a counter control unit to reduce the physical mounting space. In addition, all hardware control can reduce the load of software processing. It becomes possible to reduce.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing an example of a LAN frame exchange system using a multi-stage hardware timer according to an embodiment of the present invention,
FIG. 2 is a detailed block diagram of the multistage hardware timer. In the figure, 1 is a high-speed bus inside the system, to which a transmission buffer memory 2 is connected via a frame exchange control unit 3. The CPU 4 controls the transceiver 5, the multi-stage hard timer 6, etc. through the CPU bus 8. There are many transceivers 5, which are connected to the LAN terminal 7, respectively.

In the above configuration, in FIG. 1, the LAN frame received from the high speed bus 1 inside the system is
The data is temporarily stored in the transmission buffer memory 2 having a capacity of 256 frames, and at this time, the frame exchange control unit 3 stores the port number to be transmitted judged from the destination address of the frame and the address written in the transmission buffer memory 2. Notify the CPU 4. The CPU 4 makes a frame transmission request to the transceiver 5 of the port to be transmitted, and activates the timer of the multi-stage hard timer 6 corresponding to the address written in the transmission buffer memory 2 obtained from the frame exchange control unit 3. When the transmission of the transceiver 5 to the LAN terminal 7 is completed normally, the CPU 4 resets the started timer and releases the used transmission buffer memory 2 to the frame exchange control unit 3. If the transmission to the LAN terminal 7 is not completed due to a failure or the like, a timeout (overflow) occurs in the multistage hardware timer 6. The CPU 4 executes a failure process for this time-out, and releases the used transmission buffer memory 2 to the frame exchange control unit 3.

FIG. 2 is a detailed block diagram of a multi-stage hardware timer which realizes the 256 8-bit timers used in the embodiment of FIG. The multi-stage hardware timer of this embodiment is a RAM 2 that stores the count values of all timers.
While reading and writing 1 and the value in the RAM 21 in a time division manner,
It is divided into two, a counter control unit 20 that performs count-up control. The counter control unit 20 is an external circuit or a CPU.
It is connected to 19th grade. The counter control unit 20 uses the RA
It has a comparator 22 for judging whether the value read from M21 should be counted up or whether an overflow has occurred, and if the value to be counted up (for example, read value = 1 to 255) is added. The adder 23 adds 1 and the addition result is again written to the same address in the RAM 21, and if an overflow occurs (read value = 255), the adder 23 adds 1 to the RAM 0
Overflow flag 2 corresponding to the value (= RAM address) of the address counter when reading while writing to
Set 4 to notify the outside that a timeout has occurred.

Write (load) values to RAM 21
In this case, first, the RAM address to be written from the outside is written in the load address register 25, the value to be written is set in the load data register 26, and the writing is started,
At the determined external RAM write timing,
Load address register 2 by selectors 27 and 28
5 and the load data register 26 are selected, the RAM 21
Is written to.

In the figure, 29 is a register, which is a RAM 21.
The data read from is temporarily retained. A data output buffer 30 is for writing to the RAM 21. Further, 31 is a data input buffer, RAM
It is for inputting the data read from 21. A timing generation unit 32 generates a read / write timing signal for the RAM 21. Further, 33 is an address counter, which increments the address value for the RAM 21 each time the reading and writing are completed.

[0012]

As described above, according to the present invention, the load on a large number of timer processes by conventional software is eliminated, and for example, in the case of the above embodiment, the CPU concentrates on LAN frame handling and other fault processing. This makes it possible to improve the processing capacity. Further, if it is attempted to realize a timer by a conventional individual hardware counter, it is not realistic to provide a large number of counters due to the problem of physical mounting space, but only one memory and a counter control unit are required. The problem can be solved by reducing the scale.

[Brief description of drawings]

FIG. 1 is an example diagram of a LAN frame switching system using a multi-stage hardware timer according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a multi-stage hardware timer according to an embodiment of the present invention.

[Explanation of symbols]

 20 Counter Control Unit 21 RAM 23 +1 Adder 24 Overflow Flag 25 Load Address Register 26 Load Data Register 27, 28 Selector

Claims (1)

[Claims] 1. In a system which requires a timer for each event for a plurality of independently occurring events, a memory for storing a plurality of counter values for realizing each timer, a memory address counter, and a read from this memory. An adder for adding 1 to the count value, a comparator for determining whether or not the count result indicates an overflow that is a timeout, an overflow flag for notifying the outside that this overflow has occurred, the memory By having a counter control unit composed of an access timing generation circuit for, and setting means for setting an arbitrary counter load value for determining a timeout time until overflow to an arbitrary memory address counter, Independent timer for the capacity that the memory can store Multi-stage hardware timer which is characterized in that current.