JPH04205044A - Buffer circuit - Google Patents

Abstract

PURPOSE:To obtain a buffer circuit using a small amount of hardware by storing data to be transferred onto a predetermined bus together with addresses added to the data and data lengths in a buffer circuit, and by using a processing means to identify the data in order of storage in unit of the stored data length by the stored address. CONSTITUTION:Data from input/output unit 11 is transferred, following the first transfer when the address data length is transferred onto bus 1. To transfer data to the buffer 2, the address data length is stored as it is, followed by storing a data length of data. Likewise, data from other input/output units is transferred sequentially in buffer 2. To fetch data from buffer 2 to process, the 1st word is fetched to read the data length. Next, a data length of data is fetched to discriminate, from the address stored the 1st word from which I/O unit this data was fetched. With this, data is processed differently in accordance with an input/output unit from which data was fetched.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer circuit for storing many types of data in a digital circuit such as a computer.

(Prior Art) In a digital circuit such as a computer, when an input/output device transfers data to a bus, a waiting time occurs to secure the right to use the bus for each input/output device. To prevent data transfer speed from decreasing due to such latency,
It is common to provide a buffer circuit between the input/output device and the bus.

Buffer circuits are also used in various digital circuits to temporarily store data.

Such a buffer circuit may store data that is processed differently depending on the type of data. In such a case, the buffer circuit was configured as follows.

FIG. 2 is a diagram showing the configuration of a conventional buffer circuit.

The illustrated circuit includes a plurality of buffers 2 connected to a bus 10.
It consists of 1 to 25.

The buffers 21 to 25 are composed of RAM (random access memory) and the like, and each buffer has a different type of data D1 to D1.
Store D5. That is, as many buffers as there are types of data are prepared. That is, in FIG. 2, Dl,
Assume that five types of data D2, D3, D4, and D5 are transferred on the bus. In order to store these data, data Dl was stored in the buffer 21 and data D2 was stored in the buffer 22.

Further, the processing means 3o distributes the data D1 to D5 to the respective buffers 21 to 25. For this reason, the processing means 30
used addresses to identify each piece of data. When each piece of data is stored in a corresponding buffer, the address, data length, etc. added to the data are removed.

The processing means 30 performs processing for each type of data by processing the data stored in each of the buffers 21 to 25.

FIG. 3 is a diagram showing the configuration of a conventional input/output buffer circuit.

In the illustrated circuit, input/output devices 31 to 35 are connected to the bus 10.

In the processing means 3o, buffers 21 to 35 are used to sequentially process data output from each input/output device 31 to 35.
25 is used. The input/output device 31 is stored in the buffer 21, the input/output device 32 is stored in the sofa 22, and so on.
An address has been assigned so that it will be stored in . Since the buffers 21 to 25 are used in this manner, each buffer has the same structure and capacity.

In other words, there are as many sofas 2 as there are input/output devices 31 to 35.
1 to 25 are required.

(Problems to be Solved by the Invention) However, the above-described conventional technology has the following problems.

That is, as shown in FIG. 3, when there is a large difference in the amount of data transferred between the input/output devices 31 to 35, there is a problem in that the buffer is wasted. In other words, if there is a large difference in the amount of data transferred between the input/output devices 31 to 35, or if the input/output device 31 has a high data transfer rate and the input/output device 32 has a low data transfer rate,
The buffer 21 may have a large area for storing data, or the buffer 22 may have a large unused area. For example, in the illustrated example, compared to buffer 21, buffer 22 is not used effectively.

The example shown in Figure 3 is a case where there are five input/output devices, but
In a case where 100 input/output devices are connected, the capacity of the buffer itself becomes 100 times larger. In other words, the capacity required for the buffer increases in proportion to the type of data.

Furthermore, as the types of data increase, the variation in data access frequency also increases, and the useless portion (unused portion) of the buffer also increases.

The present invention has been made with attention to the above points, and when processing many types of data, it reduces the amount of hardware without affecting the data transfer capacity on the buffer, thereby improving efficiency. It is an object of the present invention to provide a buffer circuit that can be used in various ways.

(Means for Solving the Problems) A buffer circuit of the present invention stores data transferred on a predetermined bus together with an address and data length added to the data, and processes the data by processing means connected to the bus. The present invention is characterized in that data is retrieved in accordance with the data length in the order of storage, and the type of the retrieved data is identified by the address.

(Operation) In the buffer circuit of the present invention, a plurality of types of data are transferred on the same bus. When the processing means sequentially processes these data, the plurality of types of data are stored in a common buffer. In this case, the address and data length are also stored in the buffer together with the data. Then, the processing means retrieves the data by the data length in the order of storage, determines the type of data based on the address, and processes the data. Therefore, the buffer circuit can be realized with a small amount of hardware.

(Example) FIG. 1 is a diagram showing the configuration of a buffer circuit of the present invention.

The illustrated circuit consists of a single buffer 2 connected to a bus 1.

The buffer 2 consists of RAM (random access memory) and the like, and has a FIFO structure. This buffer 2 stores the data transferred on the bus 1 together with the address and data length added to the data.

On the other hand, the bus 1 includes a processing means 3 and input/output devices 11 to 1.
5 is connected.

The processing means 3 consists of a CPU and the like. This processing means 3 is
Retrieve data by data length in the order of storage. Then, the processing means 3 identifies the type of retrieved data using the address.

The input/output devices 11 to 15 are composed of magnetic disk devices, magnetic tape devices, and the like.

Next, the operation of the circuit described above will be explained.

For example, when data is transferred from the input/output device 11, an address and a data length are transferred onto the bus 1 as a first transfer, as shown in FIG. Next, data is transferred after the second transfer.

When data transferred from bus 1 is stored in buffer 2, as shown in the figure, the address and data length are stored in the buffer as they are, and then data corresponding to the data length is stored.

Next, when data is transferred from the input/output device 12,
Similarly, data is stored in buffer 2. Therefore, as shown in the figure, data from various input/output devices is stored in the buffer 2 in the order in which it is received.

Furthermore, when data is taken out from the buffer 2 and processed, the first word is taken out and the data length is read. Next, data is extracted for the data length. Next, it is determined from which input/output device the data comes from from the address stored in the l-th word. This makes it possible to perform different processing depending on the input/output device.

In the above embodiment, an input/output device such as a magnetic disk was used as an example of the device connected to the bus 1, but the present invention is not limited to this, and the main storage device etc. can be connected to the CPU via the bus. It can also be applied to cases where a buffer is interposed. Furthermore, although the buffer 2 has a single configuration, it may be divided into a plurality of parts as long as it can be used commonly by each device.

Further, the processing means 3 is not limited to the CPU, but may be a DMA (direct memory access) or the like provided separately from the CPU.

(Effects of the Invention) As explained above, according to the buffer circuit of the present invention,
Since a FIFO-structured buffer is provided and the data format is such that the address and data length are added to the beginning of the transferred data, multiple types of data can be stored in one resource. Furthermore, as a result, the amount of hardware can be significantly reduced, whereas in the past, buffers were prepared as many as the number of types of processing, and the amount of hardware for the buffers increased for the entire circuit.

Furthermore, it is possible to reduce wasted areas in each buffer. Therefore, the buffer can be used effectively.

As a result of the above, the capacity of the buffer can be determined only by the throughput determined by the difference between data input to the processing means and data processed and output by the processing means.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a buffer circuit of the present invention, FIG. 2 is a diagram showing the configuration of a conventional buffer circuit, and FIG. 3 is a diagram showing the configuration of a conventional buffer circuit for an input/output device. 1... Bus, 2... Buffer, 3... Processing means,
11.12.13.14.15... Input/output device. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] Storing data to be transferred on a predetermined bus together with an address added to the data and a data length, and extracting data in units of the data length in the order of storage by a processing means connected to the bus, A buffer circuit characterized in that the type of the retrieved data is identified by the address.