JPH04306755A - Fifo buffer device - Google Patents

Abstract

PURPOSE:To supply a FIFO buffer device which communicates the write termination of significant data to a read-side control part so as to improve communication efficiency even in a state where a buffer does not become full on the FIFO buffer device laid between a write-side which asynchronously operates and the control part of a read-side. CONSTITUTION:Registers 215 and 216 where a data protocol adding data which is hand to occur in significant data is extracted after the termination of significant data from a write control part 201 and additional data is set are provided. Comparators 217 and 218 compare intra-register data with transmission data. The write termination of a significant data string is informed to the read-side control part 202 by the detection of coincidence.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO buffer device for communicating data between multiprocessors operating asynchronously.

0002

[Prior Art] Figure 2 shows a conventional FIFO (first-in, first-out)
An example of the configuration of a buffer device (First In First Out) is shown below. In FIG. 2, 100 is a FIFO buffer device, and 101 and 102 are a write-side control section that writes data to the FIFO buffer device 100, and a read-side control section that reads data, which are each composed of a microprocessor or the like. The FIFO buffer device 100 has a write side and a read side separately, and is capable of asynchronous read access and write access, and has a dual port memory section (hereinafter referred to as a memory section) 110 for specifying a write address to the memory section 110. write pointer (hereinafter referred to as WP) 111, and read pointer (hereinafter referred to as RP) 11 that specifies the read address.
2, an adder 113, and a comparator 114.

In the following, for ease of understanding, it is assumed that the write-side control section 101 and the read-side control section 102 handle 8-bit width data, and the maximum number of data stored in the memory section 110 (hereinafter referred to as depth) is assumed to handle 8-bit width data. ) is 4096 words. Therefore, the address width of the memory unit 110 output by the WP 111 and the RP 112 is 12 bits.

[0004] The WP 111 is activated by a selection signal 128 when writing data from the write-side control unit 101 to the memory unit 110, and by a write signal 122, the initial output is set to "000h (hexadecimal number, the same applies hereinafter)" and is sequentially counted. It is composed of a ring-type up counter that is incremented, and its output is used as an address for holding data from the write-side control unit 101 in the memory unit 110. Therefore, write data from the write-side control unit 101 via the data bus 120 is held in the memory unit 110 in ascending order from the lower address. In addition, WP1
11 is reset by the write-side control unit 101 before the first write access to the memory unit 110, and its output is “000h”. WP111 is the maximum value "F
After counting up to "FFh", the output becomes "000h" again at the next update clock and rotates. Therefore, in this conventional example where the depth of the memory section 110 is 4096 words, the output of the WP 111 is on the write side. Indicates the value of the data write count M-4096m (m: the number of rotations of WP, that is, the number of times from 000h to FFFh to 000h) of the control unit 101.
The read-side control section 102 is activated by a selection signal 129 when reading data from the memory section 110, and is sequentially counted up with the initial output set to "000h" by a read signal 123. The output is used as an address by which the read-side control unit 102 reads the data held in the memory unit 110, and the read access by the read-side control unit 102 causes the data held in the memory unit 110 to be read.
The data is output to the data bus 121 in ascending order starting from the lower address. Note that, like the WP 111, the RP 112 is reset by the read-side control unit 102 before the first read access to the memory unit 110, and its output is "000h". After the RP 112 counts up to the maximum value "FFFh", when the next update clock comes, its output becomes "000h" again. Therefore, RP11
The output No. 2 indicates the value of the number of times N-4096n (n: number of rotations of RP, m-1≦n≦m) of data reading from the memory section 110 of the read-side control section 102.

[0005] Therefore, the output 124 (M
-4096 m) and RP112 output 125 (N-409
6n) is added (+1) by the adder 113 to (N-1-409
6n) by the comparator 114, and if a match is detected, the memory unit 110 is in a full state with valid data waiting to be read from the read-side control unit 102, and the read-side control unit 102 is notified.

[0006]

[Problem to be solved by the invention] The conventional F as described above
In the IFO buffer device, it was possible to know the full state of the FIFO buffer device. However, as the capacity of FIFO buffers has increased as semiconductor technology has improved, the amount of data required to reach a full state has also increased. For this reason, the immediacy of data communication has come to be impaired if reading is waited until the FIFO buffer becomes full. Therefore, there has been a need for a method of notifying the read-side processor immediately after writing of significant data is completed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a FIFO buffer device with good communication efficiency, which notifies a processor on the reading side of the completion of writing of significant data immediately after the completion of writing.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides one or more registers that can set a plurality of data that are difficult to occur continuously in write data from a write side control section, and A configuration that compares the setting contents of each register with the data written to the memory section from the write-side control section, and if a match is detected consecutively with the contents of each register, the read-side control section is notified of this fact. has.

[0009]

With the above-described structure, the present invention allows the read-side control section to know immediately after the writing of valid data from the write-side control section is completed, even before the large-capacity FIFO buffer becomes full.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a FIFO buffer device according to an embodiment of the present invention. 200 in Figure 1 is FIF
In the O buffer device, 201 is a write-side control section, and 202 is a read-side control section. The write-side control section 201 and the read-side control section 202 are constituted by a microprocessor or the like, similar to the conventional example described above. The FIFO buffer device 200 includes a memory section 210, a WP 211, and an RP similar to the conventional example.
212 , an adder 213 , and a comparator 214 , it also includes a first register 215 , a first comparator 217 , a second register 216 , and a second comparator 218 .

[0011] WP211, RP212, adder 213,
The comparator 214 is configured similarly to the conventional example, and the memory section 210
When it becomes full, the read-side control unit 202 is notified of this using a full signal 232.

The write-side control section 201 also selects the first register 21 by selection signals 230 and 231.
5, and a memory section 210 in the second register 216
Set arbitrary data that is difficult to occur consecutively in a significant data string to be written to the memory section 21 from the write-side control section 201.
The data written to 0 and the value set in the first register 215 are compared in the first comparator 217, and when the comparison results match, the comparison output is a match until the next write data occurs. Signal 233 remains valid. Match signal 2
33 activates the second comparator 218 in its valid state, and compares the data set in the second register 216 with the data from the write-side control unit 201 immediately after the data set in the first comparator 217. When the write data is compared with the second comparator 218 and a match between both data is detected,
The result is notified to the read-side control unit 202 using a match signal 234 that serves as a notification signal of completion of writing valid data. The write-side control unit 201 stores the significant data string in the memory unit 210.
A data string protocol is adopted in which the value set in the first register 215 is written immediately after writing to the first register 215 is completed, and the data set in the second register 216 is written immediately thereafter.

As described above, according to the FIFO buffer device of the embodiment of the present invention, the read-side control unit 202 does not have to wait until the memory unit 210 is filled with significant data, and the write-side control unit Data string memory section 2
Immediately after the writing to the processor 10 is completed, it is possible to know that the writing of one significant data string has ended, and the communication efficiency between the processors of the write-side control unit 201 and the read-side control unit 202 can be improved.

Note that there may be cases where the same data as the data set in the registers 215 and 216 occurs continuously in the significant write data of the write control unit 201.
Data transparency can be maintained by the read-side control unit 202 determining whether the data is in a significant data string or write end notification data.

Furthermore, in this embodiment, a comparison setting register,
Further, although the comparators are configured in two sets, the number is not limited, and as the number increases, the reliability of the coincidence signal as a writing completion notification improves. Further, although a dual-port RAM is used as the data retention memory, even if a single-port RAM is used time-sharingly between the write-side control section and the read-side control section, the effects of the present invention will not be affected in any way. I won't give it.

[0016]

As is clear from the above embodiments, according to the present invention, the read-side control section can finish writing the significant data string of the write-side control section without waiting for the memory section to become full. Immediately after, it is possible to know whether a significant data string can be read, and even if data communication of a short data string is performed using a large-capacity FIFO buffer, it is possible to use a FIFO with high communication reach efficiency.
O buffer device can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a FIFO buffer device according to an embodiment of the present invention.

[Figure 2] Block diagram showing the configuration of a conventional FIFO buffer device

[Explanation of symbols]

210 Dual port RAM 215 Register 216 Register 217 Comparator 218 Comparator

Claims (1)

[Claims] 1. A memory means for temporarily holding data sent from a writing side processor to a reading side processor, one or more register means holding setting data, data to be written from the writing side processor to the memory means, and a memory means for temporarily holding data sent from the writing side processor to the reading side processor. A FIFO buffer device comprising comparison means for comparing the setting data held in a register means, and notifying the reading processor of a match in the comparison result.