JPH05151146A - Dma transfer system - Google Patents

Abstract

PURPOSE:To attain the DMA transfer of all data on plural blocks turned into a chain just with a single start operation of a CPU. CONSTITUTION:The chain presence/absence identification bits fetched from each block of a buffer are stored in a chain bit storing register 5. When the presence of a chain is confirmed, the address of the next block is stored in a next-block address register 7. The contents of a data length register 9 showing the data byte length and stored in a data storing part are stored in a word counter register 5 when the chain is present, and the contents of an LI register 10 showing the valid byte length stored in the data storing part are stored in the register 5 respectively in accordance with the contents of the register 3. Then the contents of the register 5 are subtracted in response to the transfer of data. When the contents of the register 5 are equal to 0 and the presence of a chain is confirmed, the transferer is switched to the next block based on the contents of the register 7. Meanwhile the transfer of data is complete when the absence of the chain is confirmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for direct memory access transfer of a plurality of chained blocks of data.

[0002]

2. Description of the Related Art Conventionally, as a DMA controller for performing direct memory access (hereinafter, referred to as DMA) transfer, for example, "Transistor Technology", October 1988, P. 468-P. 478, published by CQ Publisher, Inc. FIG. 7 is a block diagram showing the structure of the DMA transfer system, and 51 is the DMA disclosed in the above document.
Controller, 52 is a CPU that controls the entire system
(Central processing unit), 53 is a plurality of blocks (# 0 to #n)
Is a chainable buffer, 54 is a main memory, and 55 is a bus connecting 51 to 54.

In order to transfer data from the buffer 53 to the main memory 54 in the configuration as shown in FIG. 7, the transfer destination address is set in the memory address register (not shown) of the DMA controller 51 and the device address register ( The transfer source address is set in (not shown), and the number of transfer words is set in the memory transfer counter (not shown). Then, the channel control from the CPU 52
A DMA transfer is started by setting the STR bit of a register (not shown).

To transfer a plurality of blocks of data, the above procedure is repeated for the number of transfer blocks. As a method of transferring data of a plurality of blocks at a time, there is a method of setting the start address of the buffer 53 on the main memory 54 and setting the transfer destination address in the device address register to start the DMA transfer. is there.

[0005]

However, in the above-mentioned conventional DMA controller, when transferring data from a plurality of chained blocks, the DMA controller must be activated for each block, which imposes a burden on the CPU. There was a problem that it would grow. In addition, even when using the mode of transferring data of multiple blocks at one time, the start address of each block must be set in the main memory, so if the CPU does not participate in chaining, the CPU follows the chain and buffers. However, there is a problem in that the load on the CPU becomes heavy.

In order to solve the problem that the load of the CPU becomes large when data is transferred from a plurality of chained blocks as described above, the present invention determines the presence or absence of a chain during data transfer, and All the data of the chained blocks can be transferred just by activating it from the CPU once by providing a means to trace it in hardware.
An object is to provide an MA transfer method.

[0007]

In order to solve the above problems, the present invention determines whether or not there is a chain in a DMA transfer system in which data in a buffer divided into a plurality of blocks of fixed length is transferred by a DMA controller. The presence / absence of a chain is provided by providing each bit with an indicated bit, an area showing the address of the next block when there is a chain, an area showing the effective byte length in the data storage section when there is no chain, and a storage section for transfer data in each block. For storing the data indicating the number, the second storage means for storing the address of the next block when there is a chain, and the data byte length in the data storage section when there is a chain, In the case of, the third storage means for storing the effective byte length in the data storage unit and for subtracting the stored content in accordance with the transfer of the data is a DMA controller. If the chain is present, the transfer source address is switched to the next block when the data in the data storage section has been transferred.If the chain is not present, the data is transferred when the effective byte length in the data storage section has been transferred. Configured to terminate.

Further, according to the present invention, in a DMA transfer system in which data in a buffer divided into a plurality of fixed-length blocks is transferred by a DMA controller, a bit indicating the presence or absence of a chain and an address of the next block when the chain is present. Area for indicating the effective byte length in the data storage section when there is no chain, and a storage section for the transfer data in each block, and stores the address of the next block when the chain exists. Means, a second storage means for setting the byte length of the transfer data and subtracting the stored contents according to the transfer of the data, and a counter for counting the number of bytes of the transfer data in the DMA controller,
When the content of the counter reaches the data byte length in the data storage unit, the transfer source address is switched to the next block,
The data transfer is completed when the byte length set in the storage means has been transferred.

[0009]

According to the present invention, since the DMA transfer system is configured as described above, the DMA controller stores the data indicating the presence / absence of the chain fetched from each block of the buffer in the first storage means, If there is a chain, the address of the next block is stored in the second storage means, and if there is a chain, the data byte length in the data storage section is stored in the second storage section. If there is no chain, the effective byte length in the data storage section is stored in the third storage section. The contents of the third storage means are stored and subtracted according to the data transfer. When the content of the third storage means becomes 0, if the chain is present, the transfer source address is switched to the next block based on the content of the second storage means, and if the chain is not present, the data transfer is completed. To do.

Further, according to the present invention, the DMA controller assigns the address of the next block to the first address when the chain is present.
The storage means stores the byte length of the transfer data in the second storage means, subtracts the set value according to the data transfer, and increases the content of the counter according to the data transfer. Then, when the content of the counter reaches the data byte length in the data storage unit, the transfer source address is switched to the next block, and when the content of the second storage means becomes 0, the data transfer ends.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. (First Embodiment) FIG. 1 shows a DM according to the first embodiment of the present invention.
In the block diagram showing the configuration of the A controller, 1 is an input / output interface section for inputting / outputting various control signals such as address signals, data signals, and reading, 2 is timing creation, address increment, word counter decrement, etc. A control unit for controlling the entire DMA controller, 3 is a chain bit storage register that latches and holds a chain presence / absence identification bit during data transfer, and 4 is a CP
The transfer destination address register, which is set by the I / O instruction from U and is incremented for each data transfer, is the data byte length of the data storage section in the buffer when there is a chain, and in the buffer when there is no chain. This is a word counter register that latches the effective byte length in the data storage unit at the start of data transfer of each block and decrements it every data transfer. Further, 6 is a transfer source address register which is first set by the CPU by an I / O instruction and is incremented for each transfer. When the buffer is chained, the start address of the next block is set every time the block is switched. To latch. 7 is a next block address register that latches the value when the area indicating the address of the next buffer is read when there is a chain, and 8 is a selector that selects the data to be supplied to the word counter register 5 according to the presence or absence of the chain, If there is a chain, change the contents of data length register 9 to
When there is no chain, the content of the LI register 10 is selected.
Reference numeral 9 is a data length register for holding the data byte length in the data storage section in the buffer, 10 is an LI register for holding the effective byte length in the data storage section in the buffer, and 11 is temporarily holding the transfer data during data transfer. It is a data buffer.

FIG. 2 is a block diagram of one block of the buffer according to the embodiment of the present invention. "1" indicates a chain, and "0" indicates a chain.
, A chain presence / absence identification bit CH indicating that there is no chain, LI that is an area that indicates the effective byte length in the data storage unit when there is no chain, and NPN0, NPN1, and 44 bytes that are areas that indicate the number of the next block when there is a chain. A data storage unit, which is an area including minute user data information, is provided, and is composed of 64 bytes.

FIGS. 3, 4 and 5 are operation flowcharts of the DMA transfer system according to the first embodiment of the present invention. Hereinafter, the data transfer operation in the embodiment of the present invention will be described with reference to FIGS. 1 to 5 and 8. In the following description, the DMA controller 51 in FIG. 8 has the configuration shown in FIG. 1 and the buffer 53 has the configuration shown in FIG.

First, in step 21 of FIG. 3, the CPU 52 sets the start address of the chained block of the transfer source in the transfer source address register 6 of the DMA controller 51, and sets the transfer destination in the transfer destination address register 4. Set the address of the main memory 54 of the
Then, transfer start is performed to the DMA controller 51. In step 23, the DMA controller 51 receives the right to use the bus 55 from the CPU 52 every 2 bytes (hereinafter referred to as a bus hunt), and in step 24, the transfer source address of the buffer 53 is set to 2 bytes of data (chain presence / absence identifying bits CH, LI portion). , NPN0), and releases the bus 55 in step 25.

Next, at step 26, the chain presence / absence identifying bit CH is latched in the chain bit storage register 3 and the LI section is latched in the LI register 10, and 2 is added to the content of the transfer source address register 6. Next, in step 27, bus 5
5 is hunted, and in step 28, 2-byte data is fetched from the transfer source address and NPN1 is fetched inside. Then, in step 29, the bus is released.

Next, in step 31 of FIG. 4, the previously fetched NPN0 is set as the upper side and NPN1 is set as the lower side to determine the next block number and set it in the next block address register 7. When the content of the chain bit storage register 3 is “1”, the content of the data length register 9 is latched in the word counter register 5, and when the content of the chain bit storage register 3 is “0”, the content of the LI register 10 is latched in the word counter register 5. To do. Then, in step 32, the transfer source address register 6
Add 6 to the contents of.

In this embodiment, since the buffer of FIG. 2 is placed at addresses 10000000 _H to 101 FFFFF _H , addresses A _{31 to} A ₂₄ are fixed at 10 _H. And, until A ₂₃ ~A ₈ of address NPN0 and NPN1
The next block number calculated by the above is entered and latched in the next block address register 7. In addition, the data storage unit is 44
Since it is a byte, the data length register 9 may be fixed to 44 by hardware, or may be a register that can be set by the CPU 52. Further, since the data storage section starts from the 8th byte from the beginning of the buffer block, 6 is added to the content of the transfer source address register 6.
The addition of 6 may be fixed by hardware, or the CPU 5
The setting may be made from two.

Next, in step 33, the bus 55 is hunted, and in step 34, 2 bytes of data are fetched from the transfer source address of the buffer 53, latched in the data buffer 11, and the content of the transfer source address register 6 is set to 2. Add
In step 35, the bus is released. Next, in step 36, the bus 55 is hunted, and in step 37, the main memory 54
The data of the data buffer 11 is written to the transfer destination address of 1, and 2 is added to the content of the transfer source address register 6, and 1 is subtracted from the content of the word counter register 5,
2 is added to the contents of the transfer destination address register 4, and the bus is released in step 38.

Next, in step 41 of FIG. 5, it is judged whether or not the content of the word counter register 5 is "0", and if it is not "0", the operation of step 33 onward of FIG. 4 is repeated.
If the content of the word counter register 5 is "0", the following operation is performed according to the content of the chain bit storage register 3. That is, the chain bit storage register 3
If the content of "1" is "1", the operation after step 23 of FIG. 3 is performed, and the content of the chain bit storage register 3 is "0".
If so, since the transfer is completed, the CPU 5 at step 43.
Notify 2 that the transfer is completed.

(Second Embodiment) FIG. 6 is a block diagram showing the arrangement of a DMA controller according to the second embodiment of the present invention. Here, the same technical means as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, the chain bit storage register 3, selector 8, data length register 9 and LI register 10 provided in the first embodiment are not provided, but a transfer counter 12 is provided instead. This transfer counter 12
Produces an output when the number of bytes ("44" in this embodiment) in the data storage section in the buffer is counted. Further, in the present embodiment, the word count register 5 stores the number of bytes of transfer data.

The operation of this embodiment is to add a process of setting "0" to the transfer counter 12 in step 21 of FIG. 3 and to add 1 to the content of the transfer counter in step 37 of FIG. If YES in step 41 of FIG. 5, the process proceeds to step 43. If NO in step 41, it is determined whether the content of the transfer counter 12 is “44”. If YES, the content of the transfer counter 12 is set to “0”. Set to "" and proceed to step 23 in FIG.
5 is different from the first embodiment in that the process goes to step 33 of FIG.

In the above embodiments, the data transfer unit is 1 word, 2 bytes, and the data storage unit is 44 bytes. However, it goes without saying that these can be set arbitrarily. Although the bus is hunted and released for each data transfer, it is also possible to hunt the bus and transfer it a plurality of times before releasing the bus. It should be noted that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0023]

As described above in detail, according to the present invention, the next block number of a chained block is fetched and the address of the next block is obtained. When transferring the converted data to the continuous area of the memory, the setting and activation to the DMA controller only needs to be performed once, and the load on the CPU is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DMA controller according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of one block of a buffer in the embodiment of the present invention.

FIG. 3 is a part of an operation flowchart of a DMA transfer system according to the first embodiment of the present invention.

FIG. 4 is a part of an operation flowchart of a DMA transfer system according to the first embodiment of the present invention.

FIG. 5 is a part of an operation flowchart of the DMA transfer system according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a DMA controller according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a DMA transfer system.

[Explanation of symbols]

 1 Input / Output Interface 2 Control Unit 3 Chain Bit Storage Register 4 Transfer Destination Address Register 5 Word Counter Register 6 Transfer Source Address Register 7 Next Block Address Register 8 Selector 9 Data Length Register 10 LI Register 11 Data Buffer 12 Transfer Counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jiro Aso 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A D which transfers data in a buffer divided into a plurality of fixed-length blocks by a DMA controller.
In the MA transfer method, (a) a bit indicating the presence or absence of a chain, (b) an area indicating the address of the next block when the chain is present, and (c) an effective byte length in the data storage section when the chain is absent. An area; and (d) a storage unit for storing transfer data in each of the blocks, and (e) first storage means for storing data indicating the presence or absence of the chain,
(F) second storage means for storing the address of the next block when there is a chain; (g) storing the data byte length in the data storage section when there is a chain; and for the case where there is no chain, the data The DMA controller is provided with a third storage unit for storing the effective byte length in the storage unit and for subtracting the stored contents in accordance with the data transfer. When the chain is present, the data in the data storage unit is transferred. When the transfer is completed, the transfer source address is switched to the next block, and when there is no chain, the transfer is ended when the transfer of the effective byte length in the data storage section is completed.
MA transfer method. 2. A D which transfers data in a buffer divided into a plurality of fixed-length blocks by a DMA controller.
In the MA transfer method, (a) a bit indicating the presence or absence of a chain, (b) an area indicating the address of the next block when the chain is present, and (c) an effective byte length in the data storage section when the chain is absent. An area, (d) a storage unit for transfer data is provided in each of the blocks, (f) first storage means for storing the address of the next block when there is a chain, and (g) a byte length of the transfer data. Is set and the storage content is subtracted according to the data transfer, and (h) a counter for counting the number of bytes of the transfer data is provided in the DMA controller, and the content of the counter is the data. When the data byte length in the storage unit is reached, the transfer source address is switched to the next block, and the second block
The transfer method is characterized in that the transfer is terminated when the byte length set in the storage means is completed.