JPH01295333A - Microcomputer system - Google Patents

Abstract

PURPOSE:To realize a microcomputer system including a memory having a high access time by using an address counter at the memory side and therefore pre-reading the address following a reference address. CONSTITUTION:An address counter 110 increases its contents synchronously with the rise edges t10, t11, t12... of a QWR signal 118 and updates successively the read addresses against a memory 105. While a microcomputer 100 stores successively the instruction codes read onto an AD bus 502 into an instruction queue 104 synchronously with said edges t10, t11, t12.... Thus the supply timing is reduced for the instruction code read address applied to the memory 105 from the microcomputer 100 against the reading actions of the instruction codes set to the continuous addresses. Then the processing speed is improved for a microcomputer system.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a microcomputer system.

[Conventional technology]

In recent years, the instruction processing speed of microcomputers themselves has become extremely fast due to improvements in process technology and architecture. However, when reading instruction codes and referencing data from memory, the time required for reading them is relatively limited compared to the processing speed of the microcomputer itself due to limitations on memory access speed and data transfer speed of the connected bus. This is a major factor that reduces the instruction processing speed of microcomputers.

FIG. 5 shows a conventional example of a conventional microcomputer system.

This microcomputer system includes a microcomputer 500 and a memory 50 for storing programs and data.
1, and these hardware blocks are interconnected via an address data bus 502 (hereinafter referred to as AD bus) in which address information and data information are multiplexed.

Microcomputer 500 includes an instruction execution unit 503 that performs actual instruction processing. Furthermore, the microcomputer 500 outputs an address latch enable signal 504 (hereinafter A
LE) and is connected to an address latch 505 set on the AD bus 02 for extracting address information.

Further, a read signal 506 (hereinafter referred to as RD signal) is outputted from the microcomputer 500 to the memory 501 to specify the read timing of programs and data.

Next, the flow of address information and data on the microcomputer 500 and the AD bus 02 during continuous input of programs placed at consecutive addresses will be explained with reference to the timing chart of FIG.

Normally, programs are stored in consecutive memory areas in sequence, and the microcomputer 500 reads these instruction codes via the AD bus 02 in the order of addresses, and the instruction execution unit 503 performs actual processing. A at this time
As shown in FIG. 6, the bus operation timing of the D bus 02 consists of basic states B1, B2 and B3.

The microcomputer 500 outputs the read address of the instruction code on the AD bus 02 during the period B1, and at the same time outputs the read address of the instruction code on the AD bus 02 during the period ALE 50'4 during the period T1, which is the first half of the period 81.
is considered a high level. The address latch 505 is
The address information on the AD bus 02 is latched in synchronization with the timing of tl when 504 becomes low level.

The microcomputer 500 keeps the RD multiplied signal 06 at an active low level for a period of T2 from 82 to 83. The memory 501 includes an address latch 50
RD signal 50 from the address location specified by
The instruction code is output onto the AD bus 02 in synchronization with 6. The microcomputer 500 takes in the instruction code read onto the AD bus 02 in synchronization with timing t2, and the instruction execution unit 503 executes predetermined instruction processing based on the read instruction code. When reading the next instruction code, the above bus cycle is repeated and the predetermined instruction processing is performed again.

The instruction execution unit 503 changes the address to A at the timing of B1.
The period from when the instruction code is output to the D bus 02 until the instruction code is received at timing t2 is in a state of waiting for the instruction code.

[Problem to be solved by the invention]

In the conventional microcomputer system described above, when reading an instruction code from memory, at least B
l, B2. Since three states of B3 are consumed, the supply of instruction codes to the instruction execution section cannot keep up with the instruction processing in the instruction execution section, and the instruction execution section is often in a state of waiting for an instruction code.

As a result, although the microcomputer itself has sufficient processing power, it has a major drawback in that it does not lead to an improvement in processing speed.

In contrast to the conventional microcomputer system mentioned above,
In the present invention, the memory side has means for holding the read address of the instruction code, and the microcomputer side has means for holding the read-ahead instruction code, and the memory side supplies the write signal of the instruction code to the microcomputer. For reading instruction codes set at consecutive addresses, this invention has an original content of improving the processing speed by reducing the timing of supplying instruction code read addresses from the microcomputer to the memory.

[Means to solve the problem]

The microcomputer system of the present invention comprises a storage means for storing various processing data including instruction codes, and a data processing means for processing data by executing instructions, and the data processing means has a buffer register for storing instruction codes. , the storage means includes a control means for controlling the transfer of the instruction code;
The control means includes an instruction means for storing instruction information instructing the storage contents of the storage means, and the control means sends instruction information instructing a read destination in data transfer performed between the storage means and the data processing means. Subsequently, a control signal is output to the first transfer means that performs one data transfer with the designated storage means, the buffer register and the instruction means, and the buffer register set in the data processing means is On the other hand, the second transfer is to update the instruction means to the next read address at the same time as specifying the writing timing of the instruction code, and to continuously transfer the instruction code between the storage means and the data processing means without sending instruction information. It is characterized by having the means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a first embodiment of a microcomputer system according to the present invention.

The microcomputer shown in FIG. 1 includes a microcomputer 100 that controls data input/output processing, arithmetic processing, and the entire microcomputer system, and a memory chip 101 that has a built-in memory that stores programs executed by the microcomputer and data necessary for them. It is composed of

Furthermore, the microcomputer 100 includes an instruction execution unit 102 that executes instructions, a bus control unit 103 that controls the interface with the outside of the microcomputer, and an instruction buffer 14 for prefetching instruction codes (hereinafter referred to as an instruction queue). There is.

From the instruction execution unit 102 to the bus control unit 103, a data read cycle and a data write cycle (to be described later) with the memory 105 in the memory chip 101 are carried out along with the execution of the instruction.
A bus request signal 106 requesting activation of the following two types of bus cycles (hereinafter referred to as data reference cycles) and an address line 107 for transferring a memory reference address are output, and the bus control unit 103 performs the data reference cycle described above. Upon receiving the activation request, the instruction execution unit 102 outputs a hair reset signal 108. The microcomputer 100 is connected to an AD bus 02 on which address information and data are multiplexed, and refers to data with the memory 105 in the memory chip 101 through the AD bus 02.

The instruction queue 104 is a buffer register that holds instruction codes read in the instruction prefetching process in the order in which they were read.
When the instruction queue becomes full, the queue full signal 120 (
(hereinafter referred to as QFL) is activated.

The memory chip 101 includes a memory 105 that stores programs and processing data of the microcomputer 100;
Memory address data bus 10 via AD bus 02
9 (hereinafter referred to as MAD bus) and further increments the contents, an address latch 111 that only stores address information, and a bus interface section 11.
2, and these units are connected by a MAD bus 109.

Next, a microcomputer 100 and a memory chip 10
Control signals input and output to and from 1 will be explained.

The reset signal 113 is input to the microcomputer 100 to initialize the hardware within the microcomputer.

The microcomputer 100 connects the memory chip 101 to the memory chip 101.
The RD signal 114 for specifying the data output timing onto the AD bus 02, the WR signal 115 for specifying the data write timing on the AD bus 02, and the address information on the MAD bus 109 are sent to the address counter. 110 or address latch 111, and address counter 110 or address latch 1 as the read address source of the memory 105.
A determination signal 116 (
(hereinafter referred to as ID signal) and a timing signal 504 that specifies the latch timing of reference address information on the MAD bus 109 for the address counter 110 or address latch 111, whichever is specified by the ID signal 116.
(hereinafter referred to as the ALE signal) and a transfer permission signal 117 (hereinafter referred to as the TEN signal) that specifies the period during which instruction code transfer is permitted to the memory chip 101 and instructions can be preempted are output. are doing.

Note that the TEN signal 117 is a control signal generated by the control gate 119 when the QFL signal 120 is inactive (the instruction queue is not full) and the acknowledge signal 1
08 is not active, that is, the bus control unit 103 has completed the bus cycle requested by the instruction execution unit 102 to start, and the instruction queue 104 has room to store an instruction code, becomes active. .

Further, the ID signal 116 specifies the address latch 111 when it is at a low level, and specifies the address counter 110 when it is at a high level.

From the memory chip 101 to the microcomputer 100, a transfer timing designation signal 118 (
(hereinafter referred to as QWR signal) is output. Furthermore, QWR11
8, the address counter 110 increments its contents.

Next, a data read cycle, a data write cycle, a branch cycle, and a continuous instruction code read cycle between the microcomputer 100 and the memory chip 101 will be explained in order with reference to FIGS. 2-1 to 2-4.

- Data read cycle The data read cycle of the microcomputer 100 is composed of basic states B1, B2° and B3, as shown in FIG. 2-1.

The instruction execution unit 102 requests the bus control unit 103 to start a data read cycle by activating the bus request signal 106.

At the same time, a memory reference address is output onto the address line 107 and transferred to the bus control unit 103. Bus control unit 103
In response to the request for activating the data reference cycle, the instruction execution unit 102 outputs the hair removal signal 108 and at the same time activates the data read bus cycle.

The bus control unit 103 outputs the data read address on the AD bus 02 during the B1 period, and at the same time sets the ALE signal 504 to a high level during the T1 period, which is the first half of the B1 period. At the same time, the ID signal 116 is set to low level to select the address latch 111. address latch 111
The MAD must be input via the AD bus 02 in synchronization with the timing tl when the ALE signal 504 goes low level.
Latch address information on bus 109.

The bus control unit 103 sets the D signal 114 to an active low level for a period r of T2 from <82 to the middle of B3. Data is synchronously transferred to the AD bus 02 via the MAD bus 109.
Output on top.

The bus control unit 103 takes in the data read onto the AD bus 02 in synchronization with timing t2, and the instruction execution unit 102 executes predetermined data processing.

・Data write cycle As shown in FIG. 2-2, the data write cycle of the microcomputer 100 is similar to the read bus cycle.
, B2. It consists of the basic states of B3.

The instruction execution unit 102 requests the bus control unit 103 to start a data write cycle by activating the bus request signal 1.6.

At the same time, the reference address of the memory 105 is output onto the address line 107 and transferred to the bus control unit 103.

In response to the request for starting the data reference cycle, the bus control unit 103 sends a hair reference signal 10 to the instruction execution unit 102.
At the same time as outputting 8, a data write bus cycle is activated.

The bus control unit 103 outputs the data write address on the AD bus 02 during the B1 period, and at the same time sets the ALE signal 504 to a high level during the T1 period, which is the first half of the B1 period. At the same time, the ID signal 116 is set to low level to select the address latch 111. The address latch 111 latches the address information on the MAD bus 109 input via the AD bus 02 in synchronization with the timing tl when the ALE signal 504 becomes low level.

The bus control unit 103 sets the WR multiplication signal 15 to an active low level for a period of T2 from 82 to 83, and at the same time outputs write data on the AD bus 02 for a period of T3 from B2 to B3. . The memory 105 is
Within the address location specified by address latch 111, t4 is the rising edge of WR signal 115.
Data is written onto the MAD bus 109 input via the AD bus 02 in synchronization with the AD bus 02.

- Branch cycle The branch cycle of the microcomputer 100 is the second -
As shown in Figure 3, Bl, B2. It consists of B3 basic states.

The instruction execution unit 102 requests the bus control unit 103 to start a branch cycle by activating the bus request signal 106. At the same time, a branch address is output onto the address line 107 and transferred to the bus control section 103.

The bus control unit 103 outputs the hair loss signal 108 to the instruction execution unit 102 in response to the request for starting the branch cycle, and at the same time starts the branch cycle.

The bus control unit 103 outputs the branch address on the AD bus 02 during the B1 period, and at the same time sets the ALE signal 504 to a high level during the T1 period, which is the first half of B1. At the same time, the ID signal 116 is set to high level to select the address counter 110.

The address counter 110 operates the AD bus 02 in synchronization with the timing tl when the ALE signal 504 becomes low level.
The address information on the MAD bus 109 input via the MAD bus 109 is latched.

The bus control unit 103 sets the RD multiplied signal 14 to an active low level for a period of T2 from <82 to the middle of B3. The memory 105 outputs the instruction code from the address location specified by the address counter 110 onto the AD bus 02 via the MAD bus 109 in synchronization with the RD signal 114. The instruction queue 104 is AD Babus 0.
The instruction code read on the QWR signal 118 is fetched and stored in synchronization with the rising edge of the QWR signal 118, ie, the timing t3. Memory 105 is an address counter 110
Increments the contents of and holds the next read address.

- Continuous instruction code read cycle The continuous instruction code read cycle of the microcomputer 100 consists of a B1 state and a plurality of B3 states, as shown in FIG. 2-4.

If no data reference request is generated from the instruction execution unit 102 and the instruction queue 104 is not in a full state, the bus control unit 1
03 starts an instruction code read cycle.

The bus control unit 103 selects the address counter 110 by setting the ID signal 116 to a high level from the beginning of B1, and at the same time, from t4, which is the intermediate timing of <83, to T
The TEN signal 117 is kept active for a period of 3 to request the memory chip 101 to read continuous instruction codes.

The bus control unit 103 maintains the active level of the TEN signal 117 from t4, which is the intermediate timing of <83.
The RD double signal 14 is kept inactive at a high level for a period of 4.

The memory 105 transfers the instruction code from the address location specified by the address counter 110 to the AD bus 02 via the MAD bus 109 in synchronization with the TEN signal 117.
The memory chip 101 activates the QWR signal 118 as a pulse-like signal.

The address counter 110 increments its contents in synchronization with the rising edges of the QWR signal 118, tlo, tll, tl2, . . . , and sequentially updates the read address for the memory 105. The instruction code read out onto the AD bus 02 in synchronization with the rising edge of tio, tll, tl2, etc. is sent to the instruction queue 10.
4 in order.

Next, the configuration of the microcomputer system is the same as that of the first embodiment, and compared to the first embodiment, an output latch is set in the memory 105 to enable faster memory read operation, and the address A second embodiment is shown in which the increment operation of the counter 110 and the read operation from the memory 105 are performed in a pipeline manner.

FIG. 3 shows a block diagram of the memory chip in the second embodiment. The memory 105, address counter 110, address latch 111, and bus interface section 112 of the memory chip 301 are the same as in the first embodiment. , detailed explanation will be omitted.

In addition to the above hardware, an output latch 321 is newly provided to temporarily hold output data from the memory location indicated by the address counter 110.
They are interconnected through an AD bus 109.

Furthermore, since the operation timings of the data read cycle and data write cycle are the same as in the first embodiment, detailed explanations will be omitted.

- Branch cycle The branch cycle of the microcomputer 100 is the same as that in the first embodiment, and as shown in FIG. 4-1, B1, B2 .
It consists of B3 basic states.

In the second embodiment, the process of reading instruction codes from the memory 105 and the process of incrementing the address counter 110 are controlled in a pipeline manner.

The instruction execution unit 102 requests the bus control unit 103 to start a branch cycle by activating the bus request signal 1.6. At the same time, a branch address is output onto the address line 107 and transferred to the bus control section 103.

The bus control unit 103 outputs the hair loss signal 108 to the instruction execution unit 102 in response to the request for starting the branch cycle, and at the same time starts the branch cycle.

The bus control unit 103 outputs the branch address on the AD bus 02 during the B1 period, and at the same time sets the ALE signal 504 to high level during the T1 period, which is the first half of B1. At the same time, the ID signal 116 is set to high level to select the address counter 110.

The address counter 110 operates the AD bus 04 in synchronization with the timing tl when the ALE signal 504 becomes low level.
The branch address information on the MAD bus 109 input via the MAD bus 109 is latched.

The memory chip 301 holds the contents of the memory 105 specified by the address counter 110 in the output latch 321 in synchronization with t20 of the falling edge of the RD signal 114, and at the same time holds the contents of the memory 105 specified by the address counter 110 in synchronization with the falling edge of the RD signal 114 at t20.
is incremented to generate the read address for the next instruction code.

The bus control unit 103 sets the RD signal 114 to an active low level for a period of T2 from 82 to 83. The memory chip 301 outputs the contents of the output latch 321 onto the AD bus 02 via the MAD bus 109 in synchronization with the RD signal 114.

The instruction queue 104 takes in and stores the instruction code read out onto the AD bus 02 in synchronization with timing t3.

The memory chip 101 holds the memory contents specified by the address counter 110 in the output latch 321 again in synchronization with the rising edge 73 of the QWR signal 118, and at the same time increments the address counter 110 in synchronization with the same time t3. A read address for the instruction code is generated and preparations are made for reading the next instruction code.

- Continuous instruction code read cycle The continuous instruction code read cycle of the microcomputer 100 is also similar to the first embodiment, and consists of a B1 state and a plurality of B3 states, as shown in FIG. 4-2.

Similarly to the branch cycle, in the continuous instruction code read cycle in the second embodiment, the instruction code read process from the memory 105 and the increment process of the address counter 110 are controlled in a pipeline manner.

The bus interface unit 112 transfers the instruction code from the output latch 321 to the AD bus 02 via the MAD bus 109.
Output on top. Furthermore, the memory chip 101 receives the QWR signal 1.
18, the microcomputer detects the rising edge of the QWR signal 118, tlO
, tll, t12, . . . , the instruction code read out onto the AD bus 02 is stored in the instruction queue 104. At the same time, the memory chips are tlo, tll, t12,
The instruction code to be read next is read out in advance into the output latch 321 in synchronization with . . . and at the same time, the contents of the address counter 110 are updated.

〔Effect of the invention〕

The present invention makes it possible to read in advance the address next to the reference address by providing an address counter on the memory side. Furthermore, by supplying a write signal to the instruction queue from the memory side to the microcomputer, the instruction processing of the microcomputer itself and the instruction code read from the memory can be realized completely asynchronously and at high speed.

As explained above, the present invention can provide a very high-speed microcomputer system having a very high-speed memory with short access time, and has very high practical effects.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a microcomputer system according to a first embodiment of the present invention, FIG. 2 is a timing chart showing a bus cycle in the microcomputer system according to the first embodiment, and FIG. 3 is a diagram of the present invention. A configuration diagram of a microcomputer system according to a second embodiment of the invention, FIG.
FIG. 5 is a configuration diagram of a conventional microcomputer system, and FIG. 6 is a timing chart showing bus cycles in a conventional microcomputer system. . 100.500...Microcomputer, 101.
301...Memory chip, 102,503...Instruction execution unit, 103...Bus control unit, 104...Instruction queue, 105,501...Memory, 106...Bus request signal, 107... ...address line, 108...
・Acknowledge signal, 109...MAD bus, 110
... Address counter, 111, 505 ... Address latch, 112 ... Bus interface section, 113
...Reset signal, 114,506...RD signal,
115...WR signal, 116...ID signal, 117
...TEN signal, 118...QWR signal, 119.
...Control gate, 120...QFL signal, 321...
・Output latch, 502...AD bus 504...A
LE signal.

Claims (1)

[Scope of Claims] In a microcomputer system having storage means for storing various processing data including instruction codes, and data processing means for performing data processing by executing instructions, the data processing means stores instruction codes. the storage means has a buffer register; the storage means has a control means for controlling transfer of instruction codes; and an instruction means for storing instruction information for instructing the storage contents of the storage means; the control means has a control means for controlling the transfer of instruction codes; and a first transfer means for performing one data transfer with the specified storage means, following the sending of instruction information instructing a read destination in data transfer between the data processing means and the data processing means; and outputs a control signal to the instruction means to designate the writing timing of the instruction code to the buffer register and at the same time updates the instruction means to the address to be read next, so that the instruction information can be read from the storage means without sending out instruction information. A microcomputer system comprising a second transfer means for continuously transferring instruction codes between the data processing means.