JPH0256028A - Microcomputer system - Google Patents

Abstract

PURPOSE:To improve the processing speed by prereading continuously data corresponding to the next address of an instruction code or data which is read out on an AD bus by an address pointer to which an incrementer is added and an output latch for holding read-out data from a memory. CONSTITUTION:When a fundamental operation clock CLK 307 from an oscillator 108 becomes '0', a control signal C3 becomes '1', and data is written in a data latch DTL 212. Also, simultaneously, since a control signal C1 is '1', an address being an output of an incrementer 208 is written in a pointer DP 207. Moreover, since control signals C4, C8 are both '0', an output of a NOR gate 219 becomes '1', a read-out buffer 223 becomes a conducting state, and data is outputted onto an address ADR bus 218. A bus interface part 201 outputs the data onto an AD bus 300. A microprocessor 100 inputs the data by a timing in which the CLK 307 is '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer including a microprocessor and a memory.

[Conventional technology]

In recent years, improvements in the architecture of microprocessors have made it possible to process instructions at extremely high speeds, but due to access speed limitations when reading programs and data from memory, it takes longer than the processing time of a microprocessor. It takes a relatively long time and causes a decrease in the instruction execution time of the microprocessor. In particular, when reading and inputting instruction codes stored in consecutive addresses like a program, most of the processing time of the entire microprocessor is spent waiting for the instruction code from memory, which increases the processing speed of the entire microcomputer system. is decreasing.

θ The microcomputer shown in the first subfigure is a microprocessor-000 that controls data input/output processing and the entire microcomputer, and a multiplexed address information, instruction code, and input data output from the microprocessor-000. It consists of an address latch 1205 for multiplexing and a memory 1201 for storing processing data and programs of the four microphone processors 000, and these units form an address data multiplex bus 1301 (hereinafter referred to as "AD bus").
, a row active read signal (hereinafter referred to as "RA double signal") 1302 that the microprocessor-000 outputs to read data and programs stored in the memory 301, and a row active read signal (hereinafter referred to as "RA double signal") 1302 to store an address in the address latch 1205. It is connected to the ASTB signal 1303 to be output.

Next, the flow of address information and data on the microprocessor-000 and the AD bus during continuous input of programs placed at consecutive addresses will be explained with reference to FIG.

Normally, programs are stored in consecutive memory areas in sequence, and the microprocessor-000 reads and executes these programs via the AD 1301 in accordance with the address order.The program input is as shown in FIG. As shown in Bl,
B2. It consists of the basic state of B2.

First, the microprocessor-000 activates the ASTB signal 1303 during the %BlB1 state and simultaneously outputs a read address onto the AD bus 301 from the B1 state to the B2 state. The RD signal 1302 is set to "0" in the middle of the B2 state and set to "1" in the middle of the Bz state. During the active period of this RD signal 1302, the AD bus 301 is transferred from the memory 1201.
The microprocessor 1000 reads the data on the AD bus 30 at a predetermined timing in the %B3 state.
Import data onto 1.

Through the above series of processes, one cycle of the program input data read cycle is completed.

[Problem to be solved by the invention]

In this way, although the addresses of instructions to be executed are continuous unless a branch instruction or other instruction that changes the processing sequence is executed, conventional Microphone 4 computers generate an address every time an instruction is fetched. The processing speed is fast.

Therefore, an object of the present invention is to provide a microcomputer system with improved processing speed.

[Means to solve the problem]

A microcomputer system according to the present invention includes a storage means for storing various processing data including instruction codes, and a data processing means for processing data by executing instructions, in which an address for storing address information of the storage means is provided. an instruction means, an update means for updating the contents stored in the address instruction means, a holding means for holding the output of the storage means instructed and read by the address instruction means, and synchronized with an operating clock of the microcomputer system. and the storage means instructed subsequent to the sending of read address information to the address instruction means in data transfer between the control means for controlling the updating means and the holding means, the storage means, and the data processing means. and a first data transfer means for performing one data transfer with the data processing means, and the storage means for controlling the control means into an operating state, and storing the storage means corresponding to the contents of the address instruction means in the holding means. By holding the read data from and storing the next address to be read in the address instruction means in advance, continuous data transfer can be performed between the holding means and the data processing means without sending out address information. Second to do
data transfer means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The microcomputer system shown in FIG. 1 includes a microprocessor 100 that controls data input/output processing, calculation processing, and the entire microcomputer, and a read-only memory ROM 210 that stores programs executed by the microprocessor 100 and data necessary for calculations. (hereinafter referred to as "memory") is composed of an LSI 200 with a built-in memory.

The microprocessor 100 includes a processing execution unit 101 that executes instructions, an execution control unit 103 that controls the overall operation of the microprocessor 100, and a processing execution unit 1 that stores instructions and data read from a memory 210 in the order in which they are read.
01, and an oscillator 108 that generates a clock signal 307 for operating the microprocessor 100.

A bus request signal 1 is sent from the processing execution unit 101 to the execution control unit 103 to request activation of a memory 210 in the LSI 200 and a data read cycle, which will be described later, upon execution of an instruction.
05 and an address line 104 carrying the address information of the access destination of the memory 210 are output, and the execution control section 103 receives the start of the data read cycle and outputs the 7 key register signal 106 to the processing execution section. The microprocessor 100 reads data from the memory 210 in the LSI 200 via the AD bus 00 in which address information and data are multiplexed. The clock generated by the oscillator 108 is supplied to the microprocessor 100 as a basic operating clock, and is also input to the LSI 200 as a synchronization clock for reading instructions and data.

The LSI 200 receives outputs from the microprocessor 100 and outputs control signals CI, Cts C1#C4,C to interface with the microprocessor 100.
6, the memory 210 that stores programs and data of the microprocessor 100, and the address bus (hereinafter referred to as "ADR bus") that is input from the AD bus 00 and the bus interface section 201 and the address bus inside the LSI 200. ) 218, there is a pointer FP 203 (controlled by the C2 signal output during the instruction code read cycle) into which address information is written, and another pointer DP 206 (controlled by the C1 signal output during the data read cycle). ), an incrementer 205 that increments the contents of the FP 203, and a multiplexer MPXI 204 that selects the output of the incrementer 205 under the control of a C1 signal output during consecutive instruction read cycles and consecutive data read cycles, which will be described later. An incrementer 208 increments the contents of DP206, a multiplexer 207 selects the output of incrementer 208 in synchronization with the C1 signal, and selects the output of FP203 based on the C6 signal output during continuous instruction code read cycles. to the memory 210 via an internal address bus (hereinafter “AB”).
Multiplexer 2 supplied as 219
09, and a hood latch (hereinafter referred to as "CDL") 21 that stores data read from the memory 210 based on the C2 signal output during continuous instruction code read cycles.
1, a data latch 212 that stores data read from the memory 210 based on the C8 signal similarly output during continuous data read cycles, and an output latch 1 21
1. Output latch 2212. Read buffers 221, 222, 223, . It is made up of. Further, both the Ca and Cs signals are input to the NOR gate 219, and when both the Cm and Ca signals are "0", the NOR gate 219 receives the NOR gate 219.
The output of R game) 219 becomes "1".

Next, control signals input to and output from the microprocessor 100 and the LSI 200 will be explained.

As input control signals to the microprocessor 100,
There is a reset signal 306 for initializing the hardware within microprocessor 100. As a control signal from the microprocessor 100 to the LSI 200,
Address information on AD Babasu 00 to FP203 or DP
An ASTB signal 301 for storing data in the memory 206, a low active RD signal 302 for reading data from the memory 210, an M1 signal 304 for setting a read mode from the memory 210, and a continuous signal 304 to be described later. The microprocessor 10 is used as an M2 signal 305 for controlling readout of instruction food and data and setting a readout mode, and as a synchronization clock in continuous instruction code read and continuous data read cycles, which will be described later.
There is a basic operation clock CLK307 of 0.

When the ASTB signal 301 is “1”, the M1 signal 304,
Depending on the level of both M2 signals 305, the LSI 200
read operation is set.

When the ASTB signal 301 is “1”, the M1 signal 304, M
When the levels of the two signals 305 are "0" and "0", respectively, a continuous data read cycle is set. Also, M1
Signal 304. The level of M2 signal 305 is “0” respectively.
, '0', a continuous data read cycle is set.Similarly, when the levels of the M+(= sign 304 and Mz signal 305 are '0' and '1' respectively, one data read cycle is set. Set.

Next, FIG. 2 shows a detailed diagram of the control signal generating section 202 and will be described. Flip-flop (hereinafter referred to as “F/F”) 4
00 writes the level of the M2 signal at the rising timing of CLK307. F/F411.412,413,4
14 is the falling timing of the ASTB signal, and M1 signal 3
04. The level decoded by the decode 410 for the level of the M2 signal 303 is written. Further, F/Fs 411, 413, and 414 are cleared to "O" by a signal generated from the rise detection circuit 409 at the rise timing of the ASTB signal 305. Decoder 410 is M1
Signal 304. The level of M2 signal 305 is “l”0”1”
1""0",'1"0" F/F when "0" respectively
In order to write "1" to 411, 412, 413, and 414, the corresponding signal output is set to "1". F/F416
writes the output of the F/F 411 at the falling timing of the M1 signal 304. F/F411, 412, 413,
414 is written with '1' in the address setting cycle of a continuous instruction code read cycle, the read cycle of a continuous instruction food read cycle, the continuous data read cycle, and one data read cycle, respectively.F
/F 417 has F at the rising timing of CLK307.
/F416 output is written. The control signal C1 is “
The control signal C2 is a signal that becomes "0" when the % Mz signal 305 is "0" in consecutive instruction code read cycles.
The control signal C1 is a signal that becomes "1" when the CLK307 is "O" and the M1 signal 304 is "1".The control signal C1 is a signal that becomes "1" when the M2 signal 303 is "0" and the CLK3 signal is "0" during a continuous data read cycle.
This signal becomes "1" when 07 is "0" and when ASTD signal 301 is "1". The control signal C4 is a signal that becomes "1" when the RD signal 301 is "0" during one data read cycle. The control signal C0 is a signal that becomes "1" during consecutive instruction code read cycles.

! Next, the operation of the continuous command hood read cycle will be explained with reference to the diagram. Continuous instruction code read cycles are
Basic state for address setting (hereinafter referred to as "BR state") and B5 for continuously reading instruction codes
．． The execution control unit 103 outputs various control signals to the LSI 200 in these states to control the instruction code in the memory 210 as the instruction is executed. Controls the read cycle. Note that when continuing to read out continuous instruction codes, the Bs state is continued.

First, the microprocessor 100 sets the ASTB signal 301 to "1" and the M1 signal 304 to "1" in the %Bl state.
, sets the M2 signal 305 to "0" and outputs the address "N" onto the AD bus 00. In the LSI 200, the control signal generating unit 202 sets the control signals Cz and Cs to "L" and sets the address "N" to the address latch 221. MPX2 20
7 to the DP 206.

Next, when the ASTB signal 301 falls in the middle of the Bs state, the output of the F/F 411 becomes "1".

When the AsTB signal 301 falls and becomes "0", the control signal C2 becomes "1" and the content "N" of DP206 is transferred to FP20.
3 via MPX204.

Next, the M1 signal 304 falls in the middle of the B state, the control signal C2 becomes "0", and the contents of the FP203 "
N'' is supplied to the memory 210 as the AB bus 19 via the MPX3209, and the memory 210 outputs the address “
An instruction code (N) corresponding to N'' is output.

Next, when CLK307 becomes “1” in state B, F
The output of /F 417 becomes “1” and the control signal C1 becomes “
The MPXI 204 selects the output of the incrementer 205. B, CLK in the middle of the state
307 becomes "0", the control signal C6 becomes "1", and the memo! The output (N) of 3210 is the output latch l 211
will be written to.

Further, 1 is added by the incrementer 204, and the next address “N+1” of N is written to the FP 203. At the same time, since the control signal C6 is "1", the content (N) of the output latch 1 is output to the bus interface section 201, and the R
Since the D signal 302 is "0", the output buffer 223 becomes conductive, and data (N) is read onto the AD bus 00. Then, the execution control unit 103 selects CLK307 in the B4 state.
is input at the timing of “1”, transfers (N) to the data queue 102, and the execution processing unit 101 receives the instruction code (N).
is decoded and the process corresponding to the instruction code (N) is executed.

Next, the %B4Bs state 2 signal 303 becomes "1".

When CLK307 becomes “0” in the middle of B4 state,
The control signal C2 becomes “1” and the output latch 1211 has
The instruction food (N+1) corresponding to address “N+1” is written, and the following address “N+
2" is written. At this time, the RD signal 302 becomes "1", so the bus interface unit 201 does not output anything to the AD bus 00. At the beginning of the B state, the M
1 signal 304 rises and becomes “1”, F/F 41
1,413,414 becomes “O” and F/F412 becomes “
1", but the control signals C1 and C6 remain "1". The M2 signal 303 also becomes "0". Since the RD signal 302 becomes "0" in the middle of the B state, the instruction code (N+1) is read out on the AD bus 00.Also, CLK307 becomes 0'', but M2 signal 305 becomes B4
Since it is "1" in the Bs state, the output of the inverter 401 is "0'" and the control signal C! remains "0".

Next, in the middle of the B6 state, the output of the inverter 401 becomes “
1", so when CLK307 becomes "0", control signal C2 becomes "1", and the instruction code (N+2) corresponding to address "N+2" is written to output latch 1211, and then on AD bus 00. Instruction code (N+
2) is read out. At the same time, the following address (N+3)
is written to the FP 203. Similarly, in the next B6 state, the instruction code (N+
3) is read onto AD bus 00.

In the final B state, the M2 signal 305 becomes "1". Also, since the RD signal 302 becomes "1" in the middle of the B state, the bus interface unit 201 does not output anything to the AD bus 00 after the instruction code (N+3). In the middle of state B, the control signal C2 becomes "1", so
FP203 has address "N+5"', and CDL2
11 is the instruction code (N+
4) is written and the continuous instruction hood read cycle ends. In the next state after state B, the output of the inverter 401 becomes "0", so the control signal C3 becomes "0".
” remains.

As mentioned above, in continuous instruction code read cycles, FP
203 and CDL 211, instruction codes stored in memory 210 are continuously read out onto AD bus 00 in synchronization with the rising edge of CLK 307, and microprocessor 100 cycles. One data read cycle consists of Bl, Bt, and Bs states. In the B1 state, the microprocessor 100 sets the ASTB signal 305 to “1” rM 1 signal 3
04 to "0" and the Mt signal 303 to "1". Also,
Address “K” is output on AD bus 00.

Then, the control signal C3 becomes "1", so the DP207
Address "K" is written thereon, and data corresponding to address "K" in memory 210 is accessed. When the ASTB signal 301 becomes “0” in the middle of the B1 state,
The output of F/F414 becomes 'l'. R in B2 state
When the D signal 302 becomes "0", the control signal C4 becomes "l"
Then, the output buffer 222 becomes conductive, and the data (K) in the memory 210 corresponding to the address "K" becomes AD bus 00.
read out above. In the middle of state B, the microprocessor-00 sets the RD signal 302 to "1". The microprocessor-00 inputs data (K) at a timing determined by the %BSB1 state, and the processing execution unit 103 uses the data as data for calculations. Since the control signal C2 remains at "0" during one data read cycle, the contents of the FP203 remain at the address "1" and do not change.

Next, a continuous data read cycle will be explained using FIG. Continuous data read cycles are B,,B2
．． It consists of B, , B4 cycles, and the B state is repeated when data is read out continuously. In the B1 state, the microprocessor-00 sets the ASTB signal 305 to "1", the M1 signal 304 to "0", and the M2 signal 3
Set 03 to “1”. It also outputs the address "L" onto the AD bus 00. Then, the control signal C3 becomes "1" and the address "L" is stored in the address latch 221, and at the same time, the address "L" is written in the DP 207. In the middle of the B1 state, the F/F 414 becomes "1". In the B2 state, the ASTB signal 305 becomes "1" and the M2 signal 303 becomes "0", so the F/F 413 becomes "1" in the middle of the B2 state. Since it becomes "L", the control signal C1 becomes '1'.The address "L" is MPX3 2
09 to the memory 210, and the address “L”
Notes corresponding to! Data (L) of 7210 is read out.

When CLK307 becomes “0” in the middle of B3 state,
The control signal C8 becomes “1” and the data (L) becomes DTL2.
Written in 12. At the same time, the control signal C1 is “
1", the address "L+1", which is the output of the incrementer 208, is written to the DP 206. Also, since the control signals C4 and CI are both "0", the NOR gate 21
9 becomes "1", the read buffer 222 becomes conductive, and data "L" is output onto the ADR bus 216. Pass interface entry section 201 is data “L”
is output on AD bus 00. microprocessor 1
00 is the next B, and data (L) is input at the timing when CLK307 of the cycle is "1". The same operation is performed in the continuation<B3 state.

In the last state B, the microprocessor 100
2 signal 305 is set to "1". Then, since the output of the inverter 401 becomes "0" in the B4 state, the control signal C6 is not output even if the CLK 307 becomes "0" in the B4 state. In state B4, microprocessor 10
0 sets the RD signal 302 to "1" and ends the continuous data read cycle.

As mentioned above, in continuous data read cycles, CLK
The contents of the DP 207 are updated in synchronization with the falling edge of the DP 207, and the data in the memory 210 corresponding to the contents of the DP 206 can be continuously read out via the TL 212. At this time, the control signal C2 remains at "0" and does not change, so the contents of the FP 203 do not change. As described above, in the above-mentioned microcomputer, the microprocessor 100 controls the M2 signal 305 to continuously read instruction codes from the memory 210 in synchronization with the basic operating clock of the microphone Yobuta processor.

Data can be read. It is also possible to read data once.

Next, a second embodiment of the present invention will be described using FIGS. 3 and 4.

The microcomputer shown in FIG. 3 differs from the microcomputer described in FIG. 1 in that the memory 210 is composed of a random access memory (RAM) from which data can be read and written, and a row active write signal WR303° is used. A control signal Cal write buffer 224 is added. Therefore, in this embodiment, the first
The parts that are different from the diagram will be explained. The microprocessor 100 supplies the LSI 200 with a WR signal 303 for writing into the memory 210 write data to be output onto the AD bus 00 following the address.

In Figure 4, the output of F/F414 is "1" and WR
When the signal 303 is "0", the output of the AND gate 500 becomes "1", and the control signal C8, which is the output of the OR gate 504, becomes "1". Further, the F/F 503 is written at the falling timing of CLK 307, which is the output of the inverter 401. F/F413 output is “1”, F/F50
When the output of 3 is “1” and CLK307 is “1”, AND
The output of gate 502 becomes “L”, and OR gate 504
The control signal C, which is the output of , becomes "1".

When the control signal C3 becomes "1", the write buffer 224 becomes active, and the write data on the AD bus 00 is written to the memory 210.

Next, the microprocessor-00 continuously writes data to the memory 210. The cycle will be explained using the timing chart shown in FIG. A continuous data cycle consists of states B, , Bl, B, , B4. The Br and Bs states are the same as those in the data read cycle, so their explanation will be omitted. In the Bs state, the microprocessor 100 outputs the WR signal 302.
and set the address “M” to “θ” on the AD bus 00.
Outputs the data (M) to be written to the address of the memory 210 corresponding to ”.B, F/F 5 in the middle of the state
Since the output of 03 becomes “1”, the next Bs state C
When LK307 is “1”, control signal C6 is “1”.
”, the write buffer 223 becomes conductive, and
Data (M) on the AD bus 00 is written to the memory 210 via the bus interface section 201. Continued<
A similar operation is performed in the Bs state. The last B,
Since the M2 signal 305 becomes “1” in the state, %B4B
After the s-state control signal Cs becomes "1", the control signal C6 remains "0". Address “ in B4 state
Data CM+3) corresponding to “M+3” is written to the memory 210.

In the above two embodiments, the internal bus AD'' of the LSI 200
The R/< bus 218 used to be a multiplex bus, but the microcomputer shown in Figure 1 has an address bus and a data path. The address bus (hereinafter referred to as “A bus”) is the output of
) 332, and output buffers 221, 222, 22
3 instead of multiplexer MPX4 332 and MPX
The configuration is the same as that of the microcomputer shown in FIG. 1, except that a data bus (hereinafter referred to as "D bus"), which is the output of 4332, is added.

Therefore, in this embodiment, the parts different from those in FIG. 1 will be explained. LSI 200 is a microprocessor 10
The address information input from 0 is sent to the AsTB signal 305.
Addressra during the “l” period of.

MPX2 207 with address information stored in address latch 331 as A bus 332.
Output to. MPXI selects the output of the incrementer 206 or the output of the DP 206 under the control of the C1 signal and outputs it to the FP 203.

MPX2 uses the incrementer 208 under the control of the C1 signal.
Select the output of DP206 or the output of A bus 3312.
Output to.

The MPX3 209 reads the FP203. A bus 332. Or select the output of DP206 and take a note! Output to 7210. CDL211 is
Data read from the memory 210 is stored based on the C2 signal output during consecutive instruction code read cycles. Similarly, the DTL 212 stores data read from the memory 210 based on the 03 signal output during consecutive read cycles. MPX4 223 is CDL211, D
TL212. The output of the memory 210 is controlled by control signals Ct and Cm.
The operation of the cycle in which the selected data and the output of the NOR gate 219 are respectively selected and output to the D bus 234 will be explained.

The continuous instruction code read cycle consists of a basic state for setting an address (hereinafter referred to as the ``BR state'') and a Bs, Ba, Br state (hereinafter referred to as ``CNFCN-to'') for successively reading out the instruction code. ), and the execution control unit 103 controls the instruction code read cycle of the memory 210 accompanying instruction execution by outputting various control signals to the L-8 device 200 in these states. When continuing to read continuous instruction codes, the B6 state is continued.

First, the microprocessor 100 uses the A
STB signal 301 is “1” + M+ signal 304 is “l”
The 1M2 signal 305 is set to "0" and the address "N" is output onto the AD bus 00. In the LSI 200, the control signal generating unit 202 sets the control signals Ox and Cs to "1" and sets the address "N" to the address latch 232. MPX2 20
7 to the DP 206.

Next, when the ASTB signal 301 falls in the middle of the B state, the output of the F/F 411 becomes "1".

When the ASTB signal 301 falls and becomes "0", the control signal C2 becomes "1" and the content "N" of DP206 is transferred to FP20.
3 via MPX204.

Next, the M1 signal 304 falls in the middle of the B2 state, the control signal C2 becomes "0", and the contents of the FP203 "
N” is supplied to the memory 210 as the AB bus 19 via the MPX3209, and the address “N” is supplied from the memory 210 as the AB bus 19.
An instruction code (N) corresponding to "N" is output.

Next, when CLK307 becomes “1” in state B, F
The output of /F 417 becomes “1” and the control signal C1 becomes “
1', so the MPXI 204 selects the output of the incrementer 205. CLK in the middle of B3 state
307 becomes "0", the control signal C2 becomes "1", and the output (N) of the memory 210 is written to the output latch 1211.

Further, 1 is added by the incrementer 204, and the next address “N+1” of N is written to the FP 203.

At the same time, since the control signal C6 is "1", the content (N) of the output latch 1 is output to the bus interface section 201 via the RD bus 14, and since the RD signal 302 is "0", the output cover and the fiber 223 are rendered conductive. and data (N
) is read out. Then, the execution control unit 103 receives an input at the timing when CLK307 in the B4 state is "1",
(N) is transferred to the data queue 102 and the execution processing unit 10
1 decodes the instruction code (N) and executes the process corresponding to the instruction code (N).

Next, the M2 signal 303 becomes "1" in the B4 state.

When CLK307 becomes “0” in the middle of B4 state,
The control signal C2 becomes “1” and the output latch 1211 has
The instruction code (N+1) corresponding to address “N+1” is written, and the following address “N+
2" is written. At this time, the RD signal 302 becomes "1", so the bus interface unit 201 does not output anything to the AD bus 00. At the beginning of the B state, the M
1 signal 304 rises and becomes “1”, F/F41
1,413,414 becomes “0” and F/F412 becomes “
1", but the control signals C1 and 06 remain "1". The M2 signal 303 also becomes "0". Since the RD signal 302 becomes 0" in the middle of state B, the instruction hood (N+1) is read onto AD bus 00. Also, 307 becomes “0” in CL, but M2 signal 305 becomes “0”.
Since it is "1" in four states, the output of the inverter 401 is "On" in the Bs state, and the control signal C7 remains "0".

Next, in the middle of the B6 state, the output of the inverter 401 becomes “
1", so when the CLK307 becomes 0, the control signal C2 becomes "1" and the instruction code (N+2) corresponding to the address "N+2" is written to the output latch 1211, and the instruction is written on the AD bus 00. Code (N+2
) is read out. At the same time, the following address (N+3) is written to the FP 203. Similarly, in the next B1 state, the instruction code (N+3
) is read onto AD bus 00.

The last B, state, M! The signal 305 becomes "1". Further, since the RD signal 302 becomes "1" in the middle of the B state, the bus interface unit 201 does not output anything to the AD bus 00 after the instruction code (N+3). In the middle of the BT state, the control signal C2 becomes 1", so F
P203 becomes address "N+5", and the instruction food (N+4) corresponding to address "N+4" is written in CDL 211, and the continuous instruction code read cycle ends. In the next state after the B7 state, the inverter 401
Since the output of is "0", the control signal C2 remains "0".

As mentioned above, in continuous instruction code read cycles, FP
203 and CDL 211, the instruction food stored in the memory 210 is continuously read out onto the AD bus 00 in synchronization with the rising edge of CLK 307, and the microprocessor 00 executes the corresponding processing.

Next, one data read cycle will be explained using FIG. One data read cycle is B
+ r B 21 B It is composed of s states.

In the B1 state, microprocessor-00
TB signal 305 is “1” IM + signal 304 is “0” 2M
The t signal 303 is set to "1". It also outputs the address "K" onto the AD bus 00.

Then, the control signal Cs becomes "1", so the DP207
Address "X" is written thereon, and data corresponding to address "K" in memory 210 is accessed. When the ASTB signal 301 becomes “0” in the middle of the B1 state,
The output of F/F 414 becomes "1". When the RD signal 302 becomes “0” in the B2 state, the control signal C1 becomes “l”.
", the output buffer 222 in the bus interface unit 201 becomes conductive, and the memory 2 corresponding to the address "K"
10 data (K) is read onto the AD bus 00 via the RD bus 14. In the middle of the B state, the microbe 4S 9S 100 sets the RD signal 302 to "1".

The microprocessor 100 inputs data (K) at a predetermined timing in the B3 state and executes the process execution unit 103.
is used as data in calculations. Since the control signal C3 remains “0” during one data read cycle, the FP203
This section explains the rules. Continuous data read cycle is B
l, B2. Consisting of Bs and Ba cycles, continuously
When data is read, state B is repeated. In the B1 state, the microprocessor 100
sTB signal 305 is “1” M1 signal 304 is “0” l
The Mg signal 303 is set to "L". Also, AD Babasu 00
Address “L” is output on the top. Then, the control signal C1
becomes “1” and the address “L” is sent to the address latch 221.
is stored, and at the same time, the address "L" is written to the DP 207. In the middle of B1 state, F/F 414 is “
1". Even in state B, the ASTB signal 305 is
becomes “1” and the M2 signal 303 becomes “0”, so B
Since F'/F' 413 becomes "1" in the middle of the two states, the control signal C2 becomes "1". Address “L” is
The signal is supplied to the memory 210 via the MPX 3209, and data (L) of the memory 210 corresponding to the address "L" is read out.

B. When CLK307 becomes "o" in the middle of state,
The control signal Cs becomes “1” and the data (L) becomes DTL2.
Written in 12. At the same time, the control signal C1 is “
1", the address "L+1", which is the output of the incrementer 208, is written to the DP 206. Also, since the control signals C4 and C@ are both "0", the NOR game) 21
The output of DTL 212 is selected and output to RD bus 14. At this time, since the RD signal 302 is "0", the output buffer 222 becomes conductive, and the instruction code (L+1) is read onto the AD bus 00. The microprocessor 100 inputs data (L) at the timing when the CLK307 of the next B cycle is 1''.The same operation is performed in the following B□ state.In the final B3 state, the microprocessor 100 inputs the M2 signal 305. Set to "1".Then, the output of the inverter 401 becomes "0" in the B4 state, so the control signal C6 is not output even if the CLK307 becomes "0" in the B state.In the B state, the microprocessor 101 sets the RD signal 302 to "1" and ends the continuous data read cycle.

As mentioned above, in continuous data read cycles, CLK
The contents of the DP 207 are updated in synchronization with the falling edge of the DP 207, and the data in the memory 210 corresponding to the contents of the DP 206 can be continuously read out via the DTL 212. At this time, the control signal C2 remains at "0" and does not change, so the contents of the FP 203 do not change. As mentioned above,
In the microcomputer described above, the microprocessor 100 controls the M2 signal 305 to continuously read instruction codes from the memory 210 in synchronization with the basic operating clock of the microprocessor.

Data can be read. It is also possible to read data once.

As described above, it is clear that the effect of high-speed memory access is not impaired even if the address and data are configured with separate buses.

〔Effect of the invention〕

As explained above, in systems that require particularly high-speed program reading and data reading, the present invention requires the addition of a high-speed reference function to the storage device itself. The data corresponding to the next address of the instruction code or data being read on the AD bus is continuously read ahead by the output latch that holds the read data from the memory. Because it is used as a periodic signal to read out instruction codes and data, the instruction code and data reading operations operate almost simultaneously with the microprocessor operations.
Since there is almost no delay, the access time is very short, and the effect is to provide a high-performance microcomputer that can continuously read instructions and data at high speed and provide memory that improves the processing performance of the microprocessor.

is a timing diagram of one data read cycle, and is a timing diagram of a data read cycle in a conventional example.

Claims (1)

[Scope of Claims] A microcomputer system having storage means for storing various processing data including instruction codes, and data processing means for processing data by executing instructions, comprising: address instruction means for storing address information of the storage means. an updating means for updating the contents stored in the address instruction means; a holding means for holding the output of the storage means instructed and read by the address instruction means; control means for controlling the updating means and the holding means in synchronization with the operating clock of the microcomputer system through a bus line for transferring output to the processing means; data of the storage means; and the data processing means. A first data transfer in which one data transfer is performed via the bus line between the storage means and the data processing means instructed after sending read address information to the address instruction means in the transfer. control means and the control means to be in an operating state, causing the holding means to hold read data from the storage means corresponding to the contents of the address instruction means, and causing the address instruction means to preemptively set the address to be read next. and a second data transfer means that sequentially transfers data by storing the address information in the storage means and the data processing means by passing the bus line between the holding means and the data processing means without transmitting the address information. microcomputer system.