JPS58219645A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent a processor from occupying a register and to increase its execution speed, by providing a counter circuit which counts up and down with regard to one block in a memory and a multiplexer which selects address information externally. CONSTITUTION:The processor 1 inputs and outputs data in successive areas in the memory 5 through a data bus 2 and an address bus 3. A multiplexer 25 inputs a signal from the address bus 3 as one input and the output of the up/ down counter register 21 as the other input. When the multiplexer 25 selects the input from the bus 3, normal memory access is attained. When, however, the processor 1 performs reading/writing operation from and to a specific address, a logical circuit 22 generates a signal S. The signal S sets the register 21, an OR circuit 26, and an FF24 for specifying up or down counting, and then the multiplexer 25 selects the register 21. Consequently, memory contents of an address specified by the register 21 are read in the processor 1. The contents of the register 21 are increased or decreased as specified by the FF24 after the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer constituted by a microprocessor having nine registers and limited functions, and particularly to an improvement of its memory access section.

FIG. 1 shows the configuration of a typical microcomputer.

In the figure, 1 is a microprocessor, 2 is a data bus, 3 is an address bus, 4 is a control bus, 5 is a memory, 6 is a logic circuit for controlling this memory 5, and this logic circuit 6 is an address decoder. Equipped with etc.

In the microcomputer configured as described above, the microprocessor 1 is generally not equipped with an auto-increment and auto-decrement register. Therefore, when the microprocessor 1 accesses and processes consecutive areas of the memory 5, the program is as shown in FIG.

(1) In block 10, an address of the memory 5 to be accessed is set in a register (pointer register: abbreviated as PR) inside the microprocessor 1 that can be indirectly specified.

(11) In block 11, data is read from the indirectly designated memory into a predetermined register inside processor 1. This is written as (PR)→DR within the block.

010 Block 12 processes the read data.

fIV) In block 13, PR is increased to prepare for the next data access.

M Block 14 determines whether or not the process has ended, and if not, the processing from block 11 onward is repeated.

However, the above program assumes a processor whose effective address is the contents of an internal register.

If the processor IK does not have auto-increment and auto-decrement registers, a program like the one shown in Figure 2 will be executed, occupying registers for address information, and manipulating address information. also required.

Therefore, in the present invention, by providing an external counter circuit that can raise and lower one block of memory and a multiplexer that selects memory address information,
This is intended to prevent address information from occupying processor registers and to increase execution speed.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 3 shows an embodiment of the present invention, in which 1 is a microprocessor, 2 is a data bus, 3 is an address bus, 4-digit control bus, 5 is a memory, and a 21Vi presettable and readable up/down counter register. It is. The preset value of this register 21 is set by the microprocessor 1 through the data bus 2, and the load signal is applied to the register 21 through a line 23 as an output of a logic circuit 22 comprising an address decoder and the like. Reference numeral 24 is a 7-lip 70 tab for designating up/down of the up/down counter, and its setting and reset are set by the microprocessor 1 through the data bus 2 in accordance with the output of the logic circuit 22. 25 is a multiplexer, one input of which is the signal of the address bus 3, the other input of which is the output of the counter register 21, and the output of the logic circuit 22 selects one read/write signal. When the signal S1 is present, it is on the counter register 21 side, and when the signal S1 is strong, it is on the address bus 3 side. 26 is an OR circuit, the output of which is used to designate reading/writing of the memory 5. A signal Sl is added as one of the inputs of this OR circuit 26.

Furthermore, the signal S1 is a read/write signal generated in the logic circuit 17 when the processor 1 reads/writes a specific address (defined by the address decoder of the logic circuit 22), and this signal S1 is It is also involved in the up and down operations of the register 22. Further, a counter register 22, a multiplexer 25, etc. are provided for one block of the memory 5.

Next, the operation, particularly the operation when nine consecutive areas of the memory 5 are accessed, will be explained with reference to the program shown in FIG.

(1) In the block 30, the start address of the memory 5 to be accessed to the counter register 21 is set (EXPR set), and the flip-flop 2 for up/down is set.
Set 4.

(11) In the block 31, the address defined by the address decoder of the logic circuit 22 is accessed 1.
1 reads the memory contents of the address specified by the counter register 21 into the data register (DR) inside the processor l (or writes them conversely) e When this process is completed, the counter register 21 reads/writes the specified address. 7 lip flops 24 at the edge of the signal
Up or down its contents by specifying.

(Il[) In block 32, processing is performed on the read data.

(ψ Block 33 determines whether or not it is finished, and if not, repeats the processing from block 31 onwards.

By providing the counter register 21 that can be auto-incremented and decremented externally in this way, memory accesses do not occupy the registers of the processor, and the operation of the information at address 1'1 is simplified and high performance is achieved. Can be executed at high speed.

Further, in the case of data transfer between specific blocks of the memory 5, the data transfer is facilitated by providing such an external address register for each block.

FIG. 5 shows another embodiment of the present invention, in which a full adder and two registers are provided in place of the counter register 21 of FIG. 3 to enhance functionality.

In the figure, 1 is a microprocessor, 2 is a data bus, 3 is an address bus, 4 is a control bus, 5 is a memory, 22 is a logic circuit equipped with an address decoder, etc., 25 is a multiplexer, 26 is an OR circuit, and 41 is its A full adder whose output is one input of the front multiplexer 25. C is an address register in which the start address of the memory 5 to be accessed is set. This register C
serves as a temporary address register while being accessed.

Reference numeral 43 is a register that specifies the step interval of the memory address to be accessed, and the contents of both registers 42 and 43 are input to the full adder 41. Further, the output of the full adder 41 is fed back to the register C. 44
are the output signals S, , S of the logic circuit 22.

This is an OR circuit that applies the signal to the register 42 as a control signal.

The input end of the register 43 is connected to the data bus 2, and a signal S1 and a load signal (line 23) are applied from the logic circuit 22 as control signals. Further, Fo is a flag indicating an overflow of the full adder 41.

In the case of such a circuit configuration, first the address of the memory 5 to be accessed (defined by the decoder of the logic circuit 22) is set in the register C. Next, the access interval of the memory to be accessed is set in the register 43. This set is 1 for sequential read/write.

In this state, when the processor 1 first reads/writes a specific address defined by the logic circuit 22, the logic circuit 22 gives the multiplexer 25 a signal S1 for selecting the output of the full adder 41, and at the same time, the OR circuit A read/write command is applied to the memory 5 through 26. At this time, processor 1 uses data bus 2.
The memory contents at the address (register 42) + (register 43) are input through the register. After this, predetermined processing is performed, and when this read/write cycle is completed, the signal S
When l disappears, the register signal at that edge becomes the output of the full adder 41, that is, (register 42)' + (register 4
3) Latch. This operation is repeated every cycle,
As a result, the contents of the register 42 will increase by the amount of the register 430 each time the memory 5 is read/written.

Having a memory block in which the step interval can be freely set and which can be raised or lowered in this way enables flexible memory access. This is effective for applications such as FFT (fast Fourier transform: memory access is performed in 2-step intervals).

Hiko, in each of the above embodiments, if the input on the address bus 3 side is selected by the multiplexer 25, normal memory access is performed.

As described above, according to the present invention, a multiplexer that provides a memory address and a specific address can be read/written for one block or multiple blocks of the memory of a microcomputer that is composed of a microb with a limited number of registers and a processor. We provided a so-called external address register consisting of a counter circuit that has an up-down function that automatically increases or decreases after the operation, and whose output is used as one input of the multiplexer.
It is possible to prevent registers inside the processor from being occupied by address information, and moreover, it is possible to efficiently process continuous data by increasing the execution speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a general microcomputer, FIG. 2 is a flowchart showing an example of a program for the same computer, and FIG. 3 is a block diagram showing an embodiment of the microcomputer according to the present invention. FIG. 4 is a flowchart for explaining the operation of the same embodiment, and FIG. 5 is a block diagram showing another embodiment of the present invention. l-φ・Microprocessor, 2... Cheetah/(S, 3... Address bus, 4... Hibiki control node (S), 51+1111 memory, 21-... Counter register, 22...φ logic circuit, 24...Flip-flop, 25...Multiplexer, 26 and 4411-Sound OR circuit, 41...Full adder, 42 and 43@...
register. Figure 1 Figure 2

Claims (1)

[Claims] (In a microcomputer consisting of a microprocessor, memory, etc. whose internal registers are registers that do not have auto-increment and auto-decrement functions, a multiplexer that provides a memory address for one or more blocks of the memory is used. It has an up-down function that automatically increases or decreases after reading/writing a specific address.
A microcomputer comprising a counter circuit whose output is used as one input of the multiplexer.