JPS62285152A - Data processor - Google Patents

Abstract

PURPOSE:To minimize the unused area of a built-in memory by dividing the area of said memory into plural pages and providing a function to each page to designate the application for instruction or data. CONSTITUTION:A group of instructions to be executed are stored in an external memory 603. The output 604 of a program counter 602 is outputted to the outside and an instruction is fetched by an internal instruction bus 106 from the memory 603. When this instruction designates an instruction or data of a memory area, the instruction code on the bus 106 is decoded by a decoder 601 and the outputs are sent to the control outputs 109a-109e of a control circuit 108a. Thus the pages of a memory 104 can be optionally designated for instructions or data. Therefore, the memory areas can be properly distributed for application even though the buses of both instruction and data systems are set independently of each other and the memory areas to store instructions are separated from those to store data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device having dedicated instruction and data buses, and particularly to a circuit suitable for efficient use of built-in memory. Regarding the method.

[Conventional technology]

Conventionally, microprocessors aimed at speeding up and parallelizing processing have been known to have separate buses for instructions and data. An example of the basic configuration of such a microprocessor is shown in FIG. In the figure, 501 is a data address pointer, 502 is a data storage memory, 503 is a program counter, and 504 is an instruction storage memory.

505 is an instruction decoder, 506 is a special operation unit such as a multiplier, 507 is an arithmetic and logic operation unit, 508 is a data address bus, and 5o9 is an instruction address bus.

510 is a data bus, 511 is an instruction bus, 512 is an accumulator register, 513 is an external input/output circuit,
514 indicates the outside.

As shown in Figure 5, in a microprocessor that has separate buses for data and instructions, data access and instruction access are performed simultaneously and parallelized to achieve high-speed processing. The memory area and the memory area for storing instructions are divided. Although FIG. 5 shows the memory area within the microprocessor, the configuration is similar when an external memory is used. From the perspective of improving processing speed, it is advantageous to have a built-in memory with short access time, but its capacity is limited by the size of the chip. Therefore, when a built-in memory is provided, the capacity ratio of the instruction memory area and data memory area is determined based on the system to which the integrated circuit chip is applied. However, the appropriate capacity ratio for a system is not so clear-cut, nor are the requirements of users uniform. As a result, there may be cases where one memory capacity is sufficient, but the other memory capacity is insufficient and the use of that semiconductor integrated circuit chip must be abandoned.

To avoid this situation, some conventional devices have a function that allows the capacity of the built-in memory to be expanded by using other external memory, but external memory has slower access times than built-in memory and requires less hardware. An increase in the number of parts is also inevitable. 1985IEEE Inte
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1), the built-in 2
There are semiconductor integrated circuit chips that have a mechanism in which one of the two memory areas is designated for data use and the other for data or instructions based on an instruction, but in this case as well, the latter memory is used for instructions. If specified, it is essentially the same as having fixed dedicated memory for instructions and data, and if specified for data,
Since the instruction memory is entirely dependent on external memory, it has a drawback in terms of improving operating speed.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional technology, the data area can be increased, but the increase in the instruction area is not considered, and when the data area is specified to be increased, the storage of instructions is completely dependent on the outside. . This leaves enough room for instructions and data, even for application systems that can store everything internally without relying on external memory by appropriately allocating the instruction and data areas of the built-in memory. However, there was a problem in that it required the use of external memory, which slowed down the operation speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system that can minimize the unused area of built-in memory produced by conventional methods and utilize it efficiently.

[Means for solving problems]

The present invention achieves the above object by dividing the built-in memory area into a plurality of pages and providing each page with a function of specifying whether it is for instructions or data.

[Effect]

Divide the built-in memory area into an appropriate number of pages for the semiconductor integrated circuit. As a result, the unused memory area becomes smaller than the capacity of one page at most, so the larger the number of pages divided into one, the less the unused area can be kept.

Further, by providing each page with a function of specifying whether it is for instructions or data, it is possible to prevent a large unused area from occurring in page units.

As a result, if the tUk of instructions and data is within the capacity of the built-in memory, it becomes possible to store all of them in a small amount by appropriate designated allocation for instructions and data. Furthermore, even if you want to capture just one or the other, you can do so flexibly as long as it is within the capacity of the entire built-in memory.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the figure, 101 is an address bus for instructions, 102 is an address bus for data, and 103 is an input 101, 1 according to the specification.
02, 104 is a memory area divided into n pages (n is 2 or more), 105 is 1
A bidirectional selector that selects either 06 or 107, 106 is an instruction bus, 107 is a data bus, 108 is 1
A control circuit 109 designates the selector of 03° 105, and is an input to 108. First of all, the operation when specifying instruction use and data use by an instruction will be explained using FIG. 6. FIG. 6 shows an example of a specific logic circuit at 103°, 105, and 108 in FIG. 1, and further includes other peripheral circuit blocks necessary for explanation. However, 1
08a represents the control circuit 108 for seven pages.

A group of instructions to be executed first is stored in an external memory, the output 604 of the program counter 602 is output to the outside, and the instructions are taken into the instruction bus 106 smaller than 603. When the instruction fetched from the outside is a memory area instruction/data specification instruction, the instruction code on 106 is decoded by the decoder 601 and 108a
Control outputs 109a, 109b, 109c, 109d
.

109e is output. Here, when 109a is "1",
109b indicates that this page among n pages is specified when it is "1"; 109c indicates that data is specified when it is "1"; When 109d is "1", the memory is in read mode, and when it is "0", it is in write mode*109
e is a clock synchronization signal. After the internal small memory is designated for instructions and data by the instruction fetched from the external instruction memory in this way, the internal small memory becomes available for use. After this, if the program is temporarily stopped and the instruction sequence is written in the internal small instruction memory, the program in the internal small memory can be executed by directly rewriting the jump instruction or the contents of the program counter. If necessary, necessary data may be written in the data memory at this time.

When specifying internal small memory for instructions and data, the specified pages do not necessarily have to be consecutive; in the instruction memory, the last step of the page is the page where the next instruction is stored. There is no problem if you write a jump command to the first address. In addition, in the case of data, there is no problem as long as the address range of the memory for data is confirmed.

This method requires steps to specify internal small memory for instructions and data using instructions from external memory, and then write the program to internal small instruction memory, but the specifications can be changed dynamically during operation. Therefore, by placing an instruction at an appropriate location in the program to re-designate an instruction memory area that is no longer needed midway into the data memory area, or vice versa, you can effectively reduce the amount of memory available. It becomes possible to expand the space.

Second, the operation when specifying internal memory for instructions and data using non-volatile elements will be explained with reference to FIG.

Figure 7 is the same as Figure 6, 103,105°10 of Figure 1.
8 is described as an example of a specific logic circuit, and other peripheral circuit blocks necessary for explanation are added. However, 108b represents the control circuit 108 for one page. 109d and 109e are also as explained in FIG.

First, before operation, input a command or data area from the outside using cuff 03. Using the page designation input cuff 04, the instruction and data designation control circuit 707 and its output cuff 08 are used to allocate each page to a control circuit 702 composed of non-volatile elements. In this case, once the designation is made, the designation information is retained even if the 1Ml source is turned off, so there is no need to designate it every time the power is turned on and started, which is convenient.

After the specification is completed, the required program is written in the instruction area, and if necessary, the necessary data is also written in the data area, and then the operation is started.

This method applies to a circuit composed of a small number of nonvolatile elements.
Although a process is required to write the necessary information, once written, the specified information is maintained even when the power is turned off, so the optimal instruction set and information for each semiconductor integrated circuit chip can be determined before shipping.
It is possible to provide a distributed memory area for data.

Alternatively, the user can freely set it according to the system. In addition, the program can be written to the instruction area of the built-in memory before starting operation.
Operation can be started from a program in built-in memory, and depending on the application, external memory may be completely unnecessary.

Referring to FIG. 8, the operation when specifying internal memory for instructions and data by direct input from an external pin will be described in FIG.

Figure 8 is also similar to Figures 6 and 7 at 103°10 of Figure 1.
5.108 is described as an example of a specific logic circuit, and other peripheral circuit blocks necessary for the explanation are added. However, 108c indicates a control circuit for one page. 109d and 109e are as explained in FIG. 6, and 701 is as explained in FIG.

In the case of FIG. 8, as in FIG. 7, first, before operation, commands and data are specified manually 802. Using the page designation input 803, instructions and data designations are distributed for each page via the command/data designation control circuit 801 and its outputs 804a, b, and c. Note that 804a is the designation output for commands. , 804b is a page designation output, and 804c is a data designation output. In this figure, once specified,
The information is held statically.

After the finger fixation is completed, the operation can be performed by following exactly the same number of steps as in the case of FIG. 7 above.

Since this method does not use non-volatile elements as shown in Figure 7, it is necessary to specify the instructions and data as described above each time the power is turned on, but the specification method is simpler than in Figure 7. Yes, it is possible to have an external host processor manage it and dynamically change the specifications.

In the above embodiment, the memory areas of all pages can be designated for instructions and data respectively, so depending on the application, all memory areas can be allocated for instructions or data, while the other uses external memory. However, while the conventional one has sufficient memory area, the other does not have enough area, and even though the entire application can be stored in the internal memory, it is sometimes abandoned or decided to use external memory. The situation of addition is eliminated.

FIG. 2 shows an embodiment in which a small internal memory is divided into three or more areas, and some of these areas can be designated for instructions and data. In the figure, 204a is a memory area dedicated to instructions;
4b is a memory area divided into n pages (n is 1 or more), and 204c is a memory area dedicated to data. Other parts are the same as in FIG. In addition, 204a, 204c
In this case, one or both of them may be dedicated memory for extraction.

In this embodiment, 204a and 20.4c are dedicated to instructions, respectively.
Since the area is for data only, there is no need to specify whether it is an area for instructions or data, and only the area 204b needs to be specified as an area for instructions or data. The operating method and the method for specifying instructions and data are the same as those in the embodiment shown in FIG. Since there is already an area dedicated to instructions in the diagram, start the operation at this 20
4 If you execute the command stored in area a,
An external memory as shown in FIG. 1 is not necessarily required. That is, it is possible to perform an operation procedure in which an instruction/data designation instruction for the area 204b is written in the area 204a, and after the instruction is executed, a predetermined program is written in the area 204b designated for the instruction.

The embodiment shown in FIG. 2 is a configuration suitable for applications where the approximate memory capacity required for instructions and data can be predicted and where a certain amount of memory is required. It has the advantage of being able to be kept to the minimum necessary.

Further, as mentioned earlier, even when instructions are specified for instructions and data, there is an advantage that the operation can be performed without relying on external memory. Note that both of the instruction-only and data-only memory areas shown in FIG. 2 are not necessarily required, and only one of them may be used.

FIG. 3 shows an example in which the instruction length and data length are different. In FIG. 1, 304a is a memory area dedicated to instructions;
04b is a memory area divided into n pages (n is 1 or more), 304c is a data-only memory area, and 305 selects either one of 106° and 107 according to an instruction, and writes to the word length of 304b at the appropriate time. On the other hand, when the bit length of the selected bus is short, it is a bidirectional selector that has the function of filling the extra bits of the word length with "0". The rest is the same as in Figure 1.

Although FIG. 3 is a diagram assuming that the instruction length is longer than the data length, it goes without saying that the opposite case may be used.

In the embodiment shown in FIG. 3, when all 304b are designated for instructions, the operating method and the method for specifying instructions and data are the same as in the embodiment shown in FIG. If there is an area designated for data in 304b, countermeasures are required when writing to and reading from memory. In Figure 3, a countermeasure is considered in which an "O" is inserted into the extra word length of the memory when writing, and the extra bits are not output when reading, but this is just an example. Not limited. For example, as another measure, it is also possible to effectively utilize this extra bit portion as an area for storing additional information other than the data itself. For example,
Possible solutions include the parity of error correction codes and the addition of index data necessary for data searches, data table references, and the like.

The embodiment shown in FIG. 3 shows that the present invention can be easily implemented even if the instruction length and data length are different in this way. Note that Figure 3 is a development of Figure 2, but
It is clear that a configuration such as that shown in FIG. 1 can be similarly developed.

Figure 4 shows an example of using programmable read-only memory in part of the memory area.
404a is a programmable read-only memory; 40
4b is a writable memory, 405 is 1 as an output light
Selector for selecting either 06 or 107, 41
0 is a circuit for erasing and rewriting the programmable read-only memory of 404a, 411 is a circuit for 410
is the input to Other parts are the same as in FIG.

Figure 4 is an expanded version of Figure 1, with n pages (n is 2
The above figure shows the case where two pages of the above) are replaced with a programmable read-only memory, but the number of pages to be replaced can be any number within n pages, and even the part 204b in Figure 2 Applicable. The embodiment shown in FIG.
404a.

The operating method other than 405 and the method of specifying instructions and data are the same as in FIG. 404a is 404b
Similarly, it can be designated for either instructions or data, but in the operating state it operates as a read-only memory, so 405 is a unidirectional selector. Writing to 404a can be performed through 410° and 411 using the same writing method as for a normal single programmable read-only memory chip.

The embodiment shown in FIG. 4 reduces the effort of writing instructions and data into a small internal memory each time the system is started, for applications that have fixed instruction routines and coefficient data that do not need to be changed much each time the system is started. It has the advantage of being

〔Effect of the invention〕

According to the present invention, even in a semiconductor integrated circuit in which instruction and data buses exist independently and the memory area for storing instructions and the memory area for storing data are separated, the memory area is divided into multiple pages. Since it is divided and each page can be arbitrarily specified as being for instructions or data, it is possible to allocate the memory area appropriately for the application, and the built-in memory area can be used efficiently.

In addition, even though the required instruction and data capacity is less than the internal memory, the conventional fixed memory area allocation may result in a situation where one side has enough room and the other side does not. Even for applications where it is not possible to store everything in a small amount of space, by specifying appropriate memory area allocation, everything can be stored in the built-in memory and high-speed operation can be achieved, which is a great effect.

[Brief explanation of drawings]

FIG. 1 shows the first embodiment of the present invention, and FIG. 2 shows the second embodiment of the present invention.
Example of Figure 3 is a third example developed from Figure 2,
Fig. 4 is a block diagram showing the configuration of the fourth embodiment, which is a development of Fig. 1, Fig. 5 is a conventional basic configuration diagram, and Fig. 6.7.8
The figure is a block diagram that takes out a part of FIG. 1 and describes each implementation method in more detail. 101.509...Instruction address bus, 102゜5
08...Address bus for data, 103...Selector of address bus, 104...Memory, 204a. 304a, 504... memory dedicated to instructions, 204c. 304c, 502-dedicated memory for data, 105°30
5.513...Bidirectional path selector, 4o5...Unidirectional path selector, 106,511...Instruction path, 1
07.510...Data bus, 404a...Programmable read-only memory, 707,801...
Command data designation control circuit, 108, 108a. 108b, 108c...Control circuits 109, 109a that output designated control signals for commands and data. 109b, 109c, 109d, 109e, 708°8
04 a, 804 b, 804 c - input to the control circuit, 410... circuit for writing to the programmable read-only memory, 411.
...Input to 410, 501...Data address
Pointer, 503, 602...program counter,
505.601,701--instruction decoder, 506-
... Multiplier, 507 ... Arithmetic logic operator, 512 ...
・Achimulator register, 705, 706...Specified output for instruction/data, 603, 703, 704゜80
2.803...External command input, 604...Program counter output, 702...Nonvolatile circuit,
708...Specified control output for instructions/data.

Claims (1)

[Claims] 1. In a data processing device having a memory for storing instructions and data, an address bus for the instruction memory, an address bus for the data memory, an instruction bus, and a data bus, a plurality of memory areas are provided. or divide the memory area into three or more areas, and specify whether each memory area is for storing instructions or data. A data processing device characterized in that it is possible to arbitrarily specify whether the device is for data storage. 2. The data processing device according to item 1, wherein designation of each of the divided memory areas for instructions and data is specified by an instruction. 3. The data processing device according to item 1, wherein the designation of each of the divided memory areas for instructions and data is realized by hardware using a nonvolatile semiconductor element. 4. The data processing device according to item 1, wherein designation of each of the divided memory areas for instructions and data is performed by direct input from an external pin.