KR960016397B1 - File storaging apparatus and information processing apparatus using the same - Google Patents

Abstract

No summary

Description

File storage device and information processing device using the same

1 is a block diagram showing a system configuration of an information processing apparatus for implementing the present invention.

2 is a block diagram showing a configuration of an embodiment of a file storage device.

3 is a block diagram of main parts for explaining the operation of the embodiment;

4 is an explanatory diagram showing data control when a memory chip having a slow write in the embodiment is used.

5A and 5B are explanatory diagrams of an embodiment of file storage in a memory in the embodiment.

6 is an explanatory diagram of an embodiment of chain information storage in another embodiment of the present invention.

7 is an explanatory diagram of a memory configuration example in which a data crushing function by signal terminal input designation is provided in a memory element.

Fig. 8 is an explanatory diagram of a memory configuration example in which a memory device has a data distribution function by command setting input designation.

9 is an explanatory diagram of address connection of a memory group in the embodiment.

10 is an explanatory diagram of an operation during simultaneous 4-byte write in the embodiment.

Fig. 11 is an explanatory diagram of the operation during four-byte simultaneous write in the embodiment.

Fig. 12 is an explanatory diagram of data distribution of memory one chip simultaneous access in the embodiment.

13 is an explanatory diagram of data distribution of memory two-chip simultaneous access in the embodiment.

14 is an explanatory diagram of data distribution of memory four-chip simultaneous access in the embodiment.

FIG. 15 is an explanatory diagram of a hardware configuration in various configurations of a system bus and a data bus of a memory. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus equipped with a file storage apparatus, and more particularly, to a file storage apparatus suitable for high speed file access and an information processing apparatus using the same.

In the current general-purpose information processing devices including personal computers, file storage devices are almost essential devices. In addition, it is common for the file storage device to be incorporated in the apparatus of the main body, and the user can always handle a large amount of files.

In recent years, notebook-size or palmtop-type personal computers have been used in many cases, and their use for mobile use has become important. For this reason, instead of the magnetic disk storage device, which is weak in vibration and consumes a lot of power, a file storage device using a semiconductor as a storage medium has attracted attention. For example, Japanese Patent Application Laid-open No. Hei 2-292798 discloses a technique of a semiconductor file memory device using a flash memory as a storage medium.

The flash memory is an electrically rewritable nonvolatile memory and is one of the most effective memories as a storage medium of a semiconductor file memory device because of its low cost and large capacity. The technique described in the Japanese Patent Laid-Open No. 1 has been researched to solve the problem of constructing a file memory device using this memory and to improve convenience in use. For example, a method for relieving a defect of a flash memory in which a device decreases due to frequent rewrite, and a method for speeding up an erase pose required for rewriting the flash memory are proposed. Moreover, the same interface as the magnetic disk device is proposed as an interface with the information processing device serving as a host, and an object thereof is to construct a system which can be replaced with the magnetic disk device.

The semiconductor file storage device of the related art uses an existing interface bus of an information processing device using the same, and emphasizes compatibility with a magnetic disk device. This allows the user to accept the semiconductor file memory device without resistance, but emphasizes compatibility with the magnetic disk device, but does not consider the use of the superiority of the semiconductor memory device over the magnetic disk.

For example, unlike a magnetic disk device that collects data from a rotating disk or writes data, the semiconductor memory device is a static storage medium, and thus enables very fast data access. There is a problem that can not take advantage of the fast access.

In addition, in the magnetic disk device used in an information processing apparatus such as a personal computer, the data access is slower than the memory access of the personal computer, and it is not necessary to operate in synchronization with the CPU in the information processing apparatus. Therefore, the data transfer of the magnetic disk device is executed on an asynchronous bus. In the case where the semiconductor is used as the storage medium, the CPU can be harvested. Therefore, the synchronous operation is meaningful.

At this time, however, a problem arises when trying to solve the difference between the bus width of the CPU processing and the bus width of the data access of one flash memory chip by using the memory chips in parallel. In the flash memory, the erase unit is determined, for example, 512 bytes. Therefore, when multiple chips are used in parallel, the capacity (512 x number of parallel chips) of an erase unit that executes an element at a time becomes bytes.

On the other hand, since most of the current personal computers use 512 bytes as one paragraph (one sector) as the storage capacity unit (hereinafter referred to as file management unit) of file management, for example, when accessing one sector as a file management unit, Attempting to use four flash memory chips in parallel results in a larger minimum erase unit, and simultaneously erases four times the capacity of one sector as described above when this sector is rewritten. This erases the data other than the erase target because the erase target capacity is too large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a file storage device and a file storing method which achieve both high-speed access performance and economy in an information processing device having a semiconductor file storage device.

Another object of the present invention is to provide a file storage device and a file storing method which do not affect other file data in a file device using a flash memory having a smallest erase unit.

Another object of the present invention is to miniaturize the file storage device.

Another object of the present invention is to dynamically change the file storage method and to effectively use the gap free area generated in the process of storing several files having various sizes.

The file apparatus according to the present invention stores file data via the data bus in parallel by using a memory device group having a minimum erase unit larger than the data bus width of the file memory and a data access width smaller than the data bus width of the file memory. A file storage device comprising: file dividing means for dividing file data consisting of one or more minimum memory units into combination elements consisting of a combination of arbitrary minimum storage units, and arbitrarily combining data on a data bus in units of data access widths; Data distribution means for corresponding to any combination of memory device groups of the same number of units in units of data access width, and any of the above arbitrary combinations of memory device groups when storing each of the combination elements in a file storage device. Control means for controlling the data distribution means so as to correspond to one set.

As a result, according to the present invention, an information processing apparatus equipped with a file memory device using a storage medium having a large minimum erase unit such as a flash memory can exhibit a high speed access function superior to that of a magnetic disk device. The ready signal input to the CPU of the information processing apparatus allows the CPU to be properly set in the standby state so that timing can be adjusted at high speed even when the data bus width of the system and the number of access data bits of one flash memory chip are different. .

In particular, a large capacity for which the access time is easy for a user to recognize is effective for read-write of a file, that is, continuous sector access. In addition, although the data bus width of the system and the number of access data bits of a single flash memory chip vary depending on the purpose, performance, and era, a highly flexible configuration that can cope with various things is possible. It can also be applied to a method of speeding up interleaving memory.

According to the file storage method using the above arrangement, the access procedure from the system is simplified to assist high speed access. And the file management itself can be simplified, simplifying control circuits and control programs.

In addition, by providing a data distribution function in the memory elements, peripheral circuits can be reduced and data processing can be speeded up.

According to the concept of the present invention as described above, in the flash memory device, multiple byte parallel simultaneous writes are performed while the memory storage area is effectively used without erasing other file data at the time of file rewriting. This makes it possible to achieve high speed file data storage.

EMBODIMENT OF THE INVENTION Hereinafter, the concept of this invention is demonstrated using drawing.

The following description assumes a personal computer as an information processing apparatus and a flash memory as a semiconductor storage medium.

In order to avoid the situation of erasing file data other than the object to be erased as described in the conventional example, for example, if the CPU is a 32-bit bus and the flash memory is an 8-bit bus, one chip is accessed four times in succession. For 32-bit buses, the CPU needs to support 32-bit buses.

However, in the case of continuous access of 4 sectors or more, each of the 4 sectors of data can be simultaneously accessed in parallel on four chips, and one access can simultaneously access 32 bits from the data bus of the CPU.

In file management, it is not usually possible to divide the processing once into consecutive sectors later. That is, the file system is accessed only file by file. Therefore, in the case of continuous access of several sectors, if multiple chips are used in parallel by simultaneously accessing multiple chips at the time of writing, file data as it is written can be obtained if the same parallel access is performed at read time. .

Here, the distributed storage states of two sectors and four sectors will be described with reference to FIGS. 10 and 11. FIG. 10 shows an example of 4-byte simultaneous writes, and FIG. 11 shows an example of 2-byte simultaneous writes. Here, the host system bus is 32 bits, and the data access width of one memory group is 8 bits.

FIG. 10 shows an example of four sectors simultaneous writing to four memory chips (referred to as memory groups according to the drawings) a to d. Reference numeral 212 in the figure shows data from the system bus of the host and is transmitted in units of 32 bits (4 bytes). Reference numerals 222 to 225 denote serial numbers of data in units of 8 bits (1 byte), reference numeral 222 denotes a first byte of data, reference numeral 223 denotes a second byte of data, and reference numeral 224 denotes a third byte of data. (225) is the fourth byte of data. Hereinafter, up to the 2048th byte is transmitted continuously for 4 sectors. In fact, since it is a 32-bit bus, the first to fourth bytes are simultaneously received. Reference numerals 51 to 54 denote data latches for data temporary storage. Since it is simultaneous writing in four bytes, 32-bit data, that is, four bytes are stored in the data latches 51 to 54 at the same time, and then each byte is divided into memory groups a to d and written one by one. Each byte is written to the subsequent part of the memory groups a to d for the next 32-bit data. In this manner, up to 512 bytes per sector are written in 128 divided sections. Subsequently, the second sector is written in the subsequent portions of the memory groups a to d by 4 bytes in the same manner. Similarly, 512 bytes of the third sector and 512 bytes of the fourth sector are written. At this point, the data of the minimum erasure unit of 4 chips is sufficient to the 2048-byte data. Therefore, at the time of rewriting this file, the capacity for these four sectors is collectively erased so that there is no problem.

As described above, in practice, data of each sector is not only stored in a specific memory group but is distributed and written to memory groups a to d. However, the data of all four sectors is stored in an area corresponding to four sectors of the memory groups a to d.

In this way, the file is repeated four sector parallel access by four sectors simultaneously. If there is less than 4 sectors last, or if a file is less than 4 sectors from the beginning, it is executed as follows.

In the case of 3 sectors, 32 bits of the CPU cannot be divided by 3, so it is divided into 2 sectors and 1 sector.

The case of two sectors will be described with reference to FIG. 11 shows an example of two-byte simultaneous writes to memory group a and memory group b.

Simultaneous write by two bytes, 32-bit data, i.e., four bytes are stored in data latches 51 to 54 at the same time, and then divided into two bytes so that the first two bytes of memory group a and memory group b first. The second two bytes are written one by one into the memory group a and the memory group b. In this manner, up to 512 bytes per sector are divided into 256 times. Subsequently, the first byte of the second sector is similarly written to the subsequent part of the memory groups a and b in 256.

Although not shown in one sector, 32 bits of data from the CPU are divided into four, and one chip is accessed 8 bits at a time. 512 bytes of one sector are divided into 512 times and stored in one sector of a chip.

As described above, the access speed can be increased by changing the access method to the flash memory according to the number of sectors continuously accessed. In addition, the problem of erasing due to the flat memory can be solved by changing the storage method of the data. That is, in any storage method, it is guaranteed that only data of the same file is stored in the minimum erase area of one chip, thereby eliminating the above-described problem caused by erasing the flash memory.

In the present invention, the flash memory is synchronously operated with the CPU, but a delay occurs due to the access type. This problem corresponds to arbitrarily requesting a standby state from the CPU by using the one in the ready signal input to the CPU. CPUs with ready signal inputs are now common. For example, the CPU which is installed in the general-purpose personal computer of today is provided with all the CPUs of 16-bit processing or more of INTEL company which are the most common. By negating this ready signal, the CPU stops processing cycles. Therefore, if the read and write of access data is not completed, it is only necessary to negate this signal. Intervenes in the execution. These are the controls that enable the file storage device to be synchronized with the CPU so that it is essential to input the synchronized clocks in both directions to perform the synchronous operation. By these controls, when the data width in one processing differs between the CPU and the flash memory, the CPU can be easily responded by waiting the CPU until the data width matches.

Next, the detailed Example in this invention is described using drawing.

First, Fig. 1 shows the installation of the flash memory file storage device of the present invention in the configuration of a standard personal computer. In the figure, (1) is a CPU in charge of processing data and programs, and the data bus width is 32 bits. (2) is a clock generator that generates a synchronous clock of the entire system. (3) is a shared bus inside the system, which includes a data bus, an address bus, memory commands, and IO commands, and is collectively referred to as a system bus. (4) is a file control circuit which realizes file management and memory control of the flash memory file storage device of the present invention. Denoted at 5 is a flash memory array serving as a storage medium of the flash memory file storage device, and the number of access data bits of one memory chip is 8 bits. The flash memory file storage device is constituted by the file control circuit 4 and the flash memory array 5. (6) is a main memory control circuit for managing and controlling the main memory of the system. (7) uses DRAM as main memory. (8) is a circuit for controlling the peripheral IO bus, and as one of the peripheral IO devices, the display control circuit 9, the communication device 11, the large capacity external storage device 12, and the like are connected. The display device 10 is connected to the display control circuit 9.

Normally, other clock generators are built into the peripheral IO control circuit 8, and these peripheral IO devices operate in accordance with the clock cycle. However, it is also contemplated to operate directly with the CPU 1 by connecting directly to the internal system bus 3 for speed. Reference numeral 13 denotes a clock signal supplied to each circuit including the CPU 1 in order to synchronize the circuit connected to the internal system bus 3. However, it does not need to be the same as the clock given to the CPU 1, and depending on the circuit, even if divided, it may be synchronized.

Numeral 14 denotes a ready control signal input to the CPU 1 and collectively inputs the status indication signal output from each circuit to the CPU 1 in the ready control signal 15. Numeral 16 denotes a control circuit of an input device for instructing a process desired by the user of this system, and numeral 17 denotes an input device. In the figure, the input device 17 is a keyboard, and the control circuit 16 is a keyboard controller KBDC.

Next, the operation of the system of FIG. 1 will be described. In normal operation, the CPU 1 calculates and processes a program or data stored in the main memory 7 so as to execute a process instructed by the input device 17 from the user, and the result is displayed on the display device 10. Display. In addition, if necessary, the communication device 11 is operated, or the large capacity external memory device 12 stores the large data. When the file is taken out or stored, the file control circuit 4 is operated. When the system is running, the system program is loaded from here. In these operations, when the clock generator 2 generates a synchronous operation by the clock signal 13 generated and a circuit needs to wait for the CPU 1, the circuit sends the CPU to the ready control signal 15 to the CPU. A request is made to wait, and it is transmitted to the CPU 1 by the negate of the ready control signal 14. The CPU 1 continues to wait until the ready control signal 14 is asserted again. At this time, the file control circuit 4 is capable of executing control for increasing or decreasing the CPU waiting time by the number of files required for the CPU 1. This configuration will be described with reference to FIG.

2 is a diagram for explaining an internal configuration of a flash memory file storage device. In the figure, (3), (4), (5), and (13) are the same as those of the first diagram, and the following are the internal components of the file control circuit 4.

Denoted at 21 is a register group (I / F register group) for performing interface with the system bus 3, and reference numeral 22 denotes a status register for reporting the status of the file control circuit 4 to the CPU 1; 23 is a start sector register for setting the first sector number to be accessed, 24 is an end sector register for setting the last sector number to be accessed, and 25 is a command code for processing required by the CPU 1. The command register, 26, is a data register which executes data transfer with the system bus. Reference numeral 27 denotes a controller that oversees the internal control of the file control circuit 4, and a programmable intelligent LSI such as a one-chip microcomputer is ideal. Numeral 28 denotes a memory control circuit which executes control of the flash memory array 5 which is a storage medium, and numeral 29 denotes a data control circuit which performs control of data to be written to or read from the flash memory array 5. Numeral 30 denotes a DMA control circuit for executing memory access at high speed, and the clock signal 13 of the system is input to the present circuit. Denoted at 31 is a status indication signal outputted as a ready control signal 15, at 32 is a local bus in the flash memory file storage device, and at 33 is a control signal and address for accessing the flash memory.

Next, the operation of the flash memory file storage device of FIG. 2 will be described.

The CPU 1 executes access via the system bus 3 when the need for access to the flash memory file storage occurs. First, the contents of the status register 22 are read to see if the situation is accessible. The sector to be accessed next is set in the start sector register 23 and the end sector register 24. The command code (lead or write) of the requested access is then written to the command register 25. When the status register 22 is read and accessible again, the data register 26 writes or reads the data to the data register 26.

At this time, the controller 27 executes management of these interface register groups 21 so as to comply with the request from the CPU 1. That is, the start sector register 23, the end sector register 24, and the command register 25 are read to grasp the contents of the access to the flash memory array 5, and the code indicating the current state is written to the status register 22. Report to the CPU 1.

When writing or reading data, it is considered that the operation speed is slow when the controller directly accesses the flash memory because the access request from the CPU 1 is considered. Therefore, the flash memory access is executed by the DMA control circuit 30 at high speed. In this case, the data is transmitted to and received from the system bus 3. The controller 27 executes the setting of the contents of access to the DMA control circuit 30 and the memory control circuit 28 and the DMA activation.

The DMA control circuit 30 executes address generation and timing generation for executing DMA, and the memory control circuit 28 generates an access signal in accordance with the timing. The flash memory array 5 executes the data control circuit 29 and data transfer based on these input signals. The data control circuit 29 generates data in accordance with the number of sectors of the access.

For example, in the case of one sector write access, the data transmitted by the single access from the system bus 3 is matched to the number of write bits of one chip of the flash memory array 5. In this embodiment, since the data bus width of the system bus 3 is 32 bits, 32-bit data is obtained by transmission by one access. Since the data width of one flash memory chip is 8 bits, the transferred data is divided into four times and written to the flash memory array 5. Therefore, the data control circuit 29 executes the process of dividing the 32-bit data into four 8-bit data using the latch circuit. On the contrary, if one sector of read access is performed, the flash memory array 5 is read accessed four times to prepare 32-bit data for one bus transfer. The waiting time of the system bus 3 generated at this time is caused by a waiting request to the CPU 1 by the state control signal 31 generated by the data control circuit 29.

On the other hand, in the case of an access of several sectors, the data control circuit 29 adjusts the data latched to speed up the access and execute it normally. For example, in the case of four sectors of continuous read access, 32-bit data is accessed at high speed by simultaneously reading four chips of 8-bit access flash memory. As described above, four-chip simultaneous write access needs to be executed at the time of writing to the flash memory array 5. Otherwise, the order of the data will be different and the file will not be normal. However, in a file storage system, it is common to execute management on a file basis. Therefore, read access of the same sector number of the sector number at the time of writing is common. If you do the same in, you do not need to record the above remarks.

That is, for example, when five sectors are continuously written, the first four sectors are simultaneously written in parallel on four chips, and the remaining one sector is stored in one chip. If the access type is adopted and the read is carried out as well, the normal file data can always be accessed. In addition, information of the data storage format may be recorded in sector data stored in the flash memory array 5. If there is a redundant data storage area other than the data storage area in the flash memory, it is appropriate to store it there. If there is no redundant area, another storage area is provided and recorded.

In the case of continuous access of 6 sectors, processing is performed by parallel access of 4 sectors and parallel access of 2 sectors.

Next, these access signals and data control methods will be described in more detail with reference to FIG.

FIG. 3 shows the configuration when the system bus is 32 bits and the flash memory is 8 bits. In the figure, the reference number is the same as described so far. Reference numeral 41 denotes a counter for generating an address of the DMA control circuit 30. Although not shown in FIG. 2, an IO access (command) signal or a memory access (command) of the clock signal 13 or the system bus 3 is shown. The signal is input and the counter is counted up in synchronization with this. Reference numeral 42 denotes a start register for DMA control to which the local bus 32 of the controller 27 is connected, and the desired DMA transfer can be started by writing a code to this register. Reference numeral 43 is also a sector register connected to the local bus 32, and the DMA transfer of any sector number can be executed by writing the sector number to be accessed. In actual operation, the write value of this sector number is input to the memory control circuit 28 and used for generation of the upper address of the flash memory or the chip select signal.

Reference numeral 44 denotes a timing control circuit which generates timing signals for synchronizing with each control circuit during DMA transfer. Reference numeral 45 denotes a memory address generated by the memory control circuit 28 in accordance with the values of the counter 41 and the sector register 43. Reference numeral 46 denotes a memory control signal generated in accordance with the occurrence of the memory address 45.

(51), (52), (53), and (54) are data latches of one byte (8 bits), respectively, and data width conversion between 32-bit data and 8-bit data in the data control circuit 29 is performed. It consists of 4 bytes (32 bits) of data latch. When the data of the system bus 3 is D0 to D31, the latch 51 is D0 to D7, the latch 52 is D8 to D15, the latch 53 is D16 to D23, and the latch 54 is D24 to D31. Latches each. Reference numeral 55 denotes a latch signal generation circuit for these data latches. Reference numeral 56 denotes a data width control setting register which is connected to the local bus 32 and sets the data width and the data sorting method. In this embodiment,? Is read access to the data width control setting register 56 in the present embodiment. ? By setting any of " 1 ", " 2 ", " 4 "as the number of consecutive access sectors of?, The latch signal generation circuit 55 instructs the latch signal generation circuit and its timing. The latch signals input to the data latches 51, 52, 53, and 54 are (57), (58), (59), and (60), respectively. For example, if " 1 " is set, the latch signals 57, 58, 59, and 60 are sequentially output one by one, and data from one chip of flash memory is accessed four times, and the 32-bit Generates data and outputs it to the system bus (3). When " 2 " is set, the latch signals 57 and 58 are output simultaneously, and then the latch signals 59 and 60 are simultaneously outputted alternately. The data from the two-chip flash memory is accessed twice, and 32-bit data is generated and output to the system bus 3. If "4" is set, the system simultaneously outputs the latch signals 57, 58, 59, and 60, and accesses data from the 4-chip flash memo only once to generate 32-bit data. Output to bus (3).

On the other hand, during write access, latch signals are simultaneously sent to the data latches 51, 52, 53, and 54 to latch 32-bit data from the system at once. Reference numeral 61 denotes a data distribution circuit for distributing data stored in the data latches 51, 52, 53, and 54 or data from the memory 5. Reference numeral 62 denotes a 32-bit data bus connecting the flash memory array 5 and the data distribution circuit 61 to each other. Reference numeral 63 denotes a read / write signal for determining the direction of data of the data distribution circuit 61, and is preferably supplied from the command register 25 of the interface register 21 or the like.

The data distribution circuit 61 is a bidirectional buffer, one of which is connected to the data latches 51, 52, 53, and 54, and the other of which is connected to the flash memory array 5. . On the flash memory array 5 side, 32 bits are input, and the entire chip of the flash memory array 5 is divided into four sets of memory groups and the other groups of bits (bits 0 to 7) (bits 8 to 15) ( Bits 16 to 23 (bits 24 to 31) are allocated and input as 32 bits. The direction is determined by reads or writes, and distribution of each data is determined in accordance with the setting contents of the data width control setting register 56.

The distribution of this data will be described in detail with reference to FIGS. 12, 13, and 14. These figures show the data distribution string of the data distribution circuit 61 for each setting value of the data width control setting register 56. FIG. 12 shows the data distribution in the case where the number of consecutive access sectors is 1, the number of consecutive access sectors is 2, and the number of consecutive access sectors is 4 in FIG. 13, and which four memory groups are accessed in each case. There are four types of data distribution. Lead lights are also shown separately. If the number of consecutive access sectors is 1, one access is made in four system cycles. If the number of consecutive access sectors is two, one access is made in two system cycles. If the number of consecutive access sectors is four, one access is made in one system cycle. It becomes

If the number of consecutive access sectors is 1, it is divided into four types according to which memory is divided into four, and if the number of consecutive accesses is 2 and 4, it is also divided into four types depending on which memory group is the starting point. . That is, the origin can be appropriately determined by the usage of the memory, and the memory group used can be prevented from being biased to one side. For example, if the memory group 1 is always used as a starting point, the data distribution method can be simplified, but the memory group 1 is used at a higher rate, so that the amount of usage and the frequency of use are expected to be skewed. When the shift occurs, one memory group cannot be used finally, and fast write access with 4 consecutive sectors becomes impossible. Thus, the origin can be set in all memory groups.

In the reads having 1 or 2 consecutive sectors, the data wirings of the distribution circuits are separately set for each cycle in the drawing. However, since the latch signals are not output except for the desired latches, they are not divided in each cycle. You can do the wiring together. In other words, in the read of A having the number of consecutive sectors 1 (Fig. 12), the distribution is transferred to the latch 1-memory group 1, the latch 2-memory group 1, the latch 3-memory group 1, and the latch 4-memory group 1 in sequential cycles. However, the wiring to all latches may be connected to one of the memory groups in every cycle. This is because even if data is connected, it does not affect the output unless the latch signal is output.

In addition, for example, in the write access of one sector, as shown in FIG. 12, the bit group connected to one of the flash memory groups to be accessed in the 32-bit data bus 62 is shown. In the first time, in the data latch 51, in the second time, in the data latch 52, in the third time, in the data latch 53, in the fourth time, in the data latch 54, in the following (51), the data is repeated. Take the light and run it. In the read, data is distributed to each latch one cycle by the latch signal, and 32-bit data is aligned.

In the 2-sector write access, that is, if the data width is 2 bytes, as shown in FIG. 13, 1 for each of the two bit groups connected to the corresponding two memory groups in the 32-bit data bus 62 is shown. In the first access, data is received from the data latches 51 and 52, and in the second access, the data is received from the 53 and 54, and then alternately distributed. On the other hand, in the read access, the directions are reversed, and data is distributed to the data latches 51 and 52 in the first access, and to 53 and 54 in the second access in the corresponding two memory groups. Repeat this.

4 sector write access, i.e., 4 bytes of data width, 32-bit data bus 62 has data latches 51, 52, 53, and 54 in order from the memory group corresponding to the head. 32-bit access is terminated in one cycle of access. In the lead, the direction is reversed.

In order to perform the above operation, the controller 27 sets an appropriate value to the registers described above before starting the DMA control circuit 30.

As described above for speeding up, when accessing several memory groups simultaneously, the addresses given to the respective memory groups are examined with reference to FIGS. 5A and 5B below.

In FIGS. 5A and 5B, 81 to 84 represent memory groups 1 to 4, respectively. Fig. 5A shows a state in which a certain amount of files have been written, and Fig. 5B shows a state in which a file is updated after that and its file capacity has increased. In the illustrated data symbol (m-n), m is a file number and n is a sector number that stores each file. For example, (3-2) represents the second sector of file number three. However, this figure collectively shows how the memory group area (having the capacity for one sector) is used for one or more sectors of each file. Not only the contents of a single sector are stored in one sector capacity area of the memory group, but the contents of several sectors are distributed and stored. This will be described in detail later in the description of file management.

In FIG. 5A, the same addresses are assigned to the respective memory groups because they are listed in the same column for the simultaneous access of the file number 1 (all sectors denoted by 1-n) from 1-1 to 1-4. You can give it. However, in the file number 2, when 2-1 to 2-4 are used for simultaneous access, the memory group 4 needs to be given an address different from the other memory groups. This means that the address bus needs to be provided as many as the number of memories. Or a method of giving a different address to the memory group. Therefore, in order to avoid this, it is necessary to take an access form in which file number 2 is accessed by 2-1 alone, 2-2 and 2-3 are accessed simultaneously, and 2-4 is accessed again by itself. . However, this generates waste in speeding up. Thus, a configuration example of giving another address will be described with reference to FIG.

9 is a configuration example of an address generation circuit in the memory control circuit 28 when the memory group is four. In the figure, reference numerals 201 to 204 denote four memory groups constituting the flash memory array 5, reference numeral 201 denotes a first memory group a and reference numeral 202 denotes a second memory group b, (203). ) Is the third memory group c, and 204 is the fourth memory group d. 205 denotes a latch circuit b of an upper address assigned to the memory group b, 206 denotes a latch circuit c of an upper address assigned to the memory group c, and 207 a latch circuit d of an upper address assigned to the memory group d. to be. Reference numeral 208 denotes an address bus (corresponding to 45 in FIG. 3) of the memory control circuit 28, and 209 denotes a lower address of the address bus 208. The number of address bits is the number of address bits corresponding to accessing the storage capacity of the minimum data erasing unit of the flash memory chip or the minimum unit of file management. For example, if the data erasing minimum unit is 512 bytes, it is 9 bits. When the minimum unit of data erasure of the flash memory chip is less than or equal to the minimum unit of file management, it is effective to set the number of address bits corresponding to the minimum unit of file management. Reference numeral 210 denotes an upper address except the lower address 209 of the address bus 208. However, the upper address unnecessary to access the memory group is excluded. Reference numeral 211 denotes an upper address stored in address latch b to access memory group b, 212 an upper address stored in address latch c to access memory group c, and 213 accesses memory group d. Is the upper address stored in the address latch d. Reference numeral 214 denotes a memory control signal of the memory group a 201, 215 denotes a memory control signal of the memory group b 202, 216 denotes a memory control signal of the memory group c 203, and 217 denotes a memory. This is a memory control signal of group d (204).

In the configuration of FIG. 9, when accessing the memory group a to the memory group d simultaneously, the upper address for accessing each memory group is written in the address latches 205 to 207 in advance. When the access is executed, since the lower address 209 is common to all the memory groups, the address bus supplies an address for accessing only the memory group a, and memory groups other than the memory group a are the upper addresses in the corresponding address latch circuit. Access is performed by The control of the access is left to the memory control signals 214 to 217. For example, if only the memory group a and the memory group d are accessed, only the memory control signals 214 and 215 are made active. For example, in accessing only the memory group d, no address may be given to the memory group a unless the memory control signal 214 is activated. As a result, it is possible to give different addresses to each memory group. If even the memory groups are distributed into four groups, data of the same file stored in different physical locations can be accessed at the same time, thereby increasing the contribution of speeding up. Can be. Although the structure of FIG. 9 is omitted to simplify the address latch of the memory group a, of course, if it is effective to provide the address latch in the memory group a, it may be so.

According to the above embodiment, the CPU 1 can access the read / write access of the desired sector at high speed by performing simple designation to a relatively few registers. By using the file controller as a single-chip microcomputer, fine control can be instructed by software, and by incorporating a DMA transfer control circuit, data transfer can be performed at high speed even if the single-chip microcomputer can only operate later than the system. . However, if the operation speed of the one-chip microcomputer can be sufficiently harvested for the system, a configuration in which the one-chip microcomputer performs all data transfers without the DMA control circuit is also considered.

In the present embodiment, the data bus is described as 32 bits system and 8 bits flash memory. However, the number of data latches is also used for the 16-bit CPU 1, the 64-bit CPU, and the 16-bit I / O flash memory. By changing the configuration of the data width control setting register, the control program of the controller, etc., it is possible to easily cope with different data widths. A specific example is shown in FIG. 15 shows specific numerical values of the hardware configuration in each bit width combination. The horizontal direction in the table is the number of bits of data in the flash memory, and 4, 8, 16, and 32 bits are given as examples. The vertical direction represents the data width of the system and is from the 8 bits of a simple information processing device to the 16 or 32 bits that are the mainstream of current personal computers and the 64 and 128 bits of future personal computers or high performance computers. Indicates. In addition, the data distribution circuit held as a hardware configuration shows (the number of data bits distributed by one distribution circuit) x (the number of configurations of the distribution circuit), and is explained by the data distribution circuit 61 of the embodiment. The number represents data distributed by one distribution circuit, and the number of circles indicates the number of configurations of the distribution circuit. Connection of each distribution circuit can be represented by the same concept as FIG. 12 to FIG. The number of latches is an increase or decrease in the number of latches 51 to 54 in the embodiment. However, when the number of memory data bits is larger than the system data width, the position of the latch is configured on the memory side of the data distribution circuit. In the embodiment, the memory group indicates the number of divisions of the memory divided into four.

However, the number of distributions, the number of latches, and the number of memory groups of the data distribution circuit including the present embodiment are the minimum number, and if there is room in the circuit size, the number of terminals, or the like, the system configuration can be increased by increasing the number.

This is because the increase in the memory group makes it possible to select a storage memory for data, and thus, the bias of the memory usage and the frequency of use as described above can be further prevented. In addition, since the number of parallel access memories can be increased, the speed can be further promoted. In particular, in the case where the system data width and the number of memory data bits are the same or the number of data bits in the memory are large, there is no effect of matching the data bus width as described in the embodiment, but the speed is increased by the so-called interleaving method by accessing multiple memory chips simultaneously. Can be realized. At this time, it is necessary to simultaneously increase the number of distributions and latches of data in the memory in the data distribution circuit by increasing the number of memory groups.

In this embodiment, the flash memory is described as being able to harvest data from the system, but for this purpose, it is preferable to mount a light buffer in the flash memory. In the future, when a flash memory capable of writing light at high speed is realized, such a light buffer is unnecessary. If a light buffer is not built in the flash memory, the light buffer can be installed between the flash memory and the data control circuit. When the write access is performed, the write buffer is executed without writing directly to the flash memory. After the data transfer from the system is finished, the write buffer is executed from the write buffer to the flash memory. The structural diagram of the Example in this case is shown in FIG.

During the fourth, the exit number is the same as described so far. Reference numeral 71 denotes a data selector for switching the connection with the data distribution circuit 61 according to whether the access is read or write, 72 denotes a light buffer having a data bus width such as a CPU bus width that temporarily stores write data; Reference numeral 73 denotes a read / write signal for switching the data selector 71, and may be generated by the command code written in the command register 25. If the access is a write, the data distribution circuit 61 is connected to the write buffer 72, the write data is stored in the write buffer 72, and after data transfer from the system, the controller writes the write to the flash memory array 5. Run If it is a read, the data distribution circuit 61 is directly connected to the flash memory array 5, and the same operation as that of the read access of FIG. 3 described above is executed.

With the above configuration, even if a flash memory having a slow light is used without a built-in light buffer, fast access is possible when viewed from the system.

Next, as an example of file management, description will be made with reference to FIGS. 5A and 5B. Although the embodiment of the hardware configuration has been described so far, the following describes how to actually store it in the flash memory. Basically, this operation is executed by the CPU of the system, the controller of the system program and the flash memory file, and the operation by software is the main focus. In the description of Figs. 5A and 5B, the contents of the memory capacity of each memory group of the flash memory are not allotted to the sector of the file as a result of the operation, but as a result of the operation. Indicates whether or not. A unit capacity area is secured in the memory group sequentially for each sector of the file. For four or more consecutive sectors, one unit capacity area of memory groups 1 to 4 is sequentially allocated to four sectors (for example, 1-1 to 1-4 in the figure). In practice, however, data in each of these sectors is distributed and stored in four unit capacity areas. For two sectors (for example, 1-5 to 1-6 in the figure), unit capacity areas of two memory groups are allocated. Also in this case, data of each sector is distributed and stored in two unit capacity areas. The last sector 17 of the file 1 is allocated a unit capacity area of a single memory group.

Here, the distributed storage states of two sectors and four sectors will be described in more detail with reference to FIGS. 10 and 11. FIG. 10 shows an example of 4-byte simultaneous writes, and FIG. 11 shows an example of 2-byte simultaneous writes. As described above, the host system bus is 32 bits, and the data access width of one memory group is 8 bits.

10 shows an example of four sectors simultaneous writing to the memory groups a to d. In the figure, reference numeral 221 denotes data from the system bus of the host, and is transmitted in units of 32 bits (4 bytes). Reference numerals 222 to 225 denote serial numbers of data in units of 8 bits (1 byte), 222 denotes the first byte of data, 223 denotes the second byte of data, and 224 denotes three bytes. Second, 225 is the fourth byte of data. Hereinafter, up to the 2048th byte is transmitted continuously for 4 sectors. In fact, since it is a 32-bit bus, the first to fourth bytes are simultaneously received, and the same applies to the following. Reference numerals 51 to 54 denote data latches for data temporary storage shown in FIG.

Since simultaneous writing is performed by four bytes, 32-bit data, that is, four bytes are simultaneously stored in the data latches 51 to 54, and then each byte is divided into memory groups a to d and written one by one. Each byte is written to the subsequent part of memory groups a to d for the next 32-bit data. In this manner, when the 512-byte portion for one sector is written, the second sector is successively written to the subsequent portions of the memory groups a to d by 4 bytes in the same manner. In FIG. 5, for convenience, each sector is assigned to a specific memory group. However, as described above, data of each sector is not stored only in a specific memory group, but is distributed and written to memory groups a to d. However, data of all four sectors is stored in four sectors of the memory groups a to d.

11 shows an example of two-byte simultaneous writes to the memory group a and the memory group b.

Simultaneous write by two bytes, 32-bit data, that is, four bytes, are simultaneously stored in the data latches 51 to 54, and then divided into two bytes so that the first two bytes are first stored in the memory group a and the memory group b. One byte is written, and the second two bytes are written one byte into the memory group a and the memory group b. In this manner, when the data is written up to the 512 byte for one sector, the data is written to the subsequent portions of the memory groups a and b in the same manner from the first byte of the second sector. Also in this case, the first sector is not stored only in a specific memory group, but is divided and written into the memory groups a and b, and similarly, the second sector is distributed and written into the memory groups a and b following the first sector. Although writing of a single sector is not shown, in this case, each byte data of the data latches 51 to 54 are sequentially stored in any one memory group. Only in this case, one sector of data is stored in a specific memory group without being distributed.

As can be seen from the above, it is important to note that as a result of the above operation, no other file data is mixed in the area of the minimum erase unit (here, 512 bytes corresponding to one sector capacity) of the flash memory element. This guarantees that high-speed file data storage can be achieved by multiple byte-parallel simultaneous writes without effectively erasing data of other files at the time of file rewriting and also effectively using the storage area of the memory.

As described above, Fig. 5A shows a state in which a certain amount of files have been written, while Fig. 5B shows a state in which a file is updated later and the file capacity has increased. In FIG. 5A, different memories are allocated in order of file numbers and sector numbers. In principle, there should be no empty space so as not to waste management.

As shown in FIG. 5B, when the sectors of a file are sequentially filled and stored so that no space is created in the memory group, when the file capacity is increased due to file updating, it is shown in FIG. As described above, there are cases where the physical storage location cannot be stored continuously. Even in such a case, the memory groups are stored so as to be contiguous. That is, if file number 4 is taken as an example, 5 sectors of 4-1 to 4-5 are stored in FIG. 5A, but if 2 sectors are added in FIG. 5B, 4-1 is stored in memory group 3. Since it is disclosed, the increments of 4-6 and 4-7 ensure the areas of the memory groups 2 and 3. When writing a file with an increased number of sectors, 4-5 and 4-6 are treated as two sector consecutive sectors, and 4-7 is treated as a single sector. In other words, the additional sector is also treated as a continuous sector together with the already stored sector. In order to facilitate the storage and reading of these file managements, the designation of access sectors from the system as the hardware configuration may be the starting sector and the number of sectors, and the physical storage location may be determined inside the file system. At this time, the end sector register 24 shown in FIG. 2 is unnecessary. If there is a redundant area for storing information other than the data in the memory, if there is a redundant area for storing information other than the data in the memory, and if there is a start number of the file, the physical position of the sector number subsequent to the file is concatenated. As it becomes clear in general, continuous access is possible.

6 shows an example of chain information. In the figure, reference numeral 85 denotes a file storing data which is stored, and data of file number 4 and sector number 5. Reference numeral 86 is data of a file number 4 and a sector number 6 subsequent to it. Reference numeral 87 denotes data of the file number 4 and the sector number 7 following it. However, these data have sector numbers in order, but they may be mixed in the actual storage state. That is, data may be scrambled and stored by accessing several chips simultaneously by continuous sector access. However, even in this case, it is necessary to attach the order of storing data for each byte, so the sector number is very important. Numeral 88 denotes a physical address indicating a physical position on the memory where the file storage data 85 is stored, the number "3" on the left is a memory group number, and the number "5" on the right is an address in the memory group. Reference numerals 89 and 90 are similarly the physical addresses of the file storage data 86 and the file storage data 87. Reference numeral 91 denotes chain information indicating a physical address where the next sector of the file storage data 85 is stored. Since the file storage data 85 is data of the file number 4 and the sector number 5, the chain information 91 The physical address where the data of the file number 4 and the sector number 6 is stored is shown. The numbers on the left are the memory group numbers, and the numbers on the right are the addresses in the memory group. Similarly, the concatenation information 92 indicates a physical address where data of the file number 4 and the sector number 7 are stored, and the concatenation information 93 indicates this case without the next sector. That is, it can be seen that the file of file number 4 ends in seven sectors.

If this chaining information is attached to the file data, the system's CPU does not need to know the physical location of the file store, but can simply take the form of accessing the file itself. By performing the physical access of the memory while the file control controller refers to the chain information, the continuous access is possible even for a single file and a file in which the physical storage locations are not contiguous but distributed. At that time, a configuration for inputting different addresses for simultaneous access of different memory groups is necessary. However, as described above in FIG. 9, the lower address for one sector access can be shared, and only the upper address of the sector or more is sufficient. As described above, according to the embodiment using the chain information, the access designation from the system can be simplified and can be implemented with a small amount of information.

Next, an embodiment in which various functions are incorporated into the memory element itself will be described.

7 is a configuration diagram of a memory device in which several memory chips of a memory array are housed in one package and additional circuits are provided therein. In the figure, reference numeral 101 denotes a memory element, 102-105 are memory chips having the same function, and 106-109 are input / output data terminals of the memory package 101, each one being one. Data input / output of two memory chips is possible. For example, if the memory chip 102 has 8 bits of data input / output, all of the bits 106 through 109 have data bits of 8 bits x 4 = 32 bits. Reference numeral 110 denotes a signal input terminal for specifying a path for connecting these memory chips and input / output terminals, 111 denotes a designated signal, and 112 denotes a focus path setting circuit. The user of this memory element 101 executes the setting of the data input / output terminals 106 to 109 by the signal input terminal 110 and then accesses it. In this setting, the selection in connection paths as shown in Figs. 12, 13, and 14 described above is considered as an example. The memory device 101 sends the set data connection to the connection path setting circuit 112 as the designation signal 111, and the connection path setting circuit 112 transfers the memory chips 102 to 105 according to the setting. (106) to (109), and the data of the memory chip is connected to the desired data bus.

8 shows an example of the configuration of a memory element which executes setting of a data connection from a user for command input. In the figure, reference numeral 113 denotes a command control circuit which makes a designation signal 111 from a register of a command setting value and the setting value. Reference numeral 114 denotes a data line in which a user sets a command setting value by using a part of the data input / output terminal. Other than that is the same as that of FIG.

The user selects the connection paths of the data as Fig. 12, 13, and 14 as an example, sets the command control circuit 113 as part of the data bus 114 as a command code, and sets the command control circuit ( In 113, a designated signal 111 corresponding to the connection path setting circuit 112 is sent from the set command code. The following is the same as the description of FIG. 7. According to this embodiment of FIG. 7 and FIG. 8, another embodiment described so far can be realized as a memory element, and the effect of reducing peripheral circuits can be achieved. have. In the present embodiment, a plurality of chips and control circuits are mounted in the memory package. However, by gathering them into one chip, the size and speed can be increased.

Claims (18)

A file storage device that uses a group of storage elements in which the minimum erase unit is larger than the data bus width of the file storage device and the data access width is smaller than the data bus width of the file memory device. File division means for dividing into a combination element consisting of a combination of arbitrary minimum storage units; arbitrarily combining data on a data bus in units of a data access width, and arranging a group of storage elements in the same unit in units of a data access width. File storage means having data distribution means corresponding to the combination, and control means for controlling the data distribution means so as to correspond to any one of said arbitrary combinations of the memory element group when storing each of the combination elements in the file storage device. Device. A file storage method for storing file data over a data bus using a group of memory elements having a minimum erase unit larger than the data bus width of the file memory and having a data access width smaller than the data bus width of the file memory, in parallel. Dividing the file data consisting of two or more minimum memory units into combination elements consisting of a combination of arbitrary minimum storage units, and storing the data on the data bus in units of data access when storing each of the combination elements in the file storage unit. Combining, and corresponding to any combination of storage element groups of the same number of units with data access widths, and mapping each of the combination elements to any one of the above arbitrary combinations of storage element groups. How to save a file. A file storage device that reads file data through a data bus using a group of memory elements having a minimum erase unit larger than the data bus width of the file storage device and having a data access width smaller than the data bus width of the file storage device in parallel. File dividing means for dividing file data of at least one minimum storage unit into combination elements consisting of a combination of arbitrary minimum storage units; data for dividing data on a data bus into any combination of data in units of data access width; When the storage means for dividing the partition means, the memory element group according to the number of divisions of the data partition means, and each combination element of the divided file data are stored in the file storage device, each of the divided data divided by the data partition means is stored. The element dividing means corresponds to one set of the divided memory element groups, and A file storage device with a control unit that controls to storage tank 1 of any one of any combination of the memory element group for each of the content of the element. 4. The file specification information for specifying a file and the minimum in the file according to claim 3, wherein the physical address comprises a memory element group specifying any of the memory element groups and address information specifying a specific minimum erasing unit in each memory element group. A file storage device for storing file storage information consisting of minimum storage unit specifying information for specifying a storage unit and file control information corresponding to chain information which is a physical address of another minimum storage unit in the same file in a storage element group or another storage device. 4. The storage device group or other storage device means according to claim 3, wherein the division contents of the file division means, the division contents of the data division means, the division contents of the memory element group, and the control contents of the control means are file control information for each file. File memory to remember. A file storage device that reads file data through a data bus using a group of memory elements having a minimum erase unit larger than the data bus width of the file storage device and having a data access width smaller than the data bus width of the file storage device in parallel. File dividing means for dividing file data of at least one minimum storage unit into combination elements consisting of a combination of arbitrary minimum storage units; data for dividing data on a data bus into any combination of data in units of data access width; The storage means for dividing the partition means, the memory element group into the data partition means in accordance with the number of divisions, and when storing each combination element of the divided file data in the file storage device, each of the divided data divided by the data partition means is stored. The element dividing means corresponds to one set of the divided memory element groups, and Control means for controlling the contents of each sum element to be stored in a set of any combination of storage element groups, file division means, contents of division, contents of division of data division means, contents of division of memory element division means, and control And a storage control means for storing the control contents of the means as file control information for each file in the storage element group or other storage means, and a gid means for reading the file information in accordance with the stored file storage information. Using a group of memory elements with a minimum erase unit greater than X bits and a data access width of Y bits (Y = X / P: P is an integer greater than or equal to 2) in parallel, the file data is read-written through an X-bit data bus. A file storage device comprising: file dividing means for dividing a file composed of one or more minimum memory units into a combination of any minimum storage units from 1 to P, and each combination element of a file divided by the file dividing means. Data storage means for dividing the X-bit data on the data bus into Q pieces of Y-bit units (Q = X / Y, and not dividing when Q = 1). Each of the memory element dividing means and the divided data into Q correspond to one set of which the memory element dividing means divides, and controls the contents of any combination element of the minimum memory unit to correspond to the same memory element group. In the storage means stored in the storage element, the division contents of the file division means, the division contents of the data division means, the division contents of the memory element group, and the control contents of the control means for each file. Hence, a file storage device having lead means for reading file information. Store data in files via an X-bit data bus, and use a flash memory device with a minimum erase unit greater than X bits and a data access width of Y bits (Y = X / P: P is an integer greater than or equal to 2). The P group which can be accessed simultaneously corresponds to a flash memory device comprising a flash memory element group, dividing means for dividing at least P data on an X-bit data bus, and at least P Y-bit data obtained by the dividing corresponding to one set of flash memory element groups. A data distributing means having a first function of making a first function and a second function of making each of the P pieces of Y-bit data correspond to a separate group of flash memory element groups; A flash memory file storage device having control means for controlling the data distribution means to switch the second function. 9. The flash memory file storage device according to claim 8, wherein said control means controls said data distribution means so that data of another file does not mix in a memory area of a minimum erase unit of said flash memory element. 9. The apparatus according to claim 8, wherein said control means selects said second function for data in P storage capacity units belonging to said file, and selects said first function for data in one storage capacity unit. Flash memory file storage device for controlling the number of data distribution. 9. The flash memory file storage device according to claim 8, wherein the memory capacity unit and the erase unit of the flash memory element are the same. A central processing unit for processing programs and data, a clock oscillating unit for driving the central processing unit, a file storage unit using a flash memory as a storage medium, a file storage unit for controlling access to a flash memory of the file storage unit, A flash memory which inputs the same signal as the clock signal generated by the clock oscillation means or a synchronous signal to the file memory control means, and wherein the central processing means and the file memory control means perform synchronization operations to receive file data; An information processing device equipped with a file storage device. The data storage control means according to claim 12, wherein the file storage control means outputs a status indication signal indicating whether the file data is being processed or is finished when the central processing means and the file storage means have different data access widths. And the central computation processing means receives the status indication signal and indicates that this is being processed, has a period until the end of the processing and means for stopping the progress of the processing. The file storage control means includes: And a data bit width control means for matching the number of data bits to be handled to the processing data bit width of the central processing unit, wherein the data bit width control means is provided for the period required to match the data bit width, and the state presentation signal. Display the central processing unit and wait for the processing data to be processed. Value by the information processing apparatus for executing a transfer of data. 14. The file storage control unit according to claim 13, wherein the file storage control unit constitutes the file storage unit by the number of flash memory groups necessary for generating data having the same number of bits as the data access width of the central processing unit. Means for defining a continuous order in the memory group, for files reaching a number of storage capacity units, the means for storing in accordance with the order of the prescribed memory group, and the number of storage capacity units being increased by updating a stored file once. And a means for securing a storage area for an incremental storage capacity unit in a memory group defined in the next order of the memory group in which the last data of the file was stored when the last time was stored for the increment. An information processing device comprising a central processing unit and a file storage device using a plurality of flash memory elements as a storage medium, wherein the minimum erasure unit of data in the flash memory of the file storage device is the same as the storage capacity unit of file management; When the central processing unit requests file access, if the number of storage capacity units is multiple, the plurality of flash memory devices are accessed simultaneously. If the number of storage capacity units is 1, one of the flash memory devices is accessed. Information processing device. When the flash memory is used as a storage medium, and the storage capacity of one file to be stored reaches several storage units, each storage unit stores information on the physical location where the next storage unit is stored. A flash memory file storage device having chain information storage means. Several memory chips are assembled in one package, and the package has a number of input / output data terminals corresponding to the total number of data input / output of the entire memory chip, and a control signal terminal for instructing the data control means from the memory user. And data control means for switching input / output data of the plurality of arbitrary memory chips in accordance with an instruction of the control signal terminal, and connecting to any terminal of the input / output data terminal. A plurality of memory chips are assembled in one package, and the package has a number of input / output data terminals corresponding to the total number of data input / outputs in the entire memory chip, and control commands for instructing the data control means from the memory user. Means and a data control means for switching input / output data of the plurality of arbitrary memory chips by an instruction of said control command setting means, and connecting to any terminal of said input / output data terminal.