JP3589699B2 - Data processing device and data processing system using the same - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a data processing device, and relates to a technology that is effective when applied to a memory that requires a command for an operation instruction, for example, a microcomputer that connects a flash memory. The present invention also relates to an emulator that evaluates a system to which such a data processing device is applied or debugs software for the system.
[0002]
[Prior art]
As described in the "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993, a microcomputer composed of a semiconductor integrated circuit has a part or all of an address space of a CPU serving as a central processing unit externally. As an address, an address bus, a data bus, and a control signal can be input / output to / from the outside, and a memory or other circuit connected to the outside can be read / written. At this time, depending on the setting of a predetermined register, an area decode signal corresponding to a region obtained by dividing the address space, for example, a chip select signal, a multiplexed row address / column address, and an output of various strobe signals are output. Various waveforms such as a mask ROM, a static RAM (SRAM), a pseudo-static RAM (PSRAM), and a dynamic RAM (DRAM) are directly connected by changing a waveform to enable reading / writing.
[0003]
[Problems to be solved by the invention]
However, the address / data provided to or read from the memory at the time of read / write may not be directly related to the information stored in the memory. For example, a flash memory described in "Hitachi IC Memory 2", pp. 280-304, issued by Hitachi, Ltd., September 1993, requires a command to specify the operation of the memory to be given from the data bus in advance. There is.
[0004]
FIG. 26 shows an example of the command of the flash memory.
In the figure, W indicates a write operation, R indicates a read operation, X indicates an arbitrary value, RA indicates a read address, RD indicates read data, BA indicates a block address, PA indicates a write address, PD indicates write data, and H 'indicates a hexadecimal number. . The block address BA is address information for specifying a block to be erased in block units.
For example, when writing data, a command (H'10) is written before writing data, and then data (PD) to be written is written to an address (PA) to be written. .
[0005]
A program example of a write operation by the CPU is shown below. The instructions are the same as those of the CPU described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd., March 1993.
MOV. B #CMD, R0L ... (1)
MOV. BR0L, @FMEM ... (2)
MOV. B #DATA, R0L ... (3)
MOV. BR0L, @WADR ... (4)
In the above description of the instruction, CMD indicates a command value (H'10 in the example of FIG. 26), DATA indicates write data, and # indicates immediate data. FMEM is an arbitrary address of the flash memory, and WADR is a write address. ＠ indicates a memory address. The above-mentioned instruction (1) is an instruction to transfer the command CMD to the register R0L of the CPU, (2) is an instruction to transfer the command of the register R0L to the address @FMEM of the flash memory, and (3) is data to be written to the register R0L of the CPU. (4) is an instruction to transfer the data of the register R0L to the write address WADR.
[0006]
The address may be specified as an absolute address or may be register indirect. Write data may also be prepared on a general-purpose register. As is apparent from the above instruction description, writing 1-byte data requires instructions (1) and (2) for writing a command to the flash memory. On the other hand, twice as many instructions need to be executed. As a result, the program size increases and the processing speed also decreases.
[0007]
Since the CPU can execute an arbitrary program, if the load on the software is increased as described above, data can be written to the flash memory by the command method. However, a direct memory access controller (DMAC) or the like can perform only simple data transfer, and determines whether an access target is, for example, an SRAM or a flash memory, and inserts a command. Is not easy. According to the study of the present inventor, when such data writing is to be realized by a DMAC, a command must be stored in the transfer source together with the write data, and such a thing is actually performed. If this is the case, the load on the CPU prior to the DMA transfer is significantly increased, and the throughput of the system is significantly reduced. In other words, it is not a practical approach. An example of DMAC is described in "H8 / 3003 Hardware Manual" issued by Hitachi, Ltd. in March 1993. In addition to the DMAC, the same applies to a data transfer controller (DTC) and the like. DTC is described in, for example, "H8 / 532 Hardware Manual" issued by Hitachi, Ltd. in December 1988.
[0008]
An object of the present invention is to provide a data processing device capable of automatically adding or inserting a bus cycle for command transfer to a peripheral circuit such as a flash memory whose operation is instructed by a command.
Another object of the present invention is to provide a data processing device for automatically adding or inserting the bus cycle according to bus information for accessing a required peripheral circuit.
Another object of the present invention is to provide a data processing device for automatically adding or inserting the bus cycle by writing control information into a predetermined internal register.
Still another object of the present invention is to provide a data processing device capable of shortening an instruction execution time for accessing a peripheral circuit such as a flash memory whose operation is instructed by a command and reducing a program size. .
It is another object of the present invention to provide a data processing device such as a DMAC which can be directly connected to and access a peripheral circuit such as a flash memory whose operation is instructed by a command.
Further, the present invention provides an emulator for evaluating a system to which the data processing device is applied and debugging software for the system by using a function of the data processing device capable of automatically adding or inserting a bus cycle for command transfer. An object of the present invention is to provide a technique for preventing usability from deteriorating.
[0009]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0011]
(1) A data processing device (for example, a single-chip microcomputer 1) which incorporates a bus master means (for example, a CPU 2 or a DMAC 3) that can use an external bus and can be connected to an external circuit (for example, a flash memory 10) whose operation is instructed by a command. Responding to an instruction to access an external predetermined address space by a bus master means, and prior to generating an external bus access cycle corresponding to the access instruction, operating the external circuit with respect to the predetermined address space. Bus control means (for example, bus controller 4) for generating a first command write cycle for writing a command for instructing a command.
[0012]
(2) The bus control means includes an address space designating means (for example, a register CMDCR) for designating an address space in which a first command write cycle should be started, and an access address by a bus master means designated by the address space designating means. Determining means (for example, the control circuit 41) for determining whether or not the address is included in the specified address space; and timing control means (for example, for generating the first command write cycle based on the detection result of the presence by the determining means). And a timing control circuit 44) including the configuration shown in FIG.
[0013]
(3) Commands to be written in the first command write cycle can be rewritably held in command storage means (for example, registers WCMD, CDATA0, and CDATA1).
[0014]
(4) Further, the bus control means includes a control register means (for example, a register CNTL) and a predetermined address space in a predetermined address space by the CPU operating a first bit (for example, bits BE0 to BE3) of the control register means. Timing control means (for example, a timing control circuit 44 including the configuration shown in FIG. 19) for generating a second command write cycle for writing command data (for example, a command for erasing a block in a flash memory). Can be.
[0015]
(5) The address to be output in the second command write cycle can be stored in address storage means (for example, registers BADR0 to BADR3).
[0016]
(6) Further, the bus control means is inputted from a predetermined external terminal (for example, a ready input terminal READY) by the CPU operating a second bit (for example, bit RE, bit POL) of the control register means. Timing control means (for example, a timing control circuit 44 including the configuration shown in FIG. 19) for generating an external read cycle for performing polling control for waiting for a change in a signal (for example, an output signal RDY / BUSY * of a flash memory). Can be prepared.
[0017]
(7) It is desirable to provide the data processor for emulation with an emulation interface for outputting an identification signal indicating whether or not a bus cycle to the outside is the command write cycle. Further, in the data processing device for emulation, the CPU outputs a control signal for inhibiting generation of the first command cycle by the bus control means based on a predetermined external interrupt (for example, a break signal). Such a data processing device can constitute a data processing system by an emulator coupled to an emulation interface included in the data processing device. The emulator has a trace memory and a break control circuit. The trace memory inputs and stores the identification signal together with the bus information of the data processing device, and the break control circuit predicts the control state of the data processing device. When a set state is reached, a break signal is output to the data processing device as the interrupt signal.
[0018]
(8) The data processing device may further include a direct memory access controller as the bus master means, and may be formed as a single-chip microcomputer on one semiconductor substrate. Such a data processing device can constitute a data processing system including, for example, a flash memory as an external circuit directly connected to the data processing device.
[0019]
(9) A data processing device having a built-in bus master means capable of using an external bus and connectable to a flash memory whose operation is instructed by a command, responds to an instruction to access an external predetermined address space by the bus master means, Prior to generation of an external bus access cycle corresponding to the access instruction, bus control means for generating a command write cycle for writing a command for instructing the operation of the flash memory to the predetermined address space; An external input terminal for a signal indicating the internal operation state of the flash memory designated by the write can be formed on one semiconductor substrate.
[0020]
[Action]
According to the above means (1) to (3), when a predetermined address space allocated to an external circuit such as a flash memory is accessed, prior to the access, a command for instructing the operation of the external circuit is issued. Is automatically inserted for writing the first command write cycle. This eliminates the need for a process for writing a command each time a byte or page is written to the flash memory and a program description for defining the process.
[0021]
According to the above means (4) and (5), when a predetermined bit of the internal control register is operated by the CPU, the second command for writing a command for instructing the operation of the external circuit is written after the operation. Command write cycle is automatically inserted. This means that, even when command writing divided into a plurality of times, such as block erasing for a flash memory, is required, the instruction description may define writing to the control register and the like. And the program size can be reduced.
[0022]
According to the means (6), starting and maintaining an external read cycle for polling control by operating a predetermined bit of a built-in control register by the CPU also requires the same data processing efficiency as in the case of generating an external bus cycle. And the program size can be reduced.
[0023]
According to the above-mentioned means (7), the command write cycle specially inserted does not have a corresponding instruction description, but this would hinder the emulation of verifying the instruction execution trajectory from the trace information. , The identification signal serves to indicate that it is a specially inserted command write cycle. Further, in a state where the operation space of the data processing device is switched after the break and the control program for emulation is executed, a control RAM or the like is allocated so as to overlap the address where the command write cycle is to be inserted. In such a case, the function of the data processing device that automatically prevents a command write cycle from occurring and erroneously rewrites the data in the RAM and automatically adds or inserts a command write cycle is provided by the data processing device. An emulator that evaluates a system to which the application is applied and debugs software for the system is not reduced.
[0024]
Even if the bus master means is a direct memory access controller as explicitly shown in the above means (8), the direct memory access controller can also transfer the flash memory of such a command format to the data by the automatic insertion of the command write cycle. It can be used as a transfer source or a data transfer destination.
[0025]
According to the data processing device of the above-mentioned means (9), simplification of the interface with the flash memory, the operation of which is instructed by a command, and improvement of usability are achieved.
[0026]
【Example】
FIG. 1 shows a single-chip microcomputer which is an embodiment of a data processing device according to the present invention.
The single-chip microcomputer 1 shown in FIG. 1 includes a CPU 2, a DMAC 3, a bus controller (BSC) 4, a ROM 5, a RAM 6, a timer 7, a serial communication interface (SCI) 8, first to ninth input / output ports IOP1 to IOP9, A clock oscillator (CPG) 9 is composed of functional blocks or modules, and is formed as a semiconductor integrated circuit on one semiconductor substrate by a known semiconductor manufacturing technique.
[0027]
The single-chip microcomputer 1 has a ground level terminal Vss, a power supply voltage level terminal Vcc as power supply terminals, and a reset terminal RES, a standby terminal STBY, a mode control terminal MODE, and clock input terminals EXTAL and XTAL as other dedicated control terminals. . They are external terminals.
The single-chip microcomputer 1 operates in synchronization with the system clocks φ1 and φ2 generated by the clock oscillator 9 based on a crystal oscillator (not shown) connected to the clock input terminals EXTAL and XTAL. Alternatively, an external clock may be input to the EXTAL terminal. One cycle of the system clocks φ1 and φ2 is called one state. The system clocks φ1 and φ2 are non-overlapping two-phase clocks, and φ2 is a clock whose phase is substantially inverted or shifted by 180 ° with respect to φ1.
[0028]
The functional blocks are interconnected by an internal bus. The internal bus includes a control bus including a read signal, a write signal, a bus size signal, and system clocks φ1 and φ2 in addition to an address bus and a data bus. IAB and PAB exist on the internal address bus, and IDB and PDB exist on the internal data bus. The IAB and IDB are connected to the CPU 2, the ROM 5, the RAM 6, the bus controller 4, and some of the input / output ports IOP1 to IOP9. PAB and PDB are connected to the bus controller 4, the timer 7, the SCI 8, and the input / output ports IOP1 to IOP9. The IAB and PAB and the IDB and PDB are interfaced by the bus controller 4, respectively. Although not particularly limited, PAB and PDB are exclusively used for register access in the functional block to which they are connected.
[0029]
The input / output ports IOP1 to IOP9 are also used for input / output of external bus signals and input / output signals of input / output circuits. These functions are selected and used depending on the operation mode or software setting. The input / output ports IOP1 to IOP3 are used for address bus output, the input / output ports IOP4 and IOP5 are used for data bus input / output, and the input / output ports IOP6 and IOP7 are also used for bus control signals. The external address and external data are connected to IAB and IDB via buffer circuits (not shown) included in these input / output ports, respectively. PAB and PDB are used to read / write a built-in register such as an input / output port and the bus controller 4, and have no direct relation to an external bus.
[0030]
Both the internal bus and the external bus have a 16-bit bus width, and read / write of byte size (8 bits) and word size (16 bits) is performed. The external bus may have an 8-bit width.
[0031]
The bus control signals include area selection signals CS0 * to CS7 *, read signals RD *, write signals HWR * and LWR *, column address strobe signals CAS *, wait signals WAIT *, ready signals READY, and the like.
[0032]
When a reset signal is applied to the reset terminal RES, the operation mode given by the mode control terminal MODE is fetched, and the single-chip microcomputer (hereinafter simply referred to as microcomputer) 1 is reset. The operation mode is not particularly limited, but the validity / invalidity of the built-in ROM 5, the address space is selected from 16 Mbytes or 1 Mbyte, and the initial value of the data bus width is selected from 8 bits or 16 bits. A plurality of mode control terminals MODE are provided as necessary, and an operation mode is determined by a combination of input states to these terminals.
[0033]
When the built-in ROM 5 is invalidated, the external address is made valid, and the address corresponding to the ROM 5 is set as the external address. The built-in ROM 5 is, for example, a mask ROM or a PROM (programmable ROM). Since the contents of the mask ROM are written during the manufacturing process of the semiconductor integrated circuit, the time from when the user creates the program to when the user obtains the microcomputer is extremely long. Also, rewriting cannot be performed. The PROM allows a user to write a program, but cannot rewrite the program while the PROM is attached to the system. Alternatively, the storage capacity of the ROM 5 that can be built in the microcomputer is not as large as that of the ROM alone, and it is not always possible for the user to store the desired program scale in the built-in ROM 5. Therefore, it is conceivable that a ROM for storing a program is provided outside the microcomputer separately from the microcomputer without using the built-in ROM. By exchanging an external ROM for storing programs while the microcomputer is mounted in the system, the time from program creation to system acquisition can be reduced, or system specifications can be changed. Hereinafter, a case where a program ROM is provided outside without using the built-in ROM will be described.
[0034]
When the reset state is released, the CPU 2 reads a start address and performs a reset exception process for starting reading an instruction from the start address. Although the start address is not particularly limited, it is assumed that the start address is stored in an area starting from address 0. Thereafter, the CPU 2 executes instructions sequentially from the start address.
[0035]
DMAC 3 transfers data under the control of CPU 2. The CPU 2 and the DMAC 3 perform read / write operations using the internal bus and the external bus exclusively. Arbitration of which of the CPU 2 and the DMAC 3 operates is performed by the bus controller 4.
[0036]
The bus controller 4 configures a bus cycle in response to the operation of the CPU 2 or the DMAC 3. That is, a bus cycle is formed based on the address, read signal, write signal, and bus size signal output from the CPU 2 or the DMAC 3. For example, when the CPU 2 outputs an address corresponding to the RAM 6 to the internal address bus IAB, the bus cycle is set to one state, and reading / writing is performed in one state regardless of the byte / word size. When the CPU 2 outputs addresses corresponding to the timer 7, the SCI 8, and the input / output ports IOP1 to IOP9 to the internal address bus IAB, the bus cycle is set to three states, and the contents of the internal address bus IAB are output to the internal address bus PAB. The read / write operation is performed in three states regardless of the byte / word size. This control is performed by the bus controller 4.
[0037]
FIG. 2 shows an example of an address map of the microcomputer 1.
The address space is 16 Mbytes in total, and the address space is divided into 8 areas of 2 Mbytes each. Area selection signals CS0 * to CS7 * corresponding to these areas are output. For example, when area 0 is accessed, the area selection signal CS0 * is activated. The area selection signal is a signal that is used as a chip selection signal for a circuit to which it is input.
[0038]
The access method for each area is specified by five 8-bit registers BSWCR, ASTCR, WSCRA-B, MPXCR, and CMDCR included in the bus controller 4.
Each bit of each register controls an area corresponding to a number. These correspondences are shown in the figure. For example, area 0 is controlled by each bit 0 of BSWCR, ASTCR, WSCRA-B (WSCRA and WSCRB), MPXCR, and CMDCR.
These registers can always be read / written by the CPU 2. The initial value of the register BSWCR is determined by the operation mode. That is, if the initial value of the data bus width is 8 bits, it is initialized to H'FF, and if it is 16 bits, it is initialized to H'00. The initial values of the registers ASTCR and WSCRA-B are set to H'FF, and the initial values of the registers MPXCR and CMDCR are set to H'00.
[0039]
The register BSWCR specifies the bus width of each area. A bus width of 8 or 16 bits is selected. When the corresponding bit is cleared to "0", a 16-bit bus is selected, and when the corresponding bit is set to "1", an 8-bit bus is selected.
[0040]
The registers ASTCR and WSCRA-B specify the number of bus cycles in each area. The number of bus cycles is selected from 2, 3, 4, 5, and 6 states. When the corresponding bit of the register ASTCR is cleared to "0", two-state access is performed. When the bit is set to "1", the number of states is specified by the register WSCRA-B. The register WSCRA-B sets the number of wait states. When all the corresponding bits of the register WSCRA-B are cleared to "0", no wait state is set (3-state access), the corresponding bit of the register WSCRA is cleared to "0", and the corresponding bit of the register WSCRB is set to "0". When set to “1”, a one-state wait (four-state access) is set. When the corresponding bit of the register WSCRA is set to “1”, and when the corresponding bit of the register WSCRB is cleared to “0”, a two-state wait (five-state access) is performed. ), And if all the corresponding bits of the register WSCRA-B are set to "1", a 3-state wait (6-state access) is set. The wait inserted by the register WSCRA-B is called a programmable wait and is distinguished from an external wait instructed from outside the microcomputer.
[0041]
The register MPXCR specifies an address multiplex. This is effective when the bus cycle has three or more states. For example, when connecting a 16-bit 4-Mbit DRAM, a row address (logical address A18-A10) is first output to the address output A9-A1 of the microcomputer, and then a column address (logical address A9-A1). ) Is output. At this time, the waveform of the area selection signal is changed at the same time, and the RAS * (row address strobe) signal is activated after the output of the row address. The setup and hold of the row address is secured. After the output of the column address, a CAS * (column address strobe) signal is activated from another terminal.
[0042]
The register CMDCR specifies an area for automatically generating a command cycle. When the CPU 2 or the DMAC 3 makes a predetermined access to an area where the corresponding bit of the register CMDCR is set to “1”, a bus command cycle is automatically inserted. For example, if the CPU 2
MOV. B #DATA, R0L
MOV. BR0L, @WADR
Is executed to execute a write cycle of data DATA for the address WADR. If the address WADR corresponds to an area in which the corresponding bit of the register CMDCR is set to "1", for example, A write cycle for the address WADR of the command CMD instructing the write operation to the memory is automatically activated and inserted, and then a bus cycle for the data DATA write operation for the address WADR is activated. Become. Here, when writing a command, if a chip selection signal for a circuit such as a flash memory to be written is directly supplied to the circuit as an area selection signal, the command is output to the outside at the time of command writing. Addresses have no real meaning. In this example, the same address as the address of the next data write is output for convenience.
The built-in memories and peripheral functions such as the RAM 6, the timer 7, the SCI 8, and the input / output ports IOP1 to IOP9 are included in the area 7, but are fixed to their respective bus widths and bus cycle numbers.
[0043]
FIGS. 3 and 4 show other register configurations for bus control.
The register WCMD has an 8-bit configuration, and stores data which is a command to be output prior to the above-described write cycle.
Each of the registers CDAT0 and CDAT1 has an 8-bit configuration, and stores data serving as a command to be output prior to the above-described write cycle. CDAT0 is the first command, and CDAT1 is the second command. That is,
When the required command is 2 bytes, the registers CDAT0 and CDAT1 are used. As an example of the 2-byte command, there are the commands H'20, H, and B0 for the block erase shown in FIG.
Each of the registers BADR0 to BADR3 has a 16-bit configuration and stores address information.
The above registers WCMD, CDAT0 to CDAT1, and BADR0 to BADR3 are always readable / writable by the CPU 2, and the initial value is H'00.
[0044]
The register CNTL has an 8-bit configuration, and conditions for adding a command bus cycle are set. Bits BE0 to BE3 are condition bits for block erasing of the external flash memory, and bit POL is a condition bit for polling. In addition, a bit RE is included. The bit RE is always readable / writable by the CPU 2, but the bits BE0 to BE3 and the bit POL are only writable "1", and are automatically cleared to "0" when a predetermined operation is completed. . Bits 4 and 5 are reserved bits, and when read, "0" is read and writing is invalidated.
[0045]
The initial value of the register CNTL is set to H'00.
When the bit RE is set to "1", the input of the READY terminal of the microcomputer becomes valid. In this state, if the bit POL is set to "1" by the CPU 2, a polling read cycle is automatically inserted externally following the bus cycle. At this time, a busy signal input from, for example, a flash memory to a READY terminal (to be described later) of the microcomputer 1 is recognized as a wait signal. For example, when the external flash memory is performing an internal operation and outputting a busy signal, that is, when the external flash memory is performing an internal operation, the microcomputer 1 is in a wait state until the internal operation is completed. In the meantime, the polling read cycle is automatically continued.
[0046]
If there is any other content to be processed by the microcomputer 1 during the internal operation of the flash memory, the microcomputer 1 outputs the RDY / BUSY * signal (ready at high level, busy at low level) output from the flash memory. , The rising edge may be detected to generate an interrupt. That is, after instructing the flash memory to perform writing or erasing, the microcomputer 1 detects the end of the operation by an interrupt due to the rising edge of the RDY / BUSY * signal. Therefore, the microcomputer does not need to constantly monitor the end of the operation of the flash memory during that time, and the load on the operation control of the flash memory is reduced.
When the bit RE is cleared to "0", the input of the READY terminal is invalidated, and the corresponding terminal can be used as an input / output port.
[0047]
When any one of bits BE0 to BE3 is set to "1", a command write cycle for erasing a block in an external flash memory is started following the bus cycle. The command has contents stored in the registers CDAT0 and CDATA1 in advance. Block erasure is specified by a 2-byte command. At this time, the erase target block address is an address specified by the registers BADR0 to BADR3.
For example, if the block size of the flash memory is 512 bytes, four addresses can be specified at the same time. Therefore, 2 kbytes can be continuously erased.
[0048]
Each of the registers BADR0 to BADR3 has 16 bits, and the lower 1 bit is ignored. The lower 8 bits are set to H'00 in these 16 bits, and the erase block address is designated. This corresponds to an address space of 16 Mbytes. Therefore, when H'0123 is set in the register BADR0, the start address of the erase block is H'012200.
At this time, the bit of the register CMDCR corresponding to the area including this address is set to “1”. When H'20 is stored in the register CDAT0 and H'B0 is stored in the register CDAT1, and the bit BE0 is set to "1", two write cycles are executed for the address H'012200, and the first data Is H'20, the second data is H'B0, and the 146th block of the flash memory is erased.
[0049]
When chip erasing or continuous block erasing is performed, the command data set in CDAT0 and CDATA1 may be changed to data equivalent to chip erasing or continuous block erasing. Further, if the command data set in the registers CDAT0 and CDATA1 is changed to data corresponding to page writing, and a bus command is issued and a write cycle is sequentially performed, page writing can be performed using the register CNTL.
In the case of a 16-bit bus, the same command data is output to the upper 8 bits and lower 8 bits.
[0050]
As described above, the write operation to the flash memory, the block erasure, the polling, and the like in which the operation instruction is given by the command can be performed with the load on the CPU 2 reduced. The write operation to the flash memory can be performed when the DMAC 3 starts a bus cycle in the same manner as when the CPU 2 starts.
[0051]
The read operation for the flash memory can be performed at random. That is, according to FIG. 26, the read operation is instructed by the command H'00. However, when the read operation is instructed by the command, the flash memory can perform the read operation at any time unless another operation mode is instructed thereafter. To be. For example, upon power-on reset or exception processing, the microcomputer 1 unconditionally writes a command H'00 instructing a read operation to the flash memory. The information stored in the flash memory is, for example, constant data and tuning information to be rewritten, in addition to an operation program exclusively used for reading. If such constant data and tuning information are rewritten by exception processing in a system to which the microcomputer 1 is applied, a read operation to the flash memory can be performed at any time.
[0052]
FIG. 5 shows an example of a system using the single-chip microcomputer 1.
Although not particularly limited, the system shown in FIG. 1 is a printer control system, and includes a single-chip microcomputer 1, a flash memory 10 for storing programs and tuning information of the single-chip microcomputer 1, and a DRAM (buffer) for a data buffer. RAM 11, a mask ROM for character generation (referred to as CGROM) 12, an SRAM (output buffer) 13 for temporarily storing print data, a centronics interface circuit 14 for interfacing with a host processor (not shown), and a print head drive. It has circuits 15, which are connected via an external bus 16 of the single-chip microcomputer 1. The Centronics interface circuit 14 and the print head drive circuit 15 are formed of the same semiconductor integrated circuit, for example, a gate array (G / A), and the other circuits are formed of separate semiconductor integrated circuit chips. Further, although not shown, the SCI 8 of the microcomputer 1 is connected to a host processor and includes a line feed motor and a carriage return motor of a printer controlled by the output of the timer 7 of the microcomputer 1.
[0053]
The single-chip microcomputer 1 operates based on a program stored in the flash memory 10. For example, based on such a program, data sent from the host processor is transferred to the buffer RAM 11 via the Centronics interface circuit 14. The data transferred to the buffer RAM 11 is converted into font data by referring to the CGROM 12. The font data is stored in the output buffer RAM 13. Thereafter, the single-chip microcomputer 1 outputs a pulse using the timer 7, and drives a carriage return motor (not shown). The print head is moved by the rotation of the carriage return motor. Font data is transferred from the output buffer RAM 13 to the print head drive circuit 15 in accordance with the movement of the print head. The DMAC 3 built in the single-chip microcomputer 1 can be used for data transfer from the Centronics interface circuit 14 to the buffer RAM 11 and data transfer from the output buffer 13 to the print head drive circuit 15. By rewriting the tuning information stored in the flash memory 10, fine adjustment of the system can be performed. Further, the operation program stored in the flash memory 10 may be modified by version upgrade or use change. The rewriting of the flash memory 10 can be efficiently performed by the above-mentioned automatic insertion or additional function of the command cycle by the single-chip microcomputer.
[0054]
For example, in the system shown in FIG. 5, the flash memory 10 is set to area 0, the CGROM 12 is set to area 4, the buffer RAM 11 is set to area 5, the output buffer 13 is set to area 6, the centronics interface circuit 14, and the print head drive circuit 15 are set to area 7. And
Area 0 is a 16-bit bus, 3-state, command valid,
Area 4 has a 16-bit bus and 3 states,
Area 5 is a 16-bit bus, 3-state, address multiplex,
Area 6 has a 16-bit bus and two states.
Area 7 has an 8-bit bus and 3 states,
The programmable wait shall not be inserted in any area.
At this time, the setting of the above register is
BSWCR = B'10000000,
ASTCR = B′10110001,
WSCRA = B'00000000,
WSCRB = B'00000000,
MPXCR = B'00100000,
CMDCR = B'00000001
It is said.
[0055]
FIG. 6 shows an example of a connection state by the external bus 16 in the system of FIG. In the figure, G / A is a gate array constituting the Centronics interface circuit 14 and the print head drive circuit 15.
The flash memory 10 is 16 Mbit described in “Hitachi IC Memory 2” pp 305-321 published by Hitachi, Ltd., September 1993, and the mask ROM 12 is “Hitachi IC Memory 2” pp 681 published by Hitachi, Ltd., September 1993. The DRAM 11 is a 16 Mbit DRAM described in "-687", and the DRAM 11 is a 4 Mbit DRAM described in "Hitachi IC Memory 3", pp 432-455, issued by Hitachi, Ltd. in September 1993. The number of the SRAMs 13 is two 4 Mbits described in "Hitachi IC Memory 1", pp. 470-478, issued by Hitachi, Ltd. in September 1993.
[0056]
The address is input to all of the flash memory 10, DRAM 11, mask ROM 12, SRAM 13, and G / A 14 and 15. However, the number of bits corresponding to each capacity is input. For example, since the flash memory 10 has a capacity of 1 M words (16 M bits), the address is 20 bits. Since the single-chip microcomputer 1 is an address in byte units and the flash memory 10 is an address in word units, the microcomputer 1 operates so that the least significant bit of the address output by the microcomputer 1 is ignored and the address is halved. The address is supplied to the flash memory 10. That is, the address terminals A20 to A1 of the microcomputer 1 are connected to the address terminals A19 to A0 of the flash memory 10. One of the SRAMs 13 has an even address and the other has an odd address. Address terminals A19 to A1 of the microcomputer are connected to address terminals A18 to A0 of the SRAM 13.
[0057]
The upper data buses D15 to D8 are connected to the flash memory 10, the DRAM 11, the mask ROM 12, the SRAM (even address) 13, and the G / As 14, 15. The lower data buses D7 to D0 are connected to the flash memory 10, DRAM 11, mask ROM 12, and SRAM (odd address) 13. Output terminal CS0 * (symbol * means that the active level of the signal to which it is attached is low level, and in the drawing, a horizontal bar attached to the signal name is attached instead of symbol *. Is connected to the flash memory 10, the output terminal CS4 * is connected to the mask ROM 12, and the output terminal CS6 * is connected to each chip selection signal input terminal CS * of the SRAM 13. The output terminal CS5 * is connected to the row address strobe signal input terminal RAS * of the DRAM 11. The output terminal CS7 is input to the chip selection signal input terminals CS * of the G / As 14 and 15. CS0 *, CS4 *, CS5 *, CS6 *, and CS7 * are output terminals for area selection signals.
[0058]
The output terminal RD * of the read signal is connected to the input terminal OE * of the output enable signal of the flash memory 10, the mask ROM 12, and the SRAM 13, and is also connected to the G / A input terminal OE *.
The output terminal HWR * of the write signal of the upper byte is connected to the upper write enable signal input terminal UW * of the flash memory 10 and the DRAM 11 and the write enable signal input terminal WE * of the SRAM (even address) 13. It is also connected to the write enable signal input terminal WE *.
The output terminal LWR * of the write signal of the lower byte is connected to the lower write enable signal input terminal LW of the flash memory 10 and the DRAM 11 and the write enable signal input terminal WE * of the SRAM (odd address) 13.
The output terminal CAS * of the column address strobe signal of the microcomputer 1 is connected to the column address strobe signal input terminal CAS * and the output enable signal input terminal OE * of the DRAM 11.
Further, the output terminal RDY / BUSY # of the ready / busy signal of the flash memory 10 is connected to the input terminal READY of the microcomputer 1.
Note that the symbols of the various terminals are also used as signs of the input or output signal names of the corresponding terminals in the following description.
[0059]
FIGS. 7 to 15 show typical bus cycle timings in the setting state of the registers BSWCR, ASTCR, WSCRA, WSCRB, MPXCR, and CMDCR in the system of FIG. 5, for example, the timing at the time of word data access. At these timings, word data access is limited to 2-byte data starting from an even address. Although not particularly limited, the upper bits D15 to D8 of the data bus are used for the 8-bit bus. All bus control signals are of negative logic.
[0060]
(1) 16-bit bus in area 0, 3-state access
The bus cycle timings of the read and write operations in this case are shown in FIGS.
In the case of a 16-bit bus of area 0 and three-state access, data at even addresses is read / written using the upper data bus, and data at odd addresses is read using the lower data bus. The microcomputer 1 activates the read signal RD * / higher-order write signal HWR * corresponding to even-numbered address read / write, and the read signal RD * / lower-order write signal LWR * corresponding to odd-numbered address read / write. And Read is controlled collectively by 16 bits. Writing is controlled in byte units. The address and CS0 * signal output are valid during the bus cycle. Read signal RD * is set to an active level in synchronization with the fall of clock φ in clock T1 (rise of clock φ2), and returned to inactive in synchronization with the fall of clock φ in clock T3 (rise of clock φ2). It is. The upper write signal HWR * and the lower write signal LWR * output from the microcomputer 1 are set to the active level in synchronization with the rise of the clock φ in the T2 state (the rise of the clock φ1), and the fall of the clock φ in the T3 state (clock) It is returned to inactive in synchronization with the rise of φ2).
At this time, the read operation is performed as it is, but when a write operation is instructed, a write cycle of a command to the flash memory is inserted. In the write cycle of the command, an address output by a bus master such as CPU 2 or DMAC 3 is output to the external address bus. The data at that time is the command data held in the WCMD register. The address and control signal outputs are the same as described above.
[0061]
(2) 16-bit bus in area 4 and 3-state access
The bus cycle timing of the read and write operations in this case is shown in FIGS. In the 16-bit bus and the three-state access of the area 4, data at even addresses is read using the upper data bus, and data at odd addresses is read using the lower data bus. Read is controlled collectively by 16 bits. The address and output signal CS4 * indicates a valid value during a bus cycle. The read signal RD * is set to the active level in synchronization with the fall of the clock φ in the T1 state (the rise of the clock φ2), and is returned to the inactive level in synchronization with the fall of the clock φ in the T3 state.
[0062]
(3) 16-bit bus in area 5, 3-state access, address multiplex access
The bus cycle timing of the read and write operations in this case is shown in FIGS. In this case, the row address is output to A10 to A1 in the T1 state, and the column address is output to A10 to A1 in the T2 and T3 states. The output signals CS5 *, RD *, HWR *, and LWR * are set to the active level in synchronization with the fall of the clock φ in the T1 state, and returned to the inactive level in synchronization with the fall of the clock φ in the T3 state. It is. The column address strobe signal CAS * is set to the active level in synchronization with the fall of the clock φ in the T2 state, and is returned to the inactive level in synchronization with the fall of the clock φ in the T3 state.
Similarly to the above, read / write is performed using even-numbered data using the upper data bus and odd-numbered data using the lower data bus. HWR * is activated in response to the even address write, and LWR * is activated in response to the odd address write.
[0063]
(4) 16-bit bus in area 6, 2-state access
The bus cycle timings of the read and write operations in this case are shown in FIGS. In this case, data at even addresses is read / written using the upper data bus, and data at odd addresses is read / written using the lower data bus. An RD * or HWR * output signal is activated in response to an even address read / write, and an RD * or LWR * output signal is activated in response to an odd address read / write. Read is controlled collectively by 16 bits. Writing is controlled in byte units. Address and output signal CS6 * is made active during the bus cycle. The output signals RD *, HWR *, and LWR * are set to the active level in synchronization with the fall of the clock φ in the T1 state, and are returned to the inactive level in synchronization with the fall of the clock φ in the T3 state.
[0064]
(5) 8-bit bus in area 7, 3-state access
The bus cycle timing of the read and write operations in this case is shown in FIGS. In this case, read / write is performed using the upper part of the data bus. That is, the signal RD * or HWR * is selectively activated. The address and output signal CS7 * is activated during a bus cycle. The output signal RD is set to the active level in synchronization with the fall of the clock φ in the T1 state, and is returned to inactive in synchronization with the fall of the clock φ in the T3 state. The output signal HWR * is set to an active level in synchronization with the rise of the clock φ in the T2 state, and is returned to inactive in synchronization with the fall of the clock φ in the T3 state.
As shown in FIGS. 14 and 15, when a bus master such as the CPU 2 or the DMAC 3 accesses word data, byte access is performed twice in the order of even addresses and odd addresses.
[0065]
FIG. 16 is a block diagram showing an example of the bus controller 4 for generating the various bus access timings as described above.
The bus controller 4 includes an address decode circuit 40, a control circuit 41, a bus right arbitration circuit 42, a selection circuit 43, a timing control circuit 44, a control register 45, a command register 46, and an address register 47. The control register 45 includes the registers BSWCR, ASTCR, WSCRA-B, MPXCR, CMDCR, and CNTL. The command register 46 includes the registers WCMD and CDAT0 to CDATA1. The address register 47 includes the registers BADR0 to BADR3. FIG. 16 representatively shows, as functions included in the input / output port, an input / output buffer, multiplexers 47 and 48, and an output buffer. 47 is an address multiplexer, and 48 is a data multiplexer.
[0066]
The bus right arbitration circuit 42 controls which of the CPU 2 and the DMAC 3 uses the bus. For example, when a data transfer activation factor occurs in the DMAC 3 and the DMAC bus request signal is set to an active level such as 1 level, the bus arbitration circuit 42 transmits the bus to the DMAC 3 at a predetermined timing designated by the timing control circuit 44. The use is permitted, and the DMAC bus right permission signal is set to an active level such as 1 level and returned to the DMAC 3. At other times, the CPU 2 has the bus right. Similarly, when the DMAC 3 has the bus right and the CPU 2 regains the bus right, it is performed by the CPU bus right request signal and the CPU bus right permission signal. Based on this control, the CPU 2 and the DMAC 3 can exclusively use the address / data bus.
[0067]
The selection circuit 43 selects a bus control signal output from the CPU 2 and the DMAC 3, for example, a read signal RD, a write signal HWR, LWR, bus size information, etc., based on an instruction from the bus right arbitration circuit 42, and sends it to the timing control circuit 44. give. That is, if the DMAC bus right grant signal is at level 1, the bus control signal from the DMAC 3 is given to the timing control circuit 44, and the bus control signal from the CPU 2 is given to the timing control circuit 44 otherwise. No matter which of the CPU 2 and the DMAC 3 has the bus right, the internal operation of the bus controller 4 is basically the same.
[0068]
The address decode circuit 40 decodes which area the address output from the CPU 2 or DMAC 3 to the address bus IAB corresponds to. The decoding result is output from a predetermined terminal via an output buffer as an area selection signal.
The control circuit 41 determines which area is selected based on the output of the address decode circuit 40, and determines which bit of the control register 45 is to be referred to. The determination result is given as an instruction to the timing control circuit 44.
The timing control circuit 44 generates a bus cycle based on the output of the control circuit 41, and outputs internal and external bus control signals. It also indicates the operation timing of the input / output buffer, multiplexer, and bus arbitration circuit. Further, when the bus cycle generated by this is a command write bus cycle or the like, the command register 46 is selected by the control signal DATASEL or CDATSEL as necessary.
[0069]
The address multiplexer 47 included in the output buffer selects a row address and a column address and selects the contents of the address bus IAB and the registers BADR0 to BADR3 included in the address register 47 according to the instruction of the timing control circuit 44.
The data multiplexer 48 included in the input / output buffer selects whether to input / output data on the data bus IDB or to output the contents of the registers WCMD and CDAT0 to CDATA1 included in the command register 46. Note that the timing control circuit 44 enables only a byte write for an 8-bit bus and only a word write for a 16-bit bus with respect to generation of a write cycle.
[0070]
FIG. 17 shows a specific first circuit example of the timing control circuit 44.
FIG. 18 shows an example of the operation timing chart of FIG.
In the circuit example of FIG. 17, the logical configuration of the block erase and polling functions is omitted for easy understanding of the contents. In other words, this circuit example focuses on a configuration for automatically generating and inserting a bus cycle for command writing by write access to a predetermined area. Also, this circuit example is shown by positive logic.
[0071]
The RD + WR signal is an internal signal for activating a bus for a read operation or a write operation by the CPU 2 or the DMAC 3, and is an output of the selection circuit 43. BUS8A, ST3A, and CMDA are signals obtained by decoding the address by the address decoding circuit 40, and are signals generated from the area and the corresponding bits of the BSWCR, ASTCR, and CMDCR registers. That is, the signals BUS8A, ST3A, and CMDA indicate that the area to be accessed at that time is an 8-bit bus area, a 3-state access area (the total number of states is greater than the number of wait states, and a command valid area). Something is indicated by a high level. The internal signal WR is used as a bus start internal signal for a write operation. WORD is a signal obtained by decoding an address by the address decode circuit 40, and is set to a high level in the case of word access. Both the WR and WORD signals are outputs of the selection circuit 43.
[0072]
The bus cycle is basically composed of two states. If there are three or more states, a wait state is inserted after the T1 state. (If a wait state is inserted, the wait state is referred to as a T2 state for convenience, and the next state is referred to as a T3 state. Write). The wait request signal wait includes a wait request by the registers WSCRA and WSCRB and a wait request by the wait signal WAIT supplied to the external terminal in the case of the three-state access area. That is, the external wait signal WAIT is converted into a wait request signal wait through the flip-flops FF7 to FF9 each of which includes three serial D-type latches. Regarding the programmable waits by the registers WSCRA and WSCRB, a wait request signal wait is generated according to the contents of the registers WSCRA and WSCRB. Note that, in any of the wait requests, the signal ST3A is set to the high level during the wait period. However, the signal ST3A is not set to a high level at all unless the register ASTCR specifies that the signal ST3A is not a two-state access area.
[0073]
The clock φ1B is a logical sum signal of the wait request signal wait and the clock φ1, the clock φ2B is an AND signal of the inverted signal of the wait request signal wait and the clock φ2, and the clock φ1B is at the high level during the wait. , The clock φ2B is fixed at the low level, and the flip-flops FF1 to FF4 maintain the state because the clock input does not change.
The signal DATASEL is a signal for selecting whether to output the command held by the register WCMD or to output the contents of the data bus IDB.
[0074]
The selection circuit SEL receives as inputs the outputs of flip-flops FF1, FF2, and FF3 composed of a series-connected three-stage D-type latch circuit to which the bus start signal RD + WR is supplied to the first stage via the OR gate OR1. . Also includes φ1 and φ2 synchronization circuits. The selection circuit SEL outputs the various bus timing signals. That is, output waveforms of the area selection signals CS0 * to CS7 *, the address strobe signal AS *, the read signal RD *, the write signals HWR * and LWR *, the column address strobe signal CAS *, and the timing of address multiplexing are generated. Output.
For example, the waveform of the read signal RD * is an inverted signal of the output signal of the second flip-flop FF2. When the corresponding bit of the register MPXCR is set to “1”, the area selection signal is an inverted signal of the logical product signal of the address decode result and the flip-flop FF2.
[0075]
Bus start signal RD + WR is applied to timing control circuit 44 in synchronization with system clocks φ1 and φ2 before the start of a bus cycle. The flip-flop FF1 outputs a signal in synchronization with the rising of the clock φ1B in the T1 state. Similarly, flip-flops FF2, FF3, and FF4 latch and output input signals in synchronization with the rise of clock φ2B in the T1 state, the rise of clock φ1B in the T2 state, and the rise of clock φ2B in the T3 state, respectively. The latch operation of the flip-flop FF4 is synchronized with the rise of the clock φ2 in the T3 state after the release of the wait. For example, in the case of word access to the 8-bit bus area (BUS8A and RD are at high level), or in the case of a data access cycle following the command cycle (the flip-flop FF6 is set), the first bus cycle Is completed, the output of FF4 is set to the high level, and this output is fed back to the flip-flop FF1 via the OR gate OR1, and is latched by the FF1. That is, activation of the second bus cycle is instructed.
[0076]
The first bus cycle or the second bus cycle is designated by RS (reset / set) type fifth and sixth flip-flops FF5 and FF6. The flip-flop FF5 is set in the first bus cycle and is set in the second bus cycle. The set state of the flip-flop FF5 is substantially meaningful when the signal WORD is at a high level meaning word access and the flip-flop FF10 is latching it, and the word access is not performed. This is when the operation is performed via the 8-bit bus (the signal BUS8A is at a high level). The flip-flop FF6 is set to a set state in the case of a command cycle, that is, when writing to the command valid area (WR and CMDA are at high level) and when the signal BRKAK is at inactive low level, and the flip-flop FF4 is at high level. It is reset by output.
[0077]
The signal BRKAK considers the case where the microcomputer 1 is used for emulation, and is a signal indicating that the CPU 2 is in a break state. When the signal BRKAK is set to the high level as the active level, insertion of a command cycle is prohibited, and after the break, the address space of the microcomputer is switched from the address space for the target program to the control space for evaluation. In this case, a write cycle is automatically inserted to eliminate the possibility that data is undesirably rewritten. Details on this point will be described later.
[0078]
As described above, the timing control circuit 44 of FIG. 17 first performs word access using an 8-bit bus, and secondly, when writing to the command valid area (WR and CMDA are high level) and the signal BRKAK is inactive. In the case of an instructed command cycle, a predetermined bus cycle is continuously generated twice.
[0079]
FIG. 19 shows a second specific example of the timing control circuit 44. In this circuit example, in order to make the contents easy to understand, FIG. 17 exclusively shows the logical configuration of the block erasing and polling functions, which are omitted. Also, this circuit example is of positive logic. 19, the same signals and circuit elements as those in FIG. 17 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0080]
The timing control circuit 44 shown in FIG. 7 exclusively shows a configuration for automatically starting a predetermined bus cycle by writing of the CPU 2 into the register CNTL. The signal REGCLR is a signal for clearing the contents of the register CNTL to end the automatically generated bus cycle. According to this example, two bus cycles are automatically generated for erasing a block in the flash memory, and one bus cycle is automatically generated for polling. The high-level output of the flip-flop FF4 is used as a start signal of the second cycle, and the flip-flop CFF4 controls the signal REGCLR to a high level at the timing when the automatically generated bus cycle ends. The flip-flop CFF5 and the NAND gate NAND1 use FF4 in the first cycle in two command write cycles for block erase and use CFF4 in the second cycle, and use only CFF4 in the bus cycle for polling. To control.
[0081]
The timing control circuit 44 shown in the figure receives a POL bit set signal SETPOL from the register CNTL. This SETPOL signal is made valid in synchronization with the rise of the clock φ2 in the T3 state of the write cycle for the register CNTL. However, the set signal of the POL bit is valid only when the RE bit is set to “1”. The logical product signal of the SETPOL signal and the RE signal is supplied as a start signal to the OR gate OR2, which is latched by the flip-flop FF1, and following the internal register write cycle, a polling read cycle to the outside is performed. Be started. The polling read cycle is recognized by the POL bit being set. The address at this time is not particularly limited, but is the address specified by the register BADR0.
[0082]
At this time, the signal RDY / BUSY * (referred to as a ready input signal READY) from the flash memory input to the ready terminal READY of the microcomputer 1 is supplied to the flip-flop FF7 as a signal equivalent to an external wait signal WAIT. . That is, if the flash memory is operating internally, the ready input signal READY is set to the inactive low level. Therefore, until the internal operation of the flash memory is terminated and the input signal READY is set to the active high level, the micro input is performed. The computer 1 is in a wait state. That is, during this time, the levels of the clocks φ1B and φ2B are fixed, and the latch operation of the flip-flop FF3 is suppressed. When the input signal READY is set to the active level and the wait is released, the bus cycle is completed through the T3 state of the polling read cycle. At the end, the signal REGCLR is set to the high level.
[0083]
The timing control circuit 44 is supplied with the logical sum signal SETBE of the set signals of BE0 to BE3 bits from the register CNTL. This signal SETBE becomes valid in synchronization with the rise of the clock φ2 in the T3 state of the write cycle of the register CNTL. This signal SETBE is also supplied to the OR gate OR2 as a bus start signal. Further, it is input to the reset terminal of the flip-flop CFF5. Further, a logical sum signal BEOR signal of BE0 to BE3 bits is supplied to one input of a NAND gate NAND1. An inverted signal of the output of the flip-flop CFF5 is supplied to the other input of the NAND gate NAND1. In a state where the block erase of the flash memory is instructed by writing to the register CNTL, the output of the NAND gate NAND1 is set to the low level. Therefore, at the end timing of the first cycle in the command write cycle for block erase, the output of the flip-flop FF4 is set to the high level, and the flip-flop FF1 starts the second command write bus cycle. Is indicated. At the same time, the flip-flop CFF5 is set to the set state, and the data input operation of the flip-flop CFF4 is enabled. Therefore, at the end timing of the second command write cycle, the flip-flop CFF4 latches the output of FF3 and sets the signal REGCLR to high level, thereby ending the automatic generation of the bus cycle.
[0084]
FIG. 20 shows operation timings related to the automatic generation of the command write cycle for the block erase.
Using the signal SETBE as a start signal, a command write cycle is started following the write cycle of the CPU 2 for the register CNTL. That is, the flip-flop FF1 latches the activation signal, and the flip-flop CFF5 is reset. The address at this time is the address specified by the registers BADR0 to BADR3. The designation of the registers BADR0 to BADR3 is performed according to the state of the BE0 to BE3 bits of the register CNTL.
[0085]
In the first command cycle, CFF5 is in the reset state, BEOR is at the high level, and FF4 is set in synchronization with the rise of clock φ2 in the T3 state. Using this as a start signal, the second command cycle is started, FF1 latches the start signal, and CFF5 is set.
[0086]
In the second command cycle, CFF5 is set and FF4 is controlled so that data cannot be input. On the other hand, the CFF 4 becomes ready for data input, and the register clear signal REGCLR is set to the high level in synchronization with the rise of the clock φ2 in the T3 state. As a result, the BE0 to BE3 bits that have caused the activation of the current command write cycle are cleared.
[0087]
The command written to the flash memory at that time is the contents of the registers CDAT0 and CDATA1, and the output of the registers CDAT0 and CDATA1 is selected by the signal CDATSEL output from the CFF5. When CFF5 is in the reset state, the contents of the register CDAT0 are output, and when CFF5 is in the set state, the contents of the CDAT1 register are output. The internal bus is a 16-bit bus, and the same data is output to the upper 8 bits and lower 8 bits of the command data. In the 8-bit bus mode, lower 8 bits of data are not output to the external data bus.
The BE0 to BE3 bits and the POL bit can set only one arbitrary bit to “1”, and it is prohibited to set a plurality of bits to “1” at the same time.
[0088]
Although the specific configuration of the timing control circuit 44 has been described separately in FIGS. 17 and 19, the timing circuit is actually realized by combining the circuits in FIGS. 17 and 19. In the case of combining, for example, the flip-flops FF1, FF2, FF3, FF7, FF8, FF9 and the clock system are shared, other circuit elements are separately provided, and the path is selected according to the operation mode. It can be easily realized by a known method of leading a signal from a circuit element to a common circuit element through an OR circuit.
[0089]
The flash memory can be connected to the outside of a single-chip microcomputer as a semiconductor integrated circuit device, or can be built in. For example, like the cell-based IC, the system in FIG. 5 can be made into one semiconductor integrated circuit, and the size of the system can be reduced.
In this case, the register that can set an arbitrary value can be omitted. That is, for the user of such a cell-based IC, which memory is connected to which area can be fixedly determined, and it is not necessary to arbitrarily set a register. For example, BSWCR, ASRCR, WSCRA-B, MPXCR, CMDCR, etc. can be fixed. The outputs of these registers may be fixed to either "0" or "1". In addition to fixing the value of the register, those signal lines may be pulled up or down.
[0090]
In order to speed up the system, it is necessary to improve the processing speed of the CPU 2. To improve the processing speed of the CPU 2, it is necessary to increase the instruction fetch speed. Since the flash memory is slower than the SRAM, there is a limit in improving the instruction fetch speed. On the other hand, the SRAM cannot retain the stored contents when the system is stopped. Therefore, it is conceivable to operate with the program stored in the flash memory immediately after the reset, transfer the program to the SRAM, and execute the program on the SRAM after the transfer is completed.
Further, the vector address used at the time of exception processing of the microcomputer may be fixed in the address space of the CPU 2 such as area 0, for example. For this reason, even when a program on the SRAM is being executed, the program on the flash memory must be executed every time an exception process such as an interrupt occurs. In particular, in the case of interrupt processing and the like, the response time often needs to be shortened, which imposes a constraint on speeding up the system.
Therefore, when accessing the area 0 where the flash memory is arranged, the area selection signal CS0 * is set to the non-selection state, and instead, the area selection signal CS2 * of the area 2 where the SRAM is arranged is set to the selection state. It is a good idea. A case where this control is performed using the control bit CS0C will be described.
[0091]
FIG. 21 shows an example of a circuit configuration for the CS control.
The control bit CS0C is constituted by a flip-flop circuit FF20 to which one bit of the data bus is connected. After the reset, the control bit CS0C is cleared to "0". When a write is performed on the address where control bit CS0C exists, the contents of internal data bus PDB0 are stored. The contents of the address (IAB) output from the bus master such as the CPU 2 or the DMAC 3 are decoded, and ICS0 to ICS7 are generated. Since there is no direct relationship with areas other than areas 0 and 2, illustration is omitted in FIG. 21 except for ICS0 and ICS2.
[0092]
When the control bit CS0C is cleared to "0", when the area 0 is accessed, that is, when ICS0 is at the high level which is the selection level and ICS2 is at the low level which is the non-selection level, the area selection signal CS0 is at the selection level. A certain high level is set to a low level which is a non-selection level.
When the control bit CS0C is set to "1", when the area 0 is accessed, that is, when ICS0 is at the high level which is the selection level and ICS2 is at the low level which is the non-selection level, the area selection signal is reversed. CS0 is set to a low level which is a non-selection level, and CS2 is set to a high level which is a selection level.
Regardless of the state of the control bit CS0C, at the time of area 2 access, CS0 is inactivated and CS2 is activated. The area selection signal CS0 * output to the outside is an inverted signal of the signal CS0, and the area selection signal CS2 * output to the outside is an inverted signal of the signal CS2.
[0093]
FIG. 22 shows a modification of the printer system to which the speed-up method described in FIG. 21 is applied.
FIG. 23 shows an address map in the system of FIG.
In the system of FIG. 22, an SRAM 17 is added to FIG. The SRAM 17 is a memory that is used by receiving a program and tuning information stored in the flash memory 10 and is arranged in the area 2. The same circuit blocks as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0094]
In such a system, immediately after the reset, the operation is first started by the program on the flash memory 10. Area 0 has three states and area 2 has two states. The contents of the flash memory 10 in the area 0 are copied to the SRAM 17 in the area 2. For example, DMAC3 may be used. Thereafter, the control bit CS0C is set to "1". When the address of the area 0 is accessed by the CPU 1 or the DMAC 3, CS0 * is set to inactive and CS2 * is set to active level. The access attributes are the same as in area 2. That is, the logical address of CPU 1 is area 0, while the physical address is area 2. Since the contents of the area 0 and the area 2 are common, no malfunction occurs even when the physical address is changed. A program or the like is stored in the low-speed flash memory 10, and the program or the like is transferred to the high-speed SRAM 17 during operation, so that the data processing speed can be increased. For example, since the program fetch can be speeded up by a factor of 1.5, the overall processing speed is also increased accordingly.
[0095]
Due to the characteristics of the flash memory 10, it is conceivable that information unique to the system user is accumulated. In this case, the contents are transferred from the SRAM 17 to the flash memory 10 at the end of the operation of the system. DMAC3 can be used for this. For example, the input signal READY of the microcomputer 1 can be used as a transfer request signal of the DMAC 3. That is, when writing back the contents of the SRAM 17 to the flash memory 10, the change of the signal RDY / BUSY * to the active level (ready state) indicating the end of writing in units of words or pages by the flash memory 10 is used as the input signal READY. Each time the microcomputer 1 receives the signal, the signal is processed as a DMAC 3 transfer request signal. In order to make this signal a transfer request signal, the port should be set so that the port receiving the signal READY is led to the DMAC3 as the DMAC3 transfer request signal.
[0096]
Such processing is enabled because the bus controller 4 can automatically add a command write bus cycle to the flash memory 10 in both access by the CPU 2 and access by the DMAC 3.
Note that the above-described transfer to the SRAM 17 can be applied to a device other than the flash memory 10. For example, only the program for the initialization operation may be stored in the mask ROM 12, and another program may be transferred from the secondary storage such as a floppy disk to the SRAM 17 in the area 4. The high-speed memory may be an SRAM or a synchronous DRAM.
[0097]
FIG. 24 is a block diagram when the microcomputer 1 is applied to an emulation microcomputer.
The emulation microcomputer 50 includes a microcomputer portion 51 and an emulation interface 52 including a buffer circuit (not shown) and the like, and is formed on one semiconductor substrate by a known semiconductor manufacturing technique.
[0098]
The emulation microcomputer 50 has a user interface 53 for transmitting and receiving signals to and from an application system of a single-chip microcomputer corresponding to the microcomputer portion 51. The emulation interface 52 transmits and receives signals to and from an emulator and a system development device (not shown).
24, circuit blocks having the same functions as those of the single-chip microcomputer of FIG. 1 are denoted by the same reference numerals. 24, the user interface 53 includes the input / output circuits PIO1 to PIO9 of FIG. The circuit block indicated by I / O in FIG. 24 includes the timer 7 and the SCI 8 in FIG.
[0099]
As an emulation bus, IAB and IDB are input and output via an emulation interface 52. The buses PAB and PDB are not directly connected to the emulation interface 52 as emulation buses. As a result, the number of terminals of the emulation microcomputer can be reduced, which contributes to a reduction in the size of the package and, consequently, the size of the emulator.
[0100]
A status signal CMDCYC indicating that the command cycle is automatically added is output to an emulator or the like via the emulation interface 52. In the command cycle automatically added, the CMDCYC signal is set to the active level. The CMDCYC signal can be, for example, a logical sum signal of the DATASEL, BEOR, and POL signals. In addition, the emulation interface 52 includes a break request terminal BRK and the like.
When the CPU 2 receives the break interrupt, the break acknowledge signal BRKAK is set to the active level, and the state transits to a control program execution state for emulation. When the return instruction is executed, the BRKAK signal becomes inactive and transits to the user program execution state.
During the break mode, automatic bus cycle insertion (bus command) such as a command write cycle is prohibited. The emulator memory and the user flash memory are arranged at the same address, and the emulator memory can be used in the break mode, and the user flash memory can be used in the user mode. It is desirable that the emulator memory be constituted by a RAM in accordance with the purpose of storing a program to be debugged. By issuing a write cycle as a bus command to the RAM, it is possible to prevent the contents of the RAM from being destroyed.
[0101]
FIG. 25 is a block diagram showing an example of the emulator.
The connector section 60 is mounted on an application system (user system) 61 instead of a single-chip microcomputer. The emulation microcomputer 50 inputs and outputs signals to and from the application system 61 via the connector section 60 and the interface cable 62.
[0102]
The emulation microcomputer 50 is connected to an emulation bus 63 using the emulation interface 52. The emulation bus 63 includes various signal lines such as a status signal, a control signal, data, and an address. Using the emulation bus 63, information and the like according to the internal state of the application system 61 and the emulation microcomputer 50 are output from the emulation microcomputer 50, and the emulation microcomputer 50 is provided with information for emulation. Various control signals are input. An emulation mode terminal (not shown) of the emulation microcomputer 50 is fixed at the power supply level, and the emulation mode is set inside the emulation microcomputer 50.
[0103]
The emulation bus 63 includes, but is not limited to, an emulation memory 64 such as a RAM for substituting the built-in memory of the application system 61 or the target microcomputer, the control state of the emulation microcomputer 50, and the emulation bus 63. When the state reaches a preset state, a break interrupt is requested as an interrupt exclusive to the emulator, execution of the user program by the CPU 2 is stopped, and the execution state of the control program for emulation is monitored. And a break control circuit 65 for causing the CPU 2 to make a transition (break) to the emulation bus 63 based on a signal indicating a read operation or a write operation of the CPU 2 and a signal indicating an instruction read operation. Less and data further such as real-time trace circuit 66 for storing the control information sequentially are connected. The real-time trace circuit also sequentially stores the signal CMDCYC.
[0104]
The emulation memory 64, the break control circuit 65, and the real-time trace circuit 66 are also connected to a control bus 67, and are controlled by a control processor 68 via the control bus 67. The control bus 67 is connected via a host interface 69 to a system development device 70 such as, but not limited to, a personal computer. For example, the program input from the system development device 70 is transferred to the emulation memory 64, and the CPU 2 reads the program to be arranged on the external program ROM or, if the ROM is incorporated, to be arranged on the internal ROM. Then, the program on the emulation memory 64 is read. In addition, a break condition, a real-time trace condition, and the like can also be given from the system development device 70. The system development device 70 can display the result traced by the real-time trace circuit 66 on a display screen such as a CRT or a liquid crystal.
[0105]
On the emulator system, a normal bus cycle and an automatically added bus cycle can be clearly distinguished. That is, the state of the CMDCYC signal obtained corresponding to the bus cycle can be displayed or distinguished. Alternatively, it is possible to selectively display only the normal bus cycle or only the automatically added bus cycle. This can be done by the processing of the system development device 70 selecting whether or not to display the corresponding bus cycle according to the accumulated information of the CMDCYC signal. By automatically deleting the added bus cycle, the execution of the program corresponds to the bus cycle, so that the program can be easily debugged. In addition, by displaying only the automatically added bus cycle, the execution state of the bus command can be easily traced. The emulator can easily interpret the bus command and display the contents of the command as well as the bus information. If the CMDCYC signal is at the active level and the data at that time is H'20, H'B0, "block erase" is displayed on the display screen. Thus, the program can be easily debugged without the need for the user to sequentially confirm the contents of the command.
[0106]
Here, the flash memory 10 will be schematically described. The flash memory 10 includes a memory array in which flash memory cells (hereinafter, also simply referred to as memory cells) each formed of an insulated gate field effect transistor having a two-layer gate structure are arranged in a matrix. Although not particularly limited, a control gate of each flash memory cell is connected to a corresponding word line (not shown), a drain of each flash memory cell is connected to a corresponding data line (not shown), and a source of each flash memory cell is provided for each memory block. Connected to common source line.
[0107]
The operation of writing information to the memory cell is realized by, for example, applying a high voltage to the control gate and the drain and injecting electrons from the drain side to the floating gate by avalanche injection. Due to this write operation, the threshold voltage of the flash memory cell as viewed from its control gate is higher than that of the erased memory cell in which the write operation has not been performed.
[0108]
On the other hand, the erasing operation is realized by, for example, applying a high voltage to the source and extracting electrons from the floating gate to the source side by a tunnel phenomenon. By the erase operation, the threshold voltage of the storage transistor as viewed from its control gate is lowered. The threshold value of the memory cell transistor is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the writing state is increased and the threshold voltage in the erasing state is decreased with respect to the word line selection level applied from the word line to the control gate. With such a relationship between the two threshold voltages and the word line selection level, a memory cell can be constituted by one transistor without using a selection transistor.
[0109]
In the read operation, the voltage applied to the drain and the control gate is set to a relatively low value so that weak writing to the flash memory cell, that is, undesired carrier injection to the floating gate is not performed. Limited. For example, a low voltage of about 1 V is applied to the drain, and a low voltage of about 5 V is applied to the control gate. By detecting the magnitude of the channel current flowing through the memory cell transistor based on these applied voltages, the logical values “0” and “1” of the information stored in the memory cell can be determined.
[0110]
According to the above embodiment, the following effects can be obtained.
(1) The microcomputer 1 having an external bus has a bus controller 4 for selectively controlling a memory or the like connected to a part or all of the address space in the address space, and requires a command write by its internal register CMDCR. When a bus master such as the CPU 2 or DMAC 3 reads / writes an area in the address space where the flash memory 10 is selected, a command corresponding to the read / write can be designated. The write cycle is inserted by the timing control circuit 44 of the bus controller 4 so that the flash memory 10 can be connected with a minimum load of software.
(2) By setting the bus width and the number of bus cycles in the registers BSWCR, ASTCR, WSCRA, WSCRB, various memories can be directly connected without the need for an external circuit.
(3) By automatically inserting a command during a read / write operation, a bus master such as the DMAC 3 that performs only data transfer can perform data transfer control with the flash memory 10 like an SRAM or the like. .
(4) The memory can be directly connected by outputting the area selection signal. By changing the output condition of the area selection signal as described with reference to FIG. 21, it is possible to relocate the memory and the like in the address space of the CPU 2 without changing the physical system. . Thus, when the contents stored in the low-speed nonvolatile memory are transferred to the high-speed volatile memory and the operation is performed, it can be dealt with only by changing the output condition of the area selection signal.
(5) In the microcomputer for emulation, by outputting a signal CMDCYC indicating a bus cycle performed by the bus master or a bus cycle automatically inserted by the bus controller, and by the emulator distinguishing and displaying these. Thus, the debugging efficiency can be improved.
(6) In the emulation microcomputer, when the external memory is not used (break mode), the emulation memory can be protected by prohibiting the bus controller from automatically inserting a bus cycle.
[0111]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention.
[0112]
For example, the bus master may be a CPU, a DMAC, a data transfer controller, or a digital signal processor (DSP). Any data processing device that can read / write a memory using a bus may be used. It may have three or more bus masters. Any number of data processing devices can be incorporated in one semiconductor integrated circuit. It goes without saying that the present invention can be applied to the DMAC and the DSP itself. The external circuit whose operation is instructed by the command is not limited to the flash memory. If it is a memory, it may be, for example, a synchronous DRAM.
[0113]
The details of the bus specification can be variously changed. For example, the bus width may be 16/32 bits or 8/16/32 bits in addition to the selection of 8/16 bits. When using a 32-bit bus, four 8-bit commands may be output in parallel. The address and the bus size may be determined, and the command may be output only to a predetermined bus.
[0114]
At the time of reset, a manual reset and a power-on reset may be provided, and at the time of manual reset, the contents of the register of the bus controller may be held. Further, a reset command may be output prior to the operation of the CPU.
[0115]
The specific circuit configuration of the bus control circuit can be variously changed. The configuration of the control register and the like can be variously changed. The register for storing the command can be written at any time by the CPU, or may be fixed. The method of dividing the area may be in units of 128 kbytes. The size of the area may be continuously changeable. It may not be possible to set attributes for all divided areas. When the address space is widened, it is desirable that each area does not become large. It is not desirable that the capacity be larger than the available memory capacity. If the number of divided areas is large or the terminals of the microcomputer are not sufficiently large, it is not necessary to output an area selection signal for all areas.
The other functional blocks of the single-chip microcomputer are not restricted at all.
[0116]
In the above description, the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the application field in which the invention is based, has been described. However, the present invention is not limited to this. The present invention can be applied to a system and an emulator, and at least the present invention can be applied to a data processing device that can use an external bus.
[0117]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0118]
That is, when a predetermined address space allocated to an external circuit such as a flash memory is accessed, a first command write cycle for writing a command instructing the operation of the external circuit is performed prior to the access. Can be inserted automatically. This makes it unnecessary to write a command each time a byte or page is written to the flash memory and to write a program that defines the process.
[0119]
When a predetermined bit of the internal control register is operated by the CPU, a second command write cycle for writing a command instructing the operation of the external circuit can be automatically inserted after the operation. Thus, even when a command write divided into multiple times such as a block erase write to a flash memory is required, the instruction description may specify writing to the control register and the like. The size can be reduced.
[0120]
An external read cycle for polling control can be started and maintained by the CPU by operating a predetermined bit of a built-in control register, which also improves data processing efficiency and reduces program size in terms of generating external bus cycles. Can be realized.
[0121]
In consideration of emulation, the data processing device outputs a signal indicating whether the bus cycle is performed by the bus master or the bus cycle automatically inserted by the bus controller, so that the debugging efficiency can be improved.
[0122]
When emulation is taken into consideration, emulation memory can be protected by prohibiting the automatic insertion of the bus cycle in the break mode.
[0123]
Even if the bus master means is a direct memory access controller, the direct memory access controller can use such a command format flash memory as a data transfer source or a data transfer destination by automatically inserting the command write cycle.
[0124]
The interface with the flash memory whose operation is instructed by the command can be simplified and the usability can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a single-chip microcomputer that is an embodiment of a data processing device according to the present invention.
FIG. 2 is an explanatory diagram of an example of an address map of the microcomputer of FIG. 1;
FIG. 3 is an explanatory diagram of a bus control register.
FIG. 4 is an explanatory diagram of another bus control register.
FIG. 5 is a block diagram showing an example of a printer system using the single-chip microcomputer shown in FIG. 1;
6 is an explanatory diagram of an example of a connection state by an external bus 16 in the system of FIG.
FIG. 7 is an example bus cycle timing diagram of a 16-bit bus in area 0 and a read operation in 3-state access and a read in area 4 in 16-bit bus and 3-state access.
FIG. 8 is an example bus cycle timing diagram of a write operation in a 16-bit bus of area 0 and three-state access;
FIG. 9 is a bus cycle timing diagram showing an example of a write operation in a 16-bit bus and three-state access in area 4;
FIG. 10 is a bus cycle timing diagram showing an example of a read operation in a 16-bit bus, 3-state access, and address multiplex access of an area 5;
FIG. 11 is a bus cycle timing diagram showing an example of a write operation in a 16-bit bus, three-state access, and address multiplex access of an area 5;
FIG. 12 is an example bus cycle timing chart of a read operation in a 16-bit bus and two-state access in area 6;
FIG. 13 is an example bus cycle timing diagram of a write operation in a 16-bit bus and two-state access in area 6;
FIG. 14 is an example bus cycle timing diagram of an 8-bit bus in area 7 and a read operation in three-state access;
FIG. 15 is an example bus cycle timing diagram of a write operation in an 8-bit bus and three-state access in area 7;
FIG. 16 is an example block diagram of a bus controller.
FIG. 17 is an example circuit diagram of a timing control circuit included in the bus controller.
18 is an example operation timing chart of the circuit of FIG. 17;
FIG. 19 is a circuit diagram illustrating another example of a timing control circuit included in the bus controller;
20 is an example operation timing chart relating to automatic generation of a command write cycle for block erasure in the circuit of FIG. 19;
FIG. 21 is an example circuit diagram for CS control.
FIG. 22 is a block diagram showing an example of a printer system to which the circuit shown in FIG. 21 is applied.
FIG. 23 is an explanatory diagram of an example of an address map in the system of FIG. 22;
FIG. 24 is an example block diagram of an emulation microcomputer.
FIG. 25 is a block diagram illustrating an example of an emulator.
FIG. 26 is an explanatory diagram of an example of a command of the flash memory.
[Explanation of symbols]
1 Single-chip microcomputer
2 CPU
3 DMAC
4 Bus controller
BSWCR Register for specifying bus width of each area
ASTCR, WSCRA, WSCRB Register for specifying bus cycle of each area
MPXCR Register for specifying the address multiplex of each area
CMDCR Command cycle area register to be automatically generated
Register for storing WCMD, CDATA0, CDATA1 command
BADR0-BADR3 Address storage registers
CNTL Command bus cycle insertion condition specification register
10 Flash memory
11 DRAM
12 Mask ROM
13,17 SRAM
44 Timing Control Circuit
50 Emulation microcomputer

Claims (14)

A data processing device having a built-in bus master means capable of using an external bus and being connectable to an external circuit whose operation is instructed by a command. Bus control means for generating a first command write cycle for writing a command for instructing the operation of the external circuit to the predetermined address space, prior to generation of an external bus access cycle corresponding to the instruction. ,
The bus control means includes: an address space determining means for determining an address space corresponding to an access address by the bus master means; an address space specifying means for specifying an address space in which a first command write cycle is to be started; A match determining unit that determines whether the address space determined by the space determining unit matches the address space specified by the address space specifying unit; and an address space determined by the address space determining unit. Timing control means for generating an external bus access cycle and generating the first command write cycle in response to a match determination result by the match determination means.
The data processing apparatus, wherein the address space determining means is allowed to determine a predetermined address space that can be specified by the address space specifying means as another address space according to a value of a rewritable control bit. . It said bus control means, the data processing apparatus according to claim 1, characterized in that comprising a command storage means for holding rewritable command to be written by the first command write cycle. The bus master means includes a CPU, and the bus control means includes a control register means and a second register for writing predetermined command data to a predetermined address space by operating the first bit of the control register means. 3. The data processing device according to claim 1, further comprising timing control means for generating a command write cycle. 4. The data processing apparatus according to claim 3 , wherein said bus control means further comprises address storage means for holding an address to be output in a second command write cycle. The bus control means generates an external read cycle for performing polling control for waiting for a change in a signal input from a predetermined external terminal by operating a second bit of the control register means by the CPU. The data processing device according to claim 3 , wherein the data processing device is provided. Bus cycle for the outside of any one of claims 1 to 5, characterized in that comprising further includes emulation interface for outputting an identification signal indicating whether the said command write cycle Data processing device. 4. The data processing apparatus according to claim 3, wherein the CPU outputs a control signal for inhibiting generation of the first command cycle by the bus control means based on a predetermined external interrupt. It said bus master means, the data processing apparatus of any one of claims 1 to 6, characterized in that a direct memory access controller. The external circuit data processor of any one of claims 1 to 8, characterized in that a flash memory. The data processing apparatus, data processing apparatus according to any one of claims 1 to 9, characterized in that it is formed on a single semiconductor chip. Data processing system, characterized in that the data processing device of any one of claims 1 to 8, those comprising and an the external circuit connected to the data processing device. The data processing system according to claim 11 , wherein the data processing device and the external circuit are formed on different semiconductor chips. A data processing device according to claim 7, and an emulator,
The data processing device further includes an emulation interface for outputting an identification signal indicating whether a bus cycle to the outside is the command write cycle,
The emulator is coupled to the emulation interface included in the data processing apparatus has a trace memory and break control circuit, the trace memory accumulates to input the identification signal with the bus information of the data processing device, The data processing system, wherein the break control circuit outputs a break signal to the data processing device as the interrupt signal when the control state of the data processing device reaches a preset state. A data processing device incorporating a bus master means capable of using an external bus and being connectable to a flash memory whose operation is instructed by a command,
In response to an instruction to access an external predetermined address space by the bus master means, to instruct the operation of the flash memory to the predetermined address space prior to generation of an external bus access cycle corresponding to the access instruction. A bus control means for generating a command write cycle for writing a command of the type described above, and an external input terminal for a signal indicating the internal operation state of the flash memory designated by the command write, and formed on one semiconductor substrate;
The bus control means includes: an address space determining means for determining an address space corresponding to an access address by the bus master means; an address space specifying means for specifying an address space in which a first command write cycle is to be started; A match determining unit that determines whether the address space determined by the space determining unit matches the address space specified by the address space specifying unit; and an address space determined by the address space determining unit. Timing control means for generating an external bus access cycle and generating the first command write cycle in response to a match determination result by the match determination means.
The data processing apparatus, wherein the address space determining means is allowed to determine a predetermined address space that can be specified by the address space specifying means as another address space according to a value of a rewritable control bit. .

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