JP3631209B2 - Flash with consistent latency in read processing - Google Patents

Flash with consistent latency in read processing Download PDF

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Publication number
JP3631209B2
JP3631209B2 JP2001573488A JP2001573488A JP3631209B2 JP 3631209 B2 JP3631209 B2 JP 3631209B2 JP 2001573488 A JP2001573488 A JP 2001573488A JP 2001573488 A JP2001573488 A JP 2001573488A JP 3631209 B2 JP3631209 B2 JP 3631209B2
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data
memory
read
input terminal
status
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JP2003529883A (en
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ルーパーバー、フランキー、エフ.
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マイクロン テクノロジー インコーポレイテッドMicron Technology, Inc.
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Priority to US19350600P priority Critical
Priority to US60/193,506 priority
Priority to US09/567,733 priority patent/US6615307B1/en
Priority to US09/567,733 priority
Application filed by マイクロン テクノロジー インコーポレイテッドMicron Technology, Inc. filed Critical マイクロン テクノロジー インコーポレイテッドMicron Technology, Inc.
Priority to PCT/US2001/010040 priority patent/WO2001075896A2/en
Publication of JP2003529883A publication Critical patent/JP2003529883A/en
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    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
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    • GPHYSICS
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    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
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    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
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    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
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    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
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    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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    • G11INFORMATION STORAGE
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile memory, and more particularly, to a synchronous nonvolatile flash memory.
[0002]
Background of the Invention
Usually, a memory device is provided for an internal storage area of a computer. The term “memory” refers to an integrated circuit chip used as a data recording medium. There are several types of memory. For example, a RAM (random-access memory) is used as a main memory of a computer. The RAM is a readable / writable memory. That is, data can be written to the RAM and data can be read from the RAM. In contrast, the ROM is a memory that can only read data. Many of the RAMs are volatile and require a holding current to maintain the state in which the content is stored. When the power is turned off, the data recorded in the RAM is lost.
[0003]
Most computers have a small-capacity ROM in which instruction codes for starting the computer are recorded. Unlike RAM, writing to ROM is not possible. An EEPROM (electrically erasable programmable read-only memory) is a special nonvolatile memory that can erase data (electrically) by applying a charge. Like other ROMs, EEPROM is not inherently as fast as RAM. The EEPROM includes a large number of memory cells, and each memory cell has a plurality of electrically insulated gates (floating gates). Data is recorded in the memory cell in accordance with the presence / absence of charge in the floating gate. Charges are supplied to or removed from the floating gate by programming or erasing.
[0004]
Another example of the nonvolatile memory is a flash memory. The flash memory is a kind of EEPROM, and data erasure and program update are performed not in units of bytes but in units of blocks. Many of the recent personal computers record the BIOS in a flash memory chip, and the BIOS can be easily updated as necessary. Such a BIOS is also called a flash BIOS. Flash memory is often used for modems. By using flash memory, when a new protocol is standardized, the firmware provided by the modem manufacturer can be updated to allow the modem to support this protocol.
[0005]
Usually, the flash memory includes a memory array, and the memory array is composed of a large number of memory cells specified by row addresses and column addresses. Each memory cell is provided with a field effect transistor that has a floating gate and holds electric charge. These cells are divided into groups in block units. Each cell in the block can be electrically and randomly programmed by applying a charge to the floating gate. The accumulated charge is extracted from the floating gate by an erase process in units of blocks. Cell data is determined by the presence or absence of charge in the floating gate.
[0006]
A synchronous DRAM (SDRAM) is a DRAM that operates at a higher speed than a conventional DRAM memory. The SDRAM operates in synchronization with the CPU bus. The SDRAM operates at 100 MHz, which is about three times the frequency of a conventional FPM (Fast Page Mode) RAM and about twice the frequency of an EDO (Extended Data Output) DRAM or a BEDO (Burst Extended Data Output) DRAM. SDRAM can be accessed at high speed but is volatile. Many computer systems are designed to operate using SDRAM, but the use of non-volatile memory is also expected.
[0007]
For the reasons described above or described below, there is a need in the art for a non-volatile memory device that operates in the same manner as an SDRAM. These reasons will be apparent to those skilled in the art by understanding the contents described in the specification.
[0008]
Summary of the Invention
The present invention is for solving the above-described problems of the memory device, and can be understood by examining the following description.
[0009]
In one embodiment, the present invention provides a non-volatile synchronous flash memory that is compatible with existing SDRAM package pinouts. From the detailed description, it will be apparent that any system designer having knowledge of the SDRAM field can readily implement the present invention to improve system processing.
[0010]
In one embodiment, a synchronous memory device includes a pipeline buffer having an input terminal and an output terminal. The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminal to the output terminal, and each transmission path requires a predetermined number of clock cycles. The memory includes a multiplexer circuit connected to the input terminal of the pipeline buffer. The multiplexer circuit includes a first input terminal and a second input terminal. The data register circuit is connected to the first input terminal of the multiplexer circuit, and the data read circuit is connected to the second input terminal of the multiplexer circuit. The data read circuit outputs data read from the memory array of the synchronous memory device.
[0011]
In another embodiment, the processing system includes a memory controller and a synchronous flash memory device connected to the memory controller. The memory controller receives memory cell data from the synchronous flash memory device after a first predetermined number of clock cycles have elapsed since the memory controller provided the memory column address. The memory controller also receives status data from the synchronous flash memory device after a second predetermined number of clock cycles have elapsed since the memory controller made a status read request. The first predetermined number of clock cycles and the second predetermined number of clock cycles are the same.
[0012]
A method for reading data from a synchronous flash memory is provided. The method includes the steps of starting a memory cell read process and outputting memory cell data in response to the memory cell read process. The memory cell data is output to the data connection terminal after a predetermined number of clock cycles have elapsed since the memory cell read process was started. The method includes the steps of starting a status reading process and outputting status data in response to the status reading process. The status data is output to the data connection terminal after a predetermined number of clock cycles have elapsed since the status read processing started.
[0013]
DESCRIPTION OF THE PREFERRED EMBODIMENT
Embodiments of the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings constitute a part of this specification and exemplify specific embodiments of the present invention. Each of the embodiments has been fully described so that those skilled in the art may practice the invention. It will be understood that the invention may be practiced with logical, mechanical and electrical changes without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be construed in a limiting sense. The scope of the present invention is defined only by the claims.
[0014]
The following detailed description is divided into two main items. In the first item (function description of the interface), compatibility with the SDRAM memory is described in detail. In the second item (function description), functional commands in the flash architecture are defined.
[0015]
Functional description of the interface
FIG. 1A is a block diagram showing an embodiment of the present invention. Memory device 100 includes an array of non-volatile flash memory cells 102. This array is arranged in a plurality of banks that can be addressed. In the present embodiment, four memory banks 104, 106, 108, 110 are included in the memory. Each memory bank includes a plurality of addressable sectors consisting of memory cells. Data stored in the memory can be accessed by using the location address. This location address is supplied externally and received by the address register 112. The address is decoded by the row address multiplexer 114. The address is also decoded by bank control logic 116 and row address latch / decoder 118. In order to be able to access the desired column in the memory, the column address counter / latch 120 combines the received addresses and outputs them to the column decoder 122. The circuit 124 functions as an input / output gate, a data mask logic, a read data latch, and a write driver. Data is input through the data input register 126 and output through the data output register 128. The command execution logic 130 controls the basic operation of the memory device. The state machine 132 also controls specific processing performed on the memory array and cells. Further, a status register 134 and an ID register 136 are provided for data output.
[0016]
FIG. 1B shows a connection pin array (input / output connector pin assignment) according to an embodiment of the present invention. The memory package 150 has 54 connection pins. The pin configuration is almost the same as that of the existing SDRAM package. The two unique connection pins of the present invention are RP # 152 and Vccp154. The present invention uses the same connection pin label as that of the SDRAM, but in this specification, the function of signals input / output through the connection pin is not the same as that of the SDRAM unless otherwise described. FIG. 1C illustrates a memory package 160 in one embodiment. The memory package 160 has connection terminals by bumps instead of connection terminals by pins. Accordingly, the present invention is not limited to a particular package configuration.
[0017]
Before describing the processing characteristics of the memory device, the connection pins and signals input / output through the connection pins will be described. The input clock terminal supplies a clock signal (CLK). The clock signal is driven by the system clock. All the input signals of the synchronous flash memory are sampled at the rising edge (positive edge) of CLK. CLK also increases the count value of the internal burst counter and further controls the output register.
[0018]
The input clock enable (CKE) terminal is used to make the CLK signal input active (activated HIGH state) and inactive (not activated LOW state). By deactivating the clock input, POWER-DOWN_STANDBY processing (all memory banks become idle), ACTIVE_POWER-DOWN processing (memory row becomes ACTIVE in any bank), or CLOCK_SUSPEND processing (burst / Access is ongoing). CKE is in a synchronized state except when the memory device is in a power down mode. When the memory device is in power down mode, CKE is in an asynchronous state. The input buffer such as CLK is disabled in the power down mode and is in a standby state with low power consumption. CKE may be maintained in a HIGH state in the system when power down mode is not required except when RP # is deep power down.
[0019]
A signal for enabling / disabling a command decoder provided in the command execution logic is input to the chip select (CS #) input terminal. If the signal is LOW, the command decoder is enabled, and if the signal is HIGH, the command decoder is disabled. That is, if CS # is HIGH, all commands are masked. Further, when there are a plurality of banks in the system, the bank can be selected from the outside by CS #. Therefore, CS # can be regarded as part of the command code. However, this CS # is not essential.
[0020]
Connection terminals RAS #, CAS # and WE # for inputting input commands (together with CAS # and CS #) define commands executed by the memory, as will be described later. The input / output mask (DQM) terminal is used to input a mask signal for write access and to output an enable signal for read access. If the DQM sampled during the WRITE cycle is HIGH, the input data is masked. When the DQM sampled during the READ cycle is HIGH, the output buffer becomes a high impedance (High-Z) state after the latency of 2 clocks has elapsed. DQML corresponds to data terminals DQ0 to DQ7, and DQMH corresponds to data terminals DQ8 to DQ15. DQML and DQMH are considered to be in the same state when referred to as DQM.
[0021]
The address input unit (connection terminal) 133 is mainly used for inputting an address signal. In the illustrated embodiment, the memory has 12 lines (A0-A11). Further, as will be described later, another signal may be input through the address terminal. When an ACTIVE command (row addresses A0 to A11) or a READ / WRITE command (column addresses A0 to A7) is issued in order to select a location in the memory bank, the signal at the address input section is sampled. The address input unit is also used to input a processing code (OpCode) during a LOAD_COMMAND_REGISTER process described later. The address lines A0 to A11 are used for inputting mode settings during the LOAD_MODE_REGISTER process.
[0022]
The input reset / power down (RP #) terminal 140 is used to perform reset processing and power down processing. In one embodiment, when the device is started up (initial device power-up), after RP # goes from LOW to HIGH, before issuing an executable command, for initial operation inside the device, A delay time of 100 μs is required. When the RP # signal becomes LOW, the status register is cleared and the state machine (ISM) 132 in the device is set to the array read mode. Also, the device goes into deep power down mode. By powering down, all input terminals including CS # 142 are set to “Don't Care” and all outputs are in a High-Z state. When the RP # signal becomes the same as the VHH voltage (5 V), all protection modes are canceled during the WRITE process and the ERASE process. The device protection bit is set to “1 (protection mode)” by the RP # signal, but when the RP # signal becomes VHH, each of the block protection bits existing at the locations 0 and 15 of the 16-bit register is set. , “0 (unprotected mode)” is set. The protection bit will be described later. In all other processing modes, RP # is maintained HIGH.
[0023]
Bank address input terminals BA0 and BA1 define which bank is to issue an ACTIVE command, a READ command, a WRITE command, or a BLOCK_PROTECT command. The DQ0 to DQ15 terminals 143 are data bus connection terminals used for bidirectional data communication. The VCCQ terminal shown in FIG. 1B is used to supply power to the DQ terminal that is insulated from the VCC terminal so that it is less susceptible to noise interference. In one embodiment, VCCQ = Vcc, ie 1.8V ± 0.15V. The VSSQ terminal is used as a ground that is insulated from the VSS terminal with respect to the DQ terminal so as to be less susceptible to noise interference. The VCC terminal is for supplying 3V power, for example. Connection to ground is made through the Vss terminal. Further, another option voltage may be supplied through the VCCP terminal 144. The VCCP terminal is connected to the VCC terminal outside the device, and supplies a current used for the initial operation of the device, the WRITE process, and the ERASE process. That is, the memory device writing process and erasing process are performed using the voltage supplied through the VCCP terminal, and all other processes are performed using the voltage supplied through the VCC terminal. The Vccp terminal is connected to the high voltage switch / pump circuit 145.
[0024]
Hereinafter, a more detailed description of the operation of the synchronous flash memory will be given. One embodiment of the present invention relates to a programmable ROM that is nonvolatile, can electrically erase (flash) data in units of sectors, and is programmable. This memory has a data capacity of 67, 108, 864 bits configured as 4,194,304 words in 16-bit units. Other data capacities may be used, and the present invention is not limited to the data capacities shown as examples. Each memory bank is comprised of four separately erasable blocks. That is, there are a total of 16 blocks. The memory contains 16 blocks that can be locked by hardware and software to prevent accidental erasure and overwriting and to protect important firmware, and each block has a data capacity of 256K words Have Since the memory includes four banks, true parallel processing can be realized.
[0025]
A read access to a bank can be performed when a WRITE process or an ERASE process is being performed on another bank in the background. The synchronous flash memory has a synchronous interface and can register all signals on the rising edge of the clock signal CLK. Further, reading of the memory can be performed in a burst mode. That is, memory access is started from the selected location, and the number of locations to be accessed is preprogrammed. Memory access is performed according to a preprogrammed sequence. Read access begins with the registration of the ACTIVE command and continues with the READ command. The address bits registered simultaneously with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered at the same time as the READ command are used to select the column location and bank where burst access is to start.
[0026]
Synchronous flash memory provides a programmable read burst length corresponding to one location, two locations, four locations, eight locations, or a full page. An optional burst termination may be provided. The synchronous flash memory adopts an internal pipeline architecture in order to achieve high-speed processing. The synchronous flash memory operates in a low power memory system, for example, a system driven by 3V. As an operation mode of the memory, a deep power down mode is provided as a power saving standby mode. All inputs and outputs are compatible with LVTTL (low voltage transistor-transistor logic). The synchronous flash memory can greatly improve the flash processing performance. Here, the flash processing performance includes an ability to transfer data at high speed while automatically generating a column address, and an ability to randomly switch the column address every clock cycle during a burst access period.
[0027]
Generally, a synchronous flash memory is driven at a low voltage and has the same configuration as a DRAM having a plurality of banks. Each bank is composed of a plurality of rows and a plurality of columns. The synchronous flash memory is initialized before normal processing is performed. Hereinafter, device initialization, register definition, command contents, and device operation will be described in detail.
[0028]
The synchronous flash is powered up by a predetermined method and initialized. When power is supplied to VCC, VCCQ, and VCCP (simultaneously), the clock signal becomes stable and RP # 140 changes from the LOW state to the HIGH state. In order to complete initialization inside the device, for example, a delay time of 100 μs is required after RP # shifts to the HIGH state. After the delay time elapses, the memory enters the array read mode, and the mode register can be programmed or a command can be executed. After initial programming to the non-volatile mode register (NV mode register) 147, content is automatically loaded into the volatile mode register during the initialization process. The device starts in a pre-programmed state (power-up), and does not need to reload the non-volatile mode register 147 again before issuing a processing command. This will be described later.
[0029]
The mode register 148 is used to define a specific processing mode of the synchronous flash memory. This definition includes selection of burst length, burst type, CAS latency, and processing mode, as shown in FIG. The mode register performs programming based on the LOAD_MODE_RESISTOR command, and holds the stored information until reprogramming is performed. The contents of the mode register may be copied to the NV mode register 147. Based on the setting of the NV mode register, the mode register 148 is automatically loaded during the initialization process. Details of the ERASE_NVMODE_REGISTER command and the WRITE_NVMODE_REGISTER command will be described later. Those skilled in the art will understand that in SDRAM, the mode register needs to be externally loaded for each initialization process. According to the present invention, the default mode setting is registered in the NV mode register 147. The contents of the NV mode register are copied to the volatile mode register 148 and accessed while each process is being performed in memory.
[0030]
Mode register bits M0-M2 define the burst length. The mode register bit M3 defines a burst type (sequential or interleave). Mode register bits M4-6 define CAS latency. Mode register bits M7 and M8 define the processing mode. Mode register bit M9 is set to 1. Mode register bits M10 and M11 are reserved in the present embodiment. In this embodiment, since a WRITE burst is not executed, M9 is set to logic 1, and a write access is performed in one location (non-burst). The mode register needs to be loaded when all banks are idle. The controller must wait for a predetermined time before starting subsequent processing.
[0031]
Read access to the synchronous flash memory is performed in the burst mode. The burst length is programmable as shown in Table 1. The burst length defines the maximum number of column locations that can be automatically accessed by a given READ command. Whether the burst type is sequential or interleaved, it has a burst length corresponding to one location, two locations, four locations, and eight locations. When the burst type is sequential, the burst length corresponding to the full page can be used. If the burst length is a full page, an arbitrary burst length may be created using the BURST_TERMINATE command. That is, the burst length can be customized by selectively ending the burst. When the READ command is issued, a block including a number of columns corresponding to the burst length can be selected. All accesses performed in this burst mode are performed within the selected block. In other words, the block is continuously accessed until the boundary is reached. When the burst length is set to 2, the block is independently selected by A1 to A7. When the burst length is set to 4, a block is selected by A2 to A7. When the burst length is set to 8, a block is selected by A3 to A7. The remaining lower address bits (including the least significant bit) are used to select a starting position within the block. Full page bursts are accessed continuously within the page until the boundary is reached.
[0032]
Accesses made within a given burst are programmed to sequential or interleaved burst types by bit M3. As shown in Table 1, the order of access within a burst is determined by the burst length, burst type, and start column address.
[0033]
[Table 1]
[0034]
CAS (Column Address Strobe) latency indicates a delay time in clock cycles until the first output data can be used at the DQ terminal after the READ command is registered. Latency can be set to 1, 2, or 3 clock cycles. For example, when a READ command is registered at clock edge n and the latency is m clocks, data can be used at clock edge n + m. The DQ connection unit starts driving data at the clock edge one cycle before (n + m−1), and when the access time is appropriate, valid data is obtained at the clock edge n + m. For example, assuming that the clock cycle time is set so that the access time is appropriate, when the READ command is registered at T0 and the latency is 2 clocks, as shown in FIG. Data drive is started after T1, and valid data is obtained at T2. FIG. 3 shows an example of the operation period when different clock latency settings are used. The normal processing mode is selected by setting M7 and M8 to zero. A preprogrammed burst length is applied to the READ burst.
[0035]
The following truth table shows the processing commands of the memory of the present invention in more detail. Each command and truth table 2 will be described.
[0036]
[Table 2]
[0037]
[Table 3]
[0038]
The COMMAND_INHIBIT function inhibits new commands from being executed by the synchronous flash memory regardless of whether the CLK signal is valid. Although the synchronous flash memory is in a non-selected state, it does not affect processing that is already being executed.
[0039]
The NO_OPERATION (NOP) command is used to execute NOP on the synchronous flash memory selected with CS # set to LOW. By executing the NOP, it is possible to prevent an unwanted command from being registered during the idle state or the standby state. However, it does not affect processing that is already being executed.
[0040]
Data for the mode register is loaded through input terminals A0-A11. Only when all the array banks are in an idle state, a LOAD_MODE_REGISTER command is issued. After a predetermined delay time (MRD) has elapsed, a command for processing to be executed next is issued. The data held in the NV mode register 147 is automatically loaded as default data into the mode register 148 at the time of power-on initialization (upon power-up initialization) unless dynamically changed by the LOAD_MODE_REGISTER command. The
[0041]
The ACTIVE command opens (activates) a particular array bank row so that it can be accessed. A bank is selected by input values from the input terminals BA0 and BA1, and a row is selected by an address input from the input terminals A0 to A11. This line remains active for access until the next ACTIVE command, power-down command, or RESET command is registered.
[0042]
The READ command is used to initiate a read access in burst mode for the active row. A bank is selected by input values from the input terminals BA0 and BA1, and a start column location is selected by an address input from the input terminals A0 to A7. The read data on the DQ terminal depends on the logic level on the data mask (DQM) input terminal two clocks before. When the registration of the given DQM signal is HIGH, the corresponding DQ terminal after 2 clocks becomes High-Z (high impedance). If the registration of the given DQM signal is LOW, the DQ terminal holds valid data. Therefore, the output data can be masked using the DQM input terminal during the read process.
[0043]
The WRITE command is used to initiate a write access made at one location in the active row. Before issuing the WRITE command, it is necessary to issue a WRITE_SETUP command. A bank is selected by input values from the input terminals BA0 and BA1, and a column location is selected by an address input from the input terminals A0 to A7. Input data on the DQ terminal is written to the memory array. The input data depends on the logic level of the DQM input that appears simultaneously with the input data. If the registration of the given DQM signal is LOW, the corresponding data is written into the memory. If the registration of the DQM signal is HIGH, the input of the corresponding data is ignored, and the WRITE process at the word / column location to be written is not executed. If a WRITE command is issued and the DQM signal registration is HIGH, it is considered that a NOP command has been issued.
[0044]
The ACTIVE_TERMINATE command is not essential for the synchronous flash memory, but can be used to end the reading process in the same manner as the SDRAM PRECHARGE command. The ACTIVE_TERMINATE command is issued to end the BURST_READ being executed, but may be issued to a specific bank or may not be issued to a specific bank.
[0045]
The BURST_TERMINATE command is used to truncate a burst over a fixed length or full page. The READ command registered immediately before registering the BURST_TERMINATE command is truncated. The BURST_TERMINATE command is not issued to a specific bank.
[0046]
The load command register process is used to start outputting a flash memory control command to the command execution logic (CEL) 130. The CEL receives and decodes commands for the device. This command controls the operation of the internal state machine (ISM) 132 and the read path (that is, the memory array 102, the ID register 136, or the status register 134).
[0047]
Before a READ command or a WRITE command for a bank is issued in the synchronous flash memory, a row to be processed in this bank needs to be “opened (activated)”. As shown in FIG. 4, this is performed by an ACTIVE command defined by CS #, WE #, RAS #, and CAS #, and both banks and rows to be activated are selected.
[0048]
After issuing an ACTIVE command to open a line, a READ command or a WRITE command is issued for this line. The time until the READ command or WRITE command is issued is determined based on a predetermined period (tRCD specification). A value obtained by dividing tRCD (MIN) by a clock cycle is rounded up to an integer. Based on this integer, after the ACTIVE command is issued, the first clock edge at which the READ command or the WRITE command is issued is obtained. For example, if the specification of tRCD is 30 ns and the clock is 90 MHZ (11.11 ns clock period), the calculated value is 2.7 clocks and is rounded up to “3”. In this case, that is, a case of 2 <tRCD (MIN) / tCK ≦ 3 is shown in FIG. it can).
[0049]
Issuing the next ACTIVE command for different rows in the same bank can be performed without closing the previously activated row if the minimum interval between successive ACTIVE commands for this bank is defined by tRCD.
[0050]
The next ACTIVE command for another bank can be issued while the first bank is being accessed. Thus, the total overhead in row access can be reduced. The minimum interval between successive ACTIVE commands for different banks is defined by the period tRCD.
[0051]
The READ burst is started by a READ command defined by CS #, WE #, RAS #, and CAS # shown in FIG. The start column and bank address are selected by the READ command. A valid data output element (data-out element) from the address of the start column can be used after the CAS latency has elapsed after the READ command is issued during the READ burst. Each subsequent data output element is valid at the next positive clock edge. If no other command is started after the end of the burst, the DQ terminal is in a HIGH-Z state. Full page bursts are continuously executed until the end (return to column 0 at the end of the page and processing continues). Data from the READ burst is truncated when the next READ command is issued. Immediately following the data from the fixed length READ burst, the data from the next READ command follows. In either case, a continuous data flow is maintained. The first data element of the new burst is the last data element of the finished burst or, if the burst is longer than a fixed length (truncated halfway), follows the last desired data element . A new READ command is issued x cycles before the clock edge when the last desired data element is valid. x is one less than the CAS latency. In FIG. 7, when CAS latency is 1, 2, and 3, data element n + 3 is the end of four bursts or the end of a burst longer than a fixed length. Since the synchronous flash memory employs a pipeline architecture, the 2n rule is not required unlike the prefetch architecture. The READ command can be started in any clock cycle after the previous READ command. The highest speed random read access within the page is performed as shown in FIG. Each subsequent READ process may be performed on a different bank.
[0052]
Data from the READ burst is truncated by the next WRITE command. It is necessary to execute WRITE_SETUP before the WRITE command. Immediately following the data from the fixed length READ burst, the data from the next WRITE command follows. The WRITE command is subject to bus turnaround restrictions. If I / O contention can be avoided, the WRITE process begins at the clock edge immediately following the last (last desired) data element from the READ burst. Depending on the design of the system, the device that drives the input data may become Low-Z before the DQ terminal of the synchronous flash memory becomes High-Z. In this case, a delay of at least one cycle occurs between the last read data and the WRITE command.
[0053]
The DQM input is used to avoid input / output contention shown in FIG. The DQM signal is asserted (HIGH) at least 2 clocks before the WRITE command (DQM latency for the output buffer is 2 clocks), and data output from READ is suppressed. When the WRITE command is registered, the DQ terminal becomes High-Z (or maintains the High-Z state) regardless of the state of the DQM signal. Before the WRITE command (DQM latency for the input buffer is zero clock), the DQM signal must be deasserted and the write data masked. FIG. 9 shows a case where the clock frequency is set so that bus contention can be avoided without adding a NOP cycle.
[0054]
Fixed-length or full-page READ bursts are truncated by either the ACTIVE_TERMINATE command (which may or may not be for a specific bank) or BURST_TERMINATE command (not for a specific bank) . The ACTIVE_TERMINATE command and BURST_TERMINATE command are issued x cycles before the clock edge in which the last desired data element is valid. x is one less than the CAS latency. This is illustrated in FIG. 10 for each of the different CAS latencies. Data element n + 3 may be the last desired data element of the four bursts or the last desired data element in a burst longer than a fixed length.
[0055]
The WRITE process at one location is started by a WRITE command defined by CS #, WE #, RAS #, and CAS # shown in FIG. The start column and bank address are selected by the WRITE command. When the WRITE command is registered, the READ command is executed as defined by truth tables 4 and 5. An example is shown in FIG. During the WRITE process, valid data input (data-in) is registered simultaneously with the WRITE command.
[0056]
Unlike SDRAM, synchronous flash memory does not require a PRECHARGE command to deactivate an open row in a specific bank or in all banks. The ACTIVE_TERMINATE command is similar to the BURST_TERMINATE command, but the ACTIVE_TERMINATE command may or may not be for a specific bank. If the input A10 is asserted and is HIGH during the execution of the ACTIVE_TERMINATE command, BURST_READ ends in any bank. If the input A10 is LOW during execution of the ACTIVE_TERMINATE command, which bank is to be ended is designated by BA0 and BA1. ACTIVE_TERMINATE is considered to be a NOP for a bank not addressed by A10, BA0, BA1.
[0057]
Power down occurs when the clock enable CKE matching NOP or COMMAND_INHIBIT is registered LOW when no access is taking place. When power-down occurs, the input buffer and output buffer become inactive except for CKE after processing by an internal state machine including WRITE processing. That is, the power saving mode is set to the standby state.
[0058]
The power-down state ends when NOP or COMMAND_INHIBIT is registered and CKE becomes HIGH (satisfies tCKS) at a desired clock edge. FIG. 13 shows an example of the power-down process.
[0059]
When the CKE terminal is registered LOW during execution of column access / burst, the clock suspend mode is set. In the clock suspend mode, the internal clock becomes inactive and the synchronous logic “freezes”. When CKE is sampled low at the rising edge of each clock, the next rising edge of the internal clock is suspended. When the internal clock edge is suspended, commands and data held at the input terminal are ignored. As long as the clock is suspended, as shown in the example of FIG. 14, the data held by the DQ terminal maintains its driven state, and the burst counter is not incremented. The clock suspend mode is terminated when the CKE terminal is registered as HIGH, and the processing by the internal clock is resumed at the rising edge of the next clock.
[0060]
The burst read / single write mode is the default mode in one embodiment. All of the WRITE commands generate an access (single burst) at a single column location, and the READ command generates an access to each column according to a preprogrammed burst length and sequence. The following truth table 3 shows memory processing using the CKE signal.
[0061]
[Table 4]
[0062]
[Table 5]
[0063]
[Table 6]
[0064]
Feature Description
The synchronous flash memory has many functions and is optimal for applications that use code storage on the SDRAM bus and XIP technology (execute in place) technology. The memory array is subdivided into individual erase blocks. Data held in each block can be erased without affecting the data held in other blocks. Reading, writing, and erasing of these memory blocks can be executed by issuing commands to the command execution logic (CEL) 130. The CEL controls the processing of the internal state machine (ISM) 132. CEL performs all of ERASE_NVMODE_REGISTER processing, WRITE_NVMODE_REGISTER processing, WRITE processing, BLOCK_ERASE processing, BLOCK_PROTECT processing, DEVICE_PROTECT processing, UNPROTECT_ALL_BLOCKS processing, and VERIFY processing completely. The ISM 132 protects each memory location from being over-erased and optimizes data retention to the maximum at each memory location. In addition, the ISM greatly simplifies the control required to write a device in the system or to be written by an external programmer.
[0065]
The synchronous flash memory is composed of 16 separate erasable blocks. The data held in the memory block can be partially erased without affecting the data held in other memory blocks. The memory block may be protected from accidental data erasure or writing by hardware. When protecting a block, it is necessary to drive the voltage of the RP # terminal to VHH (relatively high voltage) before the data of the block is altered. Blocks having a capacity of 256K words at locations 0 and 15 may be provided with other hardware protection measures. Once the PROTECT command is executed for these blocks, the UNPROTECT_ALL_BLOCKS command cancels protection of all blocks other than location 0 and location 15 unless RP # is VHH. Thus, even when an unexpected power failure or system reset occurs when updating the firmware in the system, security for important codes is enhanced.
[0066]
Initialization at power-up, ERASE processing, WRITE processing, and PROTECT processing is simplified by using an ISM that controls all programming algorithms in the memory array. ISM protects data by preventing over-erasing and optimizes the write margin for each cell. During the WRITE process, the ISM automatically increments and monitors the number of WRITE process attempts, authenticates the write margin in each memory cell, and updates the ISM status register. When performing a BLOCK_ERASE process, the ISM automatically overwrites the entire address block to prevent over-erasure, increments and monitors the number of WRITE process attempts, and sets a bit in the ISM status register.
[0067]
The 8-bit ISM status register 134 causes the external processor 200 to monitor the status of the ISM during WRITE processing, ERASE processing, and PROTECT processing. Of the 8-bit status register, 1 bit (SR7) is completely set and cleared (cancel setting) by the ISM. This bit indicates whether the ISM is busy with ERASE processing, WRITE processing, or PROTECT processing. Further, other error information, that is, write protection block error, erase non-protection all block error, and device protection error are set by another three bits (SR3, SR4, SR5). Status register bits SR0, SR1 and SR2 provide detailed information on the processing of the ISM being executed. The user can confirm whether the ISM processing at the device level is in progress or whether the ISM processing at the bank level is in progress, and can also check which bank is controlled by the ISM. These six bits (SR3-SR5) must be cleared by the host system. The status register will be described in more detail with reference to Table 2.
[0068]
The CEL 130 receives and decodes commands for the device. Each command controls the ISM processing and read path (ie, memory array, device configuration, or status register). When the ISM is active, a command for CEL is issued.
[0069]
In order to enhance the power saving effect, the synchronous flash supports a deep power down mode with extremely low current. In order to enter this mode, it is necessary to set the RP # terminal 140 (reset / power down) to VSS ± 0.2V. To avoid accidental RESET, the device will not enter reset mode unless RP # is maintained at Vss for 100 ns. If RP # is maintained at Vss, the device enters deep power down mode. When RP # changes from LOW to HIGH after the device enters deep power down mode, a device startup initialization sequence is performed as outlined herein. Even if RP # changes from LOW to HIGH after entering the reset mode, if it is not in the deep power-down mode, a delay time of 1 μs is required before issuing an executable command. When the device enters deep power-down mode, all buffers except the RP # buffer are disabled, reducing the amount of current, for example up to 50 μA at 3.3V VCC. During deep power-down mode, the input to RP # must be maintained at Vss. When the RESET mode is entered, the status register 134 is cleared and the ISM 132 is set to the array read mode.
[0070]
According to the synchronous flash memory architecture, when the data of each sector is erased, the other portions of the array are not affected. The array is divided into 16 addressable “blocks” which can be erased separately. Since data can be erased in blocks, not in the entire array, the durability of the entire device and the flexibility of the system are improved. Only the ERASE function and the BLOCK_PROTECT function are executed in units of blocks. The 16 addressable blocks are equally divided into four banks 104, 106, 108, 110. That is, each bank 104, 106, 108, 110 consists of four blocks. For the four banks, one can be read simultaneously and the other can be written simultaneously. When a WRITE process or an ERASE process by ISM is performed for a certain bank, a READ process can be performed for another bank. By polling the status register 134, it is possible to determine for which bank the ISM processing is being executed. The synchronous flash memory includes an ISM that performs a single background process. The ISM controls initialization processing, ERASE processing, WRITE processing, and PROTECT processing at power-on. In any case, only one process by the ISM can be executed. However, other specific commands including READ processing can be executed while performing ISM processing. The processing command controlled by the ISM is bank level processing or device level processing. The WRITE process and the ERASE process are ISM processes performed at the bank level. When the ISM process performed at the bank level is started, invalid data is output in any bank regardless of the location where the READ process is performed. However, when the READ process is performed for another bank. , The array is read. When the READ_STATUS_REGISTER command is executed, the content held in the status register 134 is output. The ISM status bit indicates the end of the ISM process (SR7 = 1). When the ISM process ends, the bank automatically enters the array read mode. The ERASE_NVMODE_REGISTER process, the WRITE_NVMODE REGISTER process, the BLOCK_PROTECT process, the DEVICE_PROTECT process, and the UNPROTECT_ALL_BLOCKS process are ISM processes performed at the device level. Once the ISM processing performed at the device level is started, the content held in the array is output regardless of which bank is read. A READ_STATUS_REGISTER command is issued to determine the end of the ISM process. When SR7 = 1, the ISM process ends and the next ISM process is started. To protect the block data by preventing unintended ERASE processing or WRITE processing by the hardware circuit, drive RP # to VHH before the WRITE processing or ERASE processing is performed as described below. There is a need to.
[0071]
In order to increase security for the most important part of the firmware, the block data may be protected by hardware. While the WRITE or ERASE process is being performed on the block protected by hardware, that is, until the WRITE or ERASE process ends, RP # must be maintained at VHH. If RP # = VHH is not satisfied, the WRITE process or ERASE process for the protected block is prohibited, resulting in a write error or an erase error. Location 0 and 15 blocks have another hardware protection function to protect against unexpected WRITE or ERASE processing. In the present embodiment, when these blocks are not RP # = VHH, the protection cannot be canceled by software based on the issuance of the UNPROTECT_ALL_BLOCKS command. The protection status of the block can be confirmed by issuing a READ_STATUS_REGISTER command and reading the protection bit of the block. In order to protect the block, a command sequence of 3 cycles must be issued to the target block address.
[0072]
The synchronous flash memory supports three different modes of READ processing. Data is created from one of the memory array, status register, or device configuration register by READ processing according to the mode. The READ process for the device configuration register or status register is performed after the LCR-ACTIVE cycle. The burst length of the data output (data out) is defined by the setting of the mode register. The array is read by a READ process after the LCR-ACTIVE cycle or a READ process that is performed without requiring an LCR-ACTIVE cycle. However, since there are some variations in the read operation, it will be described in the following items.
[0073]
By executing the READ command for the bank, the contents of the memory array are output. While the WRITE process or the ERASE process by the ISM is being performed, invalid data is output regardless of the location in the bank under the control of the ISM. When the RESET process is finished, the device automatically enters the array read mode.
[0074]
In order to execute the READ process of the status register 134, an input sequence similar to that at the time of reading the array is necessary, but the LCR_READ_STATUS_REGISTER (70H) cycle must be before the ACTIVE READ cycle. The burst length of the data output (data out) by the status register is defined by the mode register 148. The content held in the status register is updated and latched at the next rising edge of the clock after the CAS latency has elapsed. The device automatically enters the array read mode and is ready for the next READ process.
[0075]
Reading the device configuration register 136 requires the same input sequence as reading the status register, but a specific address must be designated. WE # must be HIGH and DQM and CS # must be LOW. In order to read the manufacturer compatible ID, the address must be specified as 000000H. In order to read the device ID, the address must be specified as 000001H. The block protection bit is read at the third address location in each erase block (xx0002H), and the device protection bit is read from location 000003H.
[0076]
The DQ terminal is also used to input data to the array. The address terminal is used to specify an address location or to enter a command to the CEL during the LOAD_COMMAND_REGISTER cycle. By inputting a command, an 8-bit command is issued to the CEL, and the processing mode of the device is controlled. The WRITE process is used to input data to the memory array. Hereinafter, both input types will be described.
[0077]
In order to perform command input, DQM must be LOW and CS # and WE # must also be LOW. The address terminal and DQ terminal are used for inputting each command. Address terminals that are not used to enter commands must be “don't care” and remain in a state. The 8-bit command is an input to DQ0 to DQ7 or A0 to A7, and is latched at the rising edge of the clock.
[0078]
The desired bit is set to logic 0 by the WRITE process for the memory array, but the bit set to logic 0 cannot be changed to logic 1. Setting any bit to logic 1 erases the entire block of data. In order to perform WRITE processing, DOQ must be LOW, and CS # and WE # must also be LOW. Also, VCCP must be held in VCC. To write to the protected block, RP # needs to be set to VHH. A write address is designated by A0 to A11, and data to be written to the array is input to the DQ terminal. Data and addresses are latched on the rising edge of the clock. Before the WRITE process, it is necessary to issue a WRITE_SETUP command.
[0079]
In order to simplify the writing of the memory block, the ISM of the synchronous flash memory controls all the internal algorithms of the WRITE cycle and the ERASE cycle. An 8-bit command set is used to control the device. Truth tables 1 and 2 show a list of valid commands.
[0080]
By polling the 8-bit ISM status register 134 (Table 2), ERASE_NVMODE_REGISTER processing, WRITE_NVMODE_REGISTER processing, WRITE processing, ERASE processing, BLOCK_PROTECT processing, DEVICE_PROTECT processing, or UNPROTECT_ALL_BLOCK, It is checked whether an error has occurred during these processes. The end of the ISM process is monitored by issuing a READ_STATUS_REGISTER (70H) command. The contents of the status register are output to DQ0 to DQ7. After CAS latency elapses, the contents are updated by the fixed burst length defined by the setting of the mode register at the rising edge of the next clock. The ISM process ends when SR7 = 1. All blocks defined by bits are set by the ISM, but only the ISM status bits are reset by the ISM. The erase / unprotect block, write / protect block, and device protection must be cleared by the CLEAR_STATUS_REGISTER (50H) command. As a result, it is possible to select the timing at which the user polls and clears the status register. For example, the host system can check the status register after multiple WRITE processes are performed rather than checking the status register after each WRITE process is performed. The status register is also cleared by asserting the RP # signal and powering down the device.
[0081]
[Table 7]
[0082]
The device ID, manufacturer compatible ID, device protection status, and block protection status are all read by issuing a READ_DEVICE_CONFIGURATION (90H) command. In order to read the desired register, a specific address must be asserted. Details of the configuration registers 136 for various devices are shown in Table 3.
[0083]
[Table 8]
[0084]
A command for changing the processing mode of the device can also be issued. In each mode, processing specific to that mode is performed. In some modes, it is necessary to write a series of commands before performing the process. Hereinafter, the characteristics of each mode will be described. Truth tables 1 and 2 are lists of command sequences necessary to perform the desired processing. With the function of performing reading and writing at the same time, it is possible to perform reading processing on another bank while performing writing processing or erasing processing on a bank that is background processing. In the writing process, the LCR-ACTIVE-WRITE command sequence described in Truth Table 2 must be completed in successive clock cycles. However, in order to simplify the processing of the synchronous flash controller, the NOP command or the COMMAND_INHIBIT command is issued without limitation to the number during this command sequence. Furthermore, these command sequences must be assigned to the same bank address for three cycles in order to enhance the data protection function. When the bank address is changed during the LCR-ACTIVE-WRITE command sequence, or when the command sequence is not continuous (other than the NOP command and COMMAND_INHIBIT command that are allowed to issue commands during the command sequence) When a command is issued), a write status bit and an erase status bit (SR4 and SR5) are set, and processing is prohibited.
[0085]
After power-up (power-up), the synchronous flash memory is initialized before a processing command is issued to the device. After power is supplied to VCC, VCCQ, and VCCP (simultaneously), the clock stabilizes and RP # changes from LOW to HIGH. After RP # shifts to HIGH, a delay time (in one embodiment, a delay time of 100 μs) is required to complete initialization inside the device. When device initialization is complete, the device enters array read mode and an executable command is issued to the device.
[0086]
In order to read each of the device ID, manufacturer compatible ID, device protection bit, and block protection bit, a READ_DEVICE_CONFIGURATION (90H) command is issued. In this mode, a specific address is designated to read out desired information. The manufacturer compatible ID is read at 000000H. The device ID is read as 000001H. The manufacturer compatibility and device ID are output to DQ0 to DQ7. The device protection bit is read at 000003H. Each of the block protection bits is read at the third address location (xx0002H) in each block. The device protection bit and the block protection bit are output to DQ0.
[0087]
To enter data into the array, it is necessary to issue three consecutive commands on successive clock edges (NOP and COMMAND_INHIBIT commands are allowed to be issued during each cycle). In the first cycle, a LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with a WRITE_SETUP command (40H), and bank addresses are issued to BA0 and BA1. In the next cycle, an ACTIVE command is issued, the row address becomes active, and the bank address is confirmed. The third cycle is a WRITE command, and a start column, a bank address, and data are issued. After the CAS latency has elapsed, the ISM status bit is set at the next clock edge. While the ISM is executing the WRITE process, the ISM status bit (SR7) becomes zero. Under ISM control, invalid data is created when a READ process is performed on a bank. When the ISM status bit (SR7) is set to logic 1, the WRITE process ends, the bank enters the array read mode, and the command can be executed. Even when writing to a block protected by hardware, it is necessary to set RP # to VHH before executing the WRITE process in the third cycle. Until the WRITE process by ISM is completed, RP # # Must be held at VHH. If the LCR-ACTIVE-WRITE command sequence is not completed in successive cycles, or if the bank address is changed in any of the three cycles, the write status bit and erase status bit (SR4 and SR5) are set. Is done. When the ISM starts the WRITE process, the WRITE process will not be aborted unless a RESET process is performed or a power down is performed. If RESET processing is performed or power-down is performed, data being written may be destroyed in any case.
[0088]
Executing the ERASE sequence sets all bits in the block to logic one. The command sequence necessary for executing the ERASE process is the same as that for executing the WRITE process. In order to prevent unexpected block erasure and improve security, it is necessary to issue three consecutive commands at successive clock edges to start ERASE processing for a block. In the first cycle, a LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with an ERASE_SETUP command (20H), and bank addresses of blocks to be erased are issued to BA0 and BA1. In the next cycle, an ACTIVE command is issued, and the address of the block to be erased is designated by A10, A11, BA0, and BA1. In the third cycle, a WRITE command is issued, and in the meantime, an ERASE_CONFIRM command (D0H) is issued to DQ0 to DQ7, and a bank address is reissued. After the CAS latency has elapsed, the ISM status bit is set at the next clock edge. After the ERASE_CONFIRM command (D0H) is issued, the ISM starts ERASE processing for the block whose address is specified. When READ processing is performed on a bank in which a block with an address is specified, invalid data is output. When the ERASE process is completed, the bank enters the array read mode, and the command can be executed. Even when erasing a block protected by hardware, RP # needs to be set to VHH before executing the WRITE process, which is the third cycle, and the ERASE process by ISM ends (SR7 = 1). RP # must be held at VHH. If the LCR-ACTIVE-WRITE command sequence is not completed in successive cycles (NOP and COMMAND_INHIBIT commands are allowed to be issued during each cycle), or the bank address in one or more command cycles Is changed, the write status bit and the erase status bit (SR4 and SR5) are set, and the processing is prohibited.
[0089]
The contents of the mode register 148 may be copied to the NV mode register by a WRITE_NVMODE_REGISTER command. Before writing to the NV mode register, the ERASE_NVMODE_REGISTER command sequence must be terminated and all bits in the NV mode register must be set to logic one. The command sequence necessary for executing the ERASE_NVMODE_REGISTER process and the WRITE_NVMODE_REGISTER process is the same as that for executing the WRITE process. The detailed information about the LCR-ACTIVE-WRITE command necessary to complete the ERASE_NVMODE_REGISTER and WRITE_NVMODE_REGISTER processes is shown in Truth Table 2. After the WRITE cycle of the ERASE_NVMODE_REGISTER command sequence or the WRITE_NVMODEREGISTER command sequence is registered, a READ command is issued to the array. A new WRITE process is not permitted until the currently executed ISM process ends and SR7 = 1.
[0090]
By executing the BLOCK_PROTECT sequence, first level software / hardware protection for a given block can be performed. The memory has a 16-bit register that protects 16 blocks with one bit. The memory also includes a register that provides device bits for protecting the data of the entire device by preventing write processing and erasure processing. The command sequence necessary for executing the BLOCK_PROTECT process is the same as that for executing the WRITE process. To start the BLOCK_PROTECT process, three consecutive commands need to be issued to prevent unexpected block erases and increase security. In the first cycle, a LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with a PROTECT_SETUP command (60H), and bank addresses of blocks to be protected are issued to BA0 and BA1. In the next cycle, an ACTIVE command is issued, the row of the block to be protected is activated, and the bank address is confirmed. In the third cycle, a WRITE command is issued. During that time, a BLOCK_PROTECT_CONFIRM command (01H) is issued to DQ0 to DQ7, and a bank address is reissued. After the CAS latency has elapsed, the ISM status bit is set at the next clock edge. Then, the ISM starts the PROTECT process. If the LCR-ACTIVE-WRITE command sequence is not completed in successive cycles (NOP and COMMAND_INHIBIT commands are allowed to be issued during each cycle), or if the bank address is changed WRITE status bit and erase status bit (SR4 and SR5) are set, and processing is prohibited. When the ISM status bit (SR7) is set to logic 1, the PROTECT process ends, the bank enters the array read mode, and the command can be executed. Once the block protection bit is set to 1 (protection), this protection bit cannot be changed except by resetting it to 0 by the UNPROTECT_ALL_BLOCKS command. The UNPROTECT_ALL_BLOCKS command sequence is similar to the BLOCK_PROTECT command, but in the third cycle, the WRITE command is issued with the UNPROTECT_ALL_BLOCKS_CONFIRM command (D0H) and the address is specified as “don't care”. The truth table 2 further includes other information. In the blocks of locations 0 and 15, security is further increased. Once the block protection bits at locations 0 and 15 are set to 1 (protection), each bit sets RP # to VHH before the third cycle of UNPROTECT processing until BLOCK_PROTECT processing or UNPROTECT ALL_BLOCKS processing ends. (SR7 = 1) If not held at VHH, the bit is not reset to zero. Furthermore, if the device protection bit is set, RP # must be set to VHH before the third cycle and held at VHH until the BLOCK_PROTECT process or UNPROTECT_ALL_BLOCKS process ends. The protection status of the block is confirmed by issuing a READ_DEVICE_CONFIGURATION command (90H).
[0091]
When the DEVICE_PROTECT sequence is executed, the protection bit of the device is set to 1 to prevent the block protection bit from being changed. The command sequence necessary for executing the DEVICE_PROTECT process is the same as that for executing the WRITE process. Three consecutive command cycles are required to start the DEVICE_PROTECT sequence. In the first cycle, a LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with a PROTECT_SETUP command (60H), and bank addresses are issued to BA0 and BA1. The bank address is “don't care”, but the same bank address must be used for all three cycles. The next command is ACTIVE. The third cycle is a WRITE cycle. During the WRITE cycle, a DEVICE_PROTECT command (F1H) is issued to DQ0 to DQ7, and RP # becomes VHH. After the CAS latency has elapsed, the ISM status bit is set at the next clock edge. It is possible to issue an executable command to the device. RP # must be held at VHH until the WRITE process ends (SR7 = 1). Until the currently executed ISM process is completed, execution of a new WRITE process is not permitted. Once the device protection bit is set to 1, BLOCK_PROTECT processing and BLOCK_UNPROTECT processing cannot be executed unless RP # becomes VHH. The device protection bit does not affect the WRITE process or the ERASE process. Table 4 shows more detailed information about the block protection process and the device protection process.
[0092]
[Table 9]
[0093]
After the ISM status bit (SR7) is set, the device / bank (SR0), device protection (SR3), bank A0 (SR1), bank A1 (SR2), write / protect block (SR4) and erase / unprotect ( Each status bit of SR5) is checked. If one of the status bits of SR3, SR4, SR5 or a combination (some) of these status bits is set, an error occurs during processing. The ISM cannot reset the SR3, SR4, SR5 bits. In order to clear these bits, it is necessary to issue a CLEAR_STATUS_REGISTER command (50H). Table 5 shows errors due to combinations of SR3, SR4, and SR5.
[0094]
[Table 10]
[0095]
Synchronous flash memory is designed and manufactured to meet advanced code and data storage requirements. To ensure this level of reliability, VCCP must be held at Vcc between WRITE cycles or ERASE cycles. If the process is executed without satisfying this restriction, the number of WRITE cycles and the number of ERASE cycles executed in the device are reduced. Each block is designed and manufactured so that it can be written / erased at least 100,000 times.
[0096]
The synchronous flash memory has several power saving functions. The power saving function can be used in the array read mode to save power. The deep power down mode can be executed by setting RP # to VSS ± 0.2V. In this mode, the amount of current (ICC) is small, for example, 50 μA at the maximum. When CS # goes HIGH, the device enters active standby mode. Even in this mode, the current is low, and the amount of current (ICC) is, for example, 30 mA at the maximum. If CS # goes HIGH during a write, erase, or protect process, the ISM continues with the WRITE process and the device consumes active Icpp power until the process is finished.
[0097]
FIG. 16 is a flowchart of a self-timed write sequence according to an embodiment of the present invention. This sequence includes loading a command register (code 40H), receiving an active command and a row address, receiving a write command and a column address. In this sequence, the status register is polled to determine whether or not the writing has been completed. Status register bit 7 (SR7) is monitored by polling to determine whether status register bit 7 is set to 1. As an option, a status check may be executed. When the writing process is completed, the array enters an array read mode.
[0098]
FIG. 17 shows a flowchart of a complete read status check sequence according to an embodiment of the present invention. In this sequence, status register bit 4 (SR4) is checked to determine if it is set to zero. If SR4 is 1, it is assumed that an error has occurred during the writing process. In this sequence, the status register bit 3 (SR3) is checked to determine whether it is set to zero. If SR3 is 1, it is assumed that an invalid write error has occurred during the write process.
[0099]
FIG. 18 shows a flowchart of a self-synchronizing block erase sequence according to an embodiment of the present invention. This sequence includes loading a command register (code 20H), receiving an active command and a row address. The memory then determines whether the block is protected. If the block is not protected, the memory performs a write process (D0H) on the block, monitors the status register, and determines whether the process is complete. As an option, a status check may be executed. When the erase process is finished, the memory enters an array read mode. If the block is protected, the erasing process cannot be executed unless the RP # signal is at a high voltage (VHH).
[0100]
FIG. 19 shows a flowchart of a complete block erase status check sequence according to an embodiment of the present invention. In this sequence, the status register is monitored to check whether a command sequence error has occurred (SR4 = 1 or SR5 = 1). If SR3 is set to 1, an invalid erasure error or a non-protection error (protection violation error) occurs. If SR5 is set to 1, a block erase error or a non-protection error (protection violation error) occurs.
[0101]
FIG. 20 shows a flowchart of a block protection sequence according to an embodiment of the present invention. This sequence includes loading a command register (code 60H), receiving an active command and a row address. The memory then determines whether the block is protected. If the block is not protected, the memory performs a write process (01H) on the block, monitors the status register, and checks whether the process is complete. As an option, a status check may be executed. When the block protection process is completed, the memory enters an array read mode. If the block is protected, the erasing process cannot be executed unless the RP # signal is at a high voltage (VHH).
[0102]
FIG. 21 shows a flowchart of a complete block status check sequence according to one embodiment of the present invention. In this sequence, status register bits 3, 4, 5 are monitored to determine whether an error has been detected.
[0103]
FIG. 22 shows a flowchart of a device protection sequence according to an embodiment of the present invention. This sequence includes loading a command register (code 60H), receiving an active command and a row address. The memory then determines whether RP # is VHH. The memory executes the write process (F1H), monitors the status register, and checks whether the write process is completed. As an option, a status check may be executed. When the device protection process is completed, the memory enters an array read mode.
[0104]
FIG. 23 shows a flowchart of a block protection release sequence according to an embodiment of the present invention. This sequence includes loading a command register (code 60H), receiving an active command and a row address. The memory then determines whether the memory device is protected. If not protected, the memory determines whether the boot location (blocks 0 and 15) is protected. If none of the blocks are protected, the memory performs a write process (D0H) on the block, monitors the status register, and checks whether the write process is complete. As an option, a status check may be executed. When all block protection cancellation processing is completed, the memory enters the array read mode. If the device is protected, the erase process cannot be performed unless the RP # signal is at a high voltage (VHH). Similarly, if each boot location is protected, the memory determines whether all blocks should be unprotected.
[0105]
FIG. 24 shows the timing of the process of initializing and loading the mode register. The mode register is programmed by issuing a load mode register command and issuing a processing code (opcode) for the address line. The opcode is loaded into the mode register. As described above, the contents of the nonvolatile mode register are automatically loaded into the mode register at the time of power-up, and there is a case where load mode register processing is not required.
[0106]
FIG. 25 shows the timing of clock suspend mode processing, and FIG. 26 shows the timing of another burst read processing. FIG. 27 shows the timing when the bank read access is alternately performed. Here, in order to change the bank address, an active command is required. FIG. 28 shows a full page burst read process. Full page bursts do not occur in a self-synchronous manner and require the issue of an end command.
[0107]
FIG. 29 shows the timing of read processing using a data mask signal. The DQM signal is used to mask the data output so that Dout m + 1 is not output to the DQ terminal.
[0108]
FIG. 30 shows the timing when the read process is performed on a different bank after the write process is performed. In this process, the writing process is performed on the bank a, and then the reading process is performed on the bank b. The same row is accessed in each bank.
[0109]
FIG. 31 shows the timing when the read process is performed on the same bank after the write process is performed. In this process, the writing process is performed on the bank a, and then the reading process is performed on the bank a. In the read process, another row is accessed and the memory needs to wait for the write process to finish. This is different from the case of the read process as shown in FIG. 30, that is, the case where no delay time is caused by the write process at the start of the read process.
[0110]
Matched latency for all read operations
With the synchronous flash of the present invention, memory contents can be read out basically in the same manner as SDRAM. That is, this synchronous flash memory has a read latency. In the conventional flash memory, read processing such as the status register 282 and the intelligent identifier register may be executed. The data held by the status register 282 is read using a multiplexer circuit 280 that controls data traffic according to the processing mode. Such a prior art system is shown in FIG. Data in the status register 282 is output from the multiplexer circuit 280. The second input terminal of the multiplexer circuit can receive data from the pipeline buffer 284 and the memory array read circuit 286. In order to output data from the multiplexer circuit to the DQ connection terminal, an output buffer circuit 288 is connected to the multiplexer circuit.
[0111]
A problem arises when such a conventional system is applied to a synchronous flash. If the processing mode differs depending on whether array reading or register reading is performed, the data read latency is different, so there is a high possibility that bus contention will occur when reading data from the register, causing a problem with the bus controller. Sometimes. In other words, the output data from the multiplexer circuit may have a read latency that does not match the data read latency in the memory.
[0112]
The present invention has a different output design than the prior art. As shown in FIG. 33, the flash memory of the present invention includes a multiplexer circuit 302 connected to the input terminal of the pipeline buffer 304. In one embodiment, the output buffer has three pipeline paths. A pipeline path is selected according to the clock latency (1, 2, or 3) during the reading process. Memory array read circuit 124, status register 134, and identification (configuration) register 136 are connected to multiplexer circuit 302. The multiplexer circuit is connected to the pipeline circuit and the output buffer circuit 306. Accordingly, both memory array data and register data are processed through the selected pipeline path. In this way, the data from the register always has the same clock latency as the array data. Therefore, in the present invention, bus contention is less likely to occur due to register read processing.
[0113]
Conclusion
In the present specification, a synchronous flash memory including an array of nonvolatile memory cells has been described. The package configuration of the memory device is compatible with the SDRAM. The memory device has a plurality of selectable transmission paths and includes a pipeline buffer that routes data from an input terminal to an output terminal. Each transmission path requires a predetermined number of clock cycles. The nonvolatile synchronous memory includes a circuit for matching the latency of both types of data by routing both the memory data and the register data through the pipeline output buffer. In one embodiment, the circuit includes a multiplexer circuit connected to the input terminal of the pipeline buffer. The data register circuit is connected to the first input terminal of the multiplexer circuit, and the data read circuit is connected to the second input terminal of the multiplexer circuit. The data read circuit outputs data read from the memory array of the synchronous memory device.
[Brief description of the drawings]
FIG. 1A is a block diagram showing a synchronous flash memory according to the present invention, FIG. 1B is a diagram showing terminal connection of an integrated circuit according to an embodiment of the present invention, and FIG. FIG. 2 is a diagram showing an arrangement of a bump grid array of an integrated circuit according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a mode register according to an embodiment of the present invention.
FIG. 3 is an operation explanatory diagram showing a read process when CAS latency is 1, 2, or 3 clock cycles.
FIG. 4 is an operation explanatory diagram showing a process of activating a specific row of a memory bank according to an embodiment of the present invention.
FIG. 5 is an explanatory diagram showing timing between an activation command and a read command or a write command.
FIG. 6 is an explanatory diagram showing a read command.
FIG. 7 is a diagram showing the timing of consecutive read bursts according to an embodiment of the present invention.
FIG. 8 is a diagram showing the timing of random read access within a page according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a timing of a writing process performed following a reading process.
FIG. 10 is a diagram showing a timing at which a read burst process is completed using a burst terminate command in an embodiment of the present invention.
FIG. 11 is an explanatory diagram showing a write command.
FIG. 12 is a diagram illustrating a timing of a read process performed subsequent to a write process.
FIG. 13 is a diagram showing timing of power-down processing according to the embodiment of the present invention.
FIG. 14 is a diagram illustrating timing of clock suspend processing at the time of burst reading.
FIG. 15 is an explanatory diagram showing a memory address map in an embodiment in which a memory has two boot sectors.
FIG. 16 is a flowchart showing a self-synchronous write sequence according to an embodiment of the present invention.
FIG. 17 is a flowchart showing a complete write status check sequence according to an embodiment of the present invention.
FIG. 18 is a flowchart showing a self-synchronization erasing sequence according to an embodiment of the present invention.
FIG. 19 is a flowchart showing a complete block erase status check sequence according to an embodiment of the present invention.
FIG. 20 is a flowchart showing a block protection sequence according to an embodiment of the present invention.
FIG. 21 is a flowchart showing a complete block status check sequence according to an embodiment of the present invention.
FIG. 22 is a flowchart showing a device protection sequence according to an embodiment of the present invention.
FIG. 23 is a flowchart showing a block protection release sequence according to the embodiment of the present invention.
FIG. 24 is a diagram illustrating timing of initialization and load processing of a mode register.
FIG. 25 is a diagram illustrating timing of clock suspend mode processing;
FIG. 26 is a diagram illustrating timing of burst read processing.
FIG. 27 is a diagram illustrating timings at which bank read accesses are alternately performed;
FIG. 28 is a diagram illustrating timing of full page burst read processing.
FIG. 29 is a diagram illustrating timing of burst read processing performed using a data mask signal.
FIG. 30 is a diagram illustrating a timing of performing a read process on a different bank following the read process.
FIG. 31 is a diagram illustrating a timing for performing a read process on the same bank following a write process;
FIG. 32 is a diagram illustrating a conventional register circuit.
FIG. 33 is a diagram showing an embodiment of a register of the present invention.

Claims (27)

  1. A pipeline buffer comprising an input terminal and an output terminal;
    A multiplexer circuit comprising a first input terminal and a second input terminal, the multiplexer circuit connected to the input terminal of the pipeline buffer;
    A data register circuit connected to the first input terminal of the multiplexer circuit;
    A synchronous memory device including a data read circuit connected to the second input terminal of the multiplexer circuit;
    The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminal to the output terminal, each transmission path requires a predetermined number of clock cycles;
    The synchronous memory device, wherein the data read circuit outputs data read from a memory array of the synchronous memory device.
  2. The synchronous memory device of claim 1, wherein
    The pipeline buffer has a synchronous memory device having three transmission paths that can be selected so that a clock latency in a read process is 1, 2, or 3.
  3. The synchronous memory device of claim 1, wherein
    A synchronous memory device, wherein the data register circuit includes a status register for holding status data.
  4. The synchronous memory device according to claim 3, wherein
    The status data is
    The activation status of the state machine in the synchronous memory device;
    Memory array bank status,
    A synchronous memory device characterized by including processing error data.
  5. The synchronous memory device of claim 1, wherein
    A synchronous memory device, wherein the array of memory cells is an array of nonvolatile memory cells.
  6. An array of non-volatile memory cells;
    A pipeline buffer comprising an input terminal and an output terminal;
    A multiplexer circuit comprising a first input terminal and a second input terminal, the multiplexer circuit connected to the input terminal of the pipeline buffer;
    A data register circuit connected to the first input terminal of the multiplexer circuit;
    A synchronous memory device including a data read circuit connected to the second input terminal of the multiplexer circuit;
    The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminal to the output terminal, each transmission path requires a predetermined number of clock cycles;
    The data read circuit outputs data read from the nonvolatile memory array, and the data from the data register circuit and the data from the data read circuit pass through one of the plurality of selectable transmission paths. A synchronous memory device, wherein the synchronous memory device is transmitted through the pipeline buffer circuit.
  7. The synchronous memory device of claim 6, wherein
    The synchronous memory device, wherein the pipeline buffer has three transmission paths that can be selected so that a clock latency during a read process is 1, 2, or 3.
  8. A memory controller;
    A processing system including a synchronous flash memory device connected to the memory controller,
    The synchronous flash memory device is
    An array of non-volatile memory cells;
    A pipeline buffer comprising an input terminal and a data output terminal;
    A multiplexer circuit comprising a first input terminal and a second input terminal, the multiplexer circuit connected to the input terminal of the pipeline buffer;
    A status register circuit connected to the first input terminal of the multiplexer circuit;
    A memory read circuit connected to the second input terminal of the multiplexer circuit;
    The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminals to the data output terminals, each transmission path requiring a predetermined number of clock cycles, The data output terminal of the line buffer is connected to the memory controller via a data bus,
    The data read circuit supplies data read from the array of nonvolatile memory cells, and the data from the status register circuit and the data from the memory read circuit are one of the plurality of selectable transmission paths. Is transmitted through the pipeline buffer circuit.
  9. The processing system of claim 8,
    The processing system characterized in that the plurality of selectable transmission paths include a transmission path having a transmission delay of 1 clock cycle, a transmission path having a transmission delay of 2 clock cycles, and a transmission path having a transmission delay of 3 clock cycles.
  10. A memory controller;
    A processing system including a synchronous flash memory device connected to the memory controller,
    The memory controller receives memory cell data from the synchronous flash memory device after a first predetermined number of clock cycles have elapsed since the memory controller provided a memory column address;
    The memory controller receives status data from the synchronous flash memory device after a second predetermined number of clock cycles have elapsed since the memory controller made a status read request;
    The processing system, wherein the first predetermined number of clock cycles and the second predetermined number of clock cycles are the same.
  11. The processing system of claim 10, wherein
    The synchronous flash memory is
    An array of non-volatile memory cells;
    A pipeline buffer comprising an input terminal and a data output terminal;
    A multiplexer circuit comprising a first input terminal and a second input terminal, the multiplexer circuit connected to the input terminal of the pipeline buffer;
    A status register circuit connected to the first input terminal of the multiplexer circuit;
    A memory read circuit connected to the second input terminal of the multiplexer circuit;
    The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminals to the data output terminals, each transmission path requiring a predetermined number of clock cycles, The data output terminal of the line buffer is connected to the memory controller via a data bus,
    The data read circuit supplies data read from the array of nonvolatile memory cells, and the data from the status register circuit and the data from the memory read circuit are one of the plurality of selectable transmission paths. Is transmitted through the pipeline buffer circuit.
  12. The processing system of claim 10, wherein
    The processing system, wherein the first and second predetermined number of clock cycles include one clock cycle, two clock cycles, and three clock cycles.
  13. An array of non-volatile memory cells;
    In a synchronous flash memory, which is connected to an external data connection terminal and includes a pipeline buffer for supplying memory read data in response to a read request and status register data in response to a status request,
    After a predetermined number of clock cycles have elapsed since the read request has been made, the memory read data is supplied to the external data connection terminal, and after the predetermined number of clock cycles have elapsed since the status request has been made, The status register data is supplied to the external data connection terminal,
    The synchronous flash memory device, wherein the memory read data and the status register data have the same clock latency.
  14. The synchronous flash memory device of claim 13,
    A multiplexer circuit comprising a first input terminal and a second input terminal, the multiplexer circuit connected to the input terminal of the pipeline buffer;
    A status register circuit connected to the first input terminal of the multiplexer circuit;
    An array readout circuit connected to the second input terminal of the multiplexer circuit;
    The synchronous flash memory device, wherein the data read circuit supplies data read from a memory array.
  15. The synchronous flash memory device of claim 13,
    The synchronous flash memory device, wherein the predetermined number of clock cycles includes one clock cycle, two clock cycles, and three clock cycles.
  16. Starting a memory cell read process;
    Outputting memory cell data from the memory cell read process to a data connection terminal after a predetermined number of clock cycles have elapsed since starting the memory cell read process;
    Starting the status reading process;
    Including a step of outputting status data from the status read process to the data connection terminal after the predetermined number of clock cycles have elapsed since the status read process started. How to read data.
  17. The method of claim 16, wherein
    The step of outputting the memory cell data includes the step of outputting the memory cell data to an input terminal of a pipeline buffer and transmitting the memory data through the pipeline buffer during the predetermined number of clock cycles. A method of reading data from a featured synchronous flash memory device.
  18. The method of claim 16, wherein
    Outputting the status data includes outputting the status data to an input terminal of a pipeline buffer and transmitting the status data through the pipeline buffer during the predetermined number of clock cycles. To read data from a synchronous flash memory device.
  19. The method of claim 16, wherein
    Outputting the memory cell data includes outputting the memory cell data to an input terminal of a pipeline buffer during the predetermined number of clock cycles and transmitting the memory cell data through the pipeline buffer; The outputting of the status data includes outputting the status data to the input terminal of the pipeline buffer and transmitting the status data through the pipeline buffer during the predetermined number of clock cycles. A method of reading data from a featured synchronous flash memory device.
  20. The method of claim 19, wherein
    A method of reading data from a synchronous flash memory device, wherein a path of the memory cell data and the status data to the pipeline buffer is selectively established by a multiplexer circuit.
  21. 17. The method of claim 16, wherein the predetermined number of clock cycles includes one clock cycle, two clock cycles, and three clock cycles.
  22. Establishing a path for receiving memory data or status data through an input terminal of a pipeline buffer;
    Transmitting the memory cell data or the status data through the pipeline buffer;
    Outputting the memory cell data or the status data to an external data connection terminal. A method for reading data from a synchronous memory device.
  23. The method of claim 22, wherein
    Establishing a path for receiving the memory cell data or the status data comprises:
    Reading the memory cell data and establishing a path for receiving the memory cell data through a first input terminal of a multiplexer circuit;
    Reading the status data and establishing a path for receiving the status data through a second input terminal of the multiplexer circuit;
    Selectively reading a path from either the first input terminal or the second input terminal and the pipeline buffer through the multiplexer circuit; and reading data from the synchronous memory device Method.
  24. The method of claim 22, wherein
    A method of reading data from a synchronous memory device, wherein the pipeline buffer has a plurality of selectable transmission paths.
  25. 25. The method of claim 24, wherein
    The plurality of selectable transmission paths include a transmission path having a delay time of 1 clock cycle, a transmission path having a delay time of 2 clock cycles, and a transmission path having a delay time of 3 clock cycles. How to read data from.
  26. Reading memory cell data and establishing a path for transmitting said memory cell data to a first input terminal of a multiplexer circuit;
    Reading status data from a status register and establishing a path for transmitting the status data to a second input terminal of the multiplexer circuit;
    In a method of reading data from a synchronous memory device, comprising selectively establishing a path between any one of the first input terminal and the second input terminal of the multiplexer circuit and an input terminal of a pipeline buffer,
    The pipeline buffer has a plurality of selectable transmission paths;
    A method of reading data from a synchronous device, wherein either the memory cell data or the status data is transmitted through the pipeline buffer and output to an external data connection terminal.
  27. The method of claim 26.
    The plurality of selectable transmission paths include a transmission path having a delay time of 1 clock cycle, a transmission path having a delay time of 2 clock cycles, and a transmission path having a delay time of 3 clock cycles. How to read data from.
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US6615307B1 (en) * 2000-05-10 2003-09-02 Micron Technology, Inc. Flash with consistent latency for read operations
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