CN111796771B

CN111796771B - Flash memory controller, solid state disk, controller thereof and flash memory command management method

Info

Publication number: CN111796771B
Application number: CN202010623091.XA
Authority: CN
Inventors: 方浩俊; 黄运新; 印中举; 杨州; 杨亚飞
Original assignee: Shenzhen Dapu Microelectronics Co Ltd
Current assignee: Shenzhen Dapu Microelectronics Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2024-01-26
Anticipated expiration: 2040-06-30
Also published as: CN111796771A

Abstract

The embodiment of the invention relates to the field of solid state disk application and discloses a flash memory controller, a solid state disk, a controller thereof and a flash memory command control method, wherein the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module, an IO management module and a flash memory IO module, the automatic command management module is used for storing and managing microcodes corresponding to a plurality of flash memory commands, and each microcodes is used for generating the flash memory command corresponding to each microcodes; the IO management module is used for receiving the flash memory command sent by the automatic command management module; the flash memory IO module is used for receiving the flash memory command sent by the IO management module, analyzing the command and generating a corresponding operation time sequence to interact with the flash memory medium. The flash memory command is generated by the hardware automatic command management module, and the flash memory command is automatically sent according to the set conditions, so that the software overhead of the solid state disk can be reduced, the burden of a processor is reduced, and the performance of the solid state disk is improved.

Description

Flash memory controller, solid state disk, controller thereof and flash memory command management method

Technical Field

The present invention relates to the field of solid state disk applications, and in particular, to a flash memory controller, a solid state disk, a controller thereof, and a flash memory command management method.

Background

The solid state disk (Solid State Drives, SSD) is a hard disk made of a solid state electronic memory chip array, and the solid state disk comprises a control unit and a memory unit (FLASH memory chip or DRAM memory chip). Some of the current solid state disk systems have dynamic random access memories (Dynamic Random Access Memory, DRAM), so SSD has a large data buffer space for buffering data.

Flash memory (NAND Flash) is the primary storage medium for solid state disks. Flash memory has been developed to 3D TLC at present, with IO interface speeds developed to 1600MT; the development of the method also brings problems, such as higher and higher original bit error rate (UBER), and higher design challenges of Signal Integrity (SI). Flash memory developers offer a series of solutions for this purpose that require flash mastering to assist in completion, such as periodic Read refresh commands (Read flash) to preserve the electrical characteristics of the internal Cell; or a periodic ZQ Calibration (ZQ Calibration) function to enhance flash related signal integrity. These functions typically have periodic transmission requirements and require operation only when there are no other operations (i.e., in idle).

Generally, if the software is used, the software is required to perform cycle management and flow control management, so that the command is ensured to be periodically sent, and the flash memory is enabled to be in an operational state through flow control management and then related command operation is performed. Obviously, this method will bring about the overhead of software management and increase the burden of CPU, inevitably increasing the relevant delay (Latency) of the Solid State Disk (SSD), and affecting the product performance. If a co-processor is added specifically to manage such commands, its processing requirements do not require such high processing power of the co-processor and the co-processor is cost prohibitive.

Based on this, improvements are needed in the art.

Disclosure of Invention

The embodiment of the invention aims to provide a flash memory controller, a solid state disk, a controller thereof and a flash memory command management method, which solve the problems that the burden of a processor is easily increased, time delay is caused to influence the performance of the solid state disk when the conventional solid state disk performs command management in a software mode, so that the burden of the processor is reduced, and the performance of the solid state disk is improved.

In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:

in a first aspect, an embodiment of the present invention provides a flash memory controller applied to a solid state disk, where the solid state disk includes at least one flash memory medium, the flash memory controller includes at least one flash memory channel, each flash memory channel includes an automatic command management module, an IO management module, and a flash memory IO module, where,

The automatic command management module is connected with the IO management module and used for storing microcodes corresponding to a plurality of flash memory commands, and each microcode is used for generating the flash memory command corresponding to each microcode;

the IO management module is connected with the automatic command management module and is used for receiving the flash memory command sent by the automatic command management module;

the flash memory IO module is connected with the IO management module and the flash memory medium and is used for receiving the flash memory command sent by the IO management module, analyzing the flash memory command and generating an operation time sequence, and interacting with the flash memory medium;

after the automatic command management module meets the triggering condition, triggering the corresponding microcode to generate a corresponding flash memory command, and sending the IO operation corresponding to the flash memory command to the IO management module, so that the IO management module forwards the IO operation to the flash memory IO module, and the flash memory IO module sends the IO operation to a corresponding flash memory medium.

In some embodiments, the solid state disk further comprises a processor module, and the flash memory controller further comprises:

the interface module is connected with the processor module and the IO management module and is used for receiving the flash memory command sent by the processor module and forwarding the flash memory command sent by the processor module to the IO management module so that the IO management module adds the flash memory command into a flash memory command processing sequence.

In some embodiments, the automated command management module comprises:

the command management module is used for managing flash memory commands;

and the access management module is connected with the command management module and the IO management module and is used for interfacing the IO management module.

In some embodiments, the command management module includes:

the microcode storage module is used for storing microcodes corresponding to the flash memory commands;

the microcode processing module is connected with the microcode storage module and is used for executing the microcode, generating a flash memory command corresponding to the microcode and generating IO operation corresponding to the flash memory command;

an external access interface connected with the microcode storage module and used for writing microcode into the microcode storage module;

and the condition management module is used for determining whether a triggering condition is met, wherein the triggering condition comprises a timing strategy and/or a counting strategy.

In some embodiments, the solid state disk further includes a processor module, and the condition management module includes:

an external interface connected with the processor module and used for docking the processor module;

the condition register set is connected with the external interface and comprises a plurality of condition registers, and each condition register corresponds to one triggering condition;

The timer group is connected with the control state machine and comprises a plurality of timers, each timer is used for setting a time threshold value corresponding to a flash memory command, and each timer corresponds to a condition register;

and the control state machine is connected with the external interface, the condition register group and the timer group and is used for controlling the state of the condition register group.

In some embodiments, the path management module comprises:

the IO recycling module is used for recycling the completed IO operation and updating the control information of the flash memory command corresponding to the IO operation;

the IO resource management module is used for managing resource application, resource formatting and resource release of the automatic command management module;

and the IO sending module is used for sending the IO operation to the IO management module.

In a second aspect, an embodiment of the present invention provides a solid state disk controller, including:

the flash memory controller described above;

and the processor module is connected with the flash memory controller and is used for generating a flash memory command to the flash memory controller.

In a third aspect, an embodiment of the present invention provides a solid state disk, including:

the solid state disk controller;

and the at least one flash memory medium is in communication connection with the solid state disk controller.

In a fourth aspect, an embodiment of the present invention provides a flash memory command management method, which is applied to the above solid state disk, where the method includes:

acquiring microcode corresponding to a plurality of flash memory commands;

triggering the microcode if a triggering condition is met, and generating IO operation of a flash memory command corresponding to the microcode, wherein the triggering condition comprises a timing strategy and/or a counting strategy;

and sending the IO operation to the flash memory medium to update control information corresponding to the flash memory command and/or store data returned by the flash memory medium.

In some embodiments, the timing policy is a hardware timer policy, and when the set timer reaches a preset time threshold, the corresponding condition register is written to trigger execution of the corresponding microcode;

the counting strategy is a software counting strategy, and when the counting times reach a preset time threshold, the corresponding condition register is written to trigger the execution of the corresponding microcode.

In some embodiments, the IO management module includes an IO sequence table, and after generating the IO operation of the flash memory command corresponding to the microcode, the method further includes:

inserting IO operation of the flash memory command into the IO sequence table;

And sequentially executing IO operations in the IO sequence table.

In a fifth aspect, embodiments of the present invention further provide a non-volatile computer-readable storage medium storing computer-executable instructions for enabling a solid state disk to perform the flash command management method as described above.

The embodiment of the invention has the beneficial effects that: compared with the prior art, the flash memory controller provided by the embodiment of the invention is applied to a solid state disk, the solid state disk comprises at least one flash memory medium, the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module, an IO management module and a flash memory IO module, wherein the automatic command management module is connected with the IO management module and is used for storing microcodes corresponding to a plurality of flash memory commands, and each microcodes is used for generating the flash memory command corresponding to each microcodes; the IO management module is connected with the automatic command management module and is used for receiving the flash memory command sent by the automatic command management module; the flash memory IO module is connected with the IO management module and the flash memory medium and is used for receiving the flash memory command sent by the IO management module, analyzing the flash memory command and generating an operation time sequence, and interacting with the flash memory medium; after the automatic command management module meets the triggering condition, triggering the corresponding microcode to generate a corresponding flash memory command, and sending the IO operation corresponding to the flash memory command to the IO management module, so that the IO management module forwards the IO operation to the flash memory IO module, and the flash memory IO module sends the IO operation to a corresponding flash memory medium. The flash memory command is generated by the automatic command management module, so that the burden of a processor of the solid state disk can be reduced, and the performance of the solid state disk is improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

FIG. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a flash memory controller according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another embodiment of a flash memory controller according to the present invention;

FIG. 4 is a schematic diagram of an automatic command management module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a condition management module according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an IO management module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a solid state disk controller according to an embodiment of the present invention;

FIG. 8 is a flowchart illustrating a flash command management method according to an embodiment of the present invention;

FIG. 9 is a schematic flow chart of an automatic command execution flow according to an embodiment of the present invention;

FIG. 10 is a schematic flow chart of IO recycling according to an embodiment of the present invention;

FIG. 11 is a schematic flow chart of executing a trigger strategy according to an embodiment of the present invention;

FIG. 12 is a schematic flow chart of the initialization of a ZQ calibration command according to an embodiment of the present invention;

fig. 13 is a flow chart illustrating a process of executing a ZQ calibration command according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

Typical solid state drives (Solid State Drives, SSD) generally include solid state drive controllers (host controllers), flash memory arrays, cache units, and other peripheral units.

The solid state disk controller is used as a control operation unit for managing an SSD internal system; flash memory arrays (NAND Flash), which are used as storage units for storing data, including user data and system data, typically present multiple Channels (CH) with one Channel being independently connected to a set of NAND Flash, e.g., CH0/CH1 … … CHx. Wherein the Flash memory (NAND Flash) has the characteristics that before writing, the Flash memory must be erased, and each Flash memory has limited erasing times; a cache unit for caching the mapping table, the cache unit typically being a dynamic random access memory (Dynamic Random Access Memory, DRAM). Other peripheral units may include sensors, registers, and the like.

The general solid state disk controller mainly comprises a PCIe/NVMe controller, a DDR controller, a data path module, a flash memory controller, a CPU module, a peripheral module and the like. The flash memory control is used for an operation control module related to the flash memory, specific command operation of the general flash memory is issued to the flash memory controller by the CPU through the interface, and the IO operation flow is managed by the IO management module; and generating a corresponding Flash command operation time sequence to the Flash memory by the Flash IO module.

In the prior art, the corresponding flash memory command operation is realized by periodically sending IO operation to the flash memory controller. Through flow control management, the flash memory is ensured to be in an operable state and relevant command operation is performed, so that the software design has certain complexity. Generally, if a specific command is periodically managed by software, the software is required to perform periodic management to ensure that the command is periodically sent, and related command operations are required to be performed after the flash memory is in an operable state by flow control management. Obviously, this method will bring about the overhead of software management and increase the burden of CPU, thereby increasing the relevant delay (Latency) of the Solid State Disk (SSD), and affecting the product performance.

In view of this, the invention provides a flash memory controller, a solid state disk, a controller thereof and a flash memory command management method, which are used for solving the problems that the burden of a processor is easily increased, and the performance of the solid state disk is affected due to delay caused by command management in a software mode of the existing solid state disk, so that the burden of the processor is reduced, and the performance of the solid state disk is improved.

The technical scheme of the invention is described below with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of a solid state disk according to an embodiment of the present invention.

As shown in fig. 1, the solid state disk 300 includes a flash memory medium 310 and a solid state disk controller 320 connected to the flash memory medium 310. The solid state disk 300 is in communication connection with the host 400 through a wired or wireless manner, so as to implement data interaction.

The Flash memory medium 310, which is a storage medium of the solid state disk 300, is also referred to as a Flash memory, a Flash memory or Flash particles, belongs to one type of storage device, is a nonvolatile memory, and can store data for a long time even without current supply, and has storage characteristics equivalent to a hard disk, so that the Flash memory medium 310 becomes a base of storage media of various portable digital devices.

The FLASH memory medium 310 may be a Nand FLASH memory, which uses a single transistor as a storage unit of binary signals, and has a structure very similar to that of a common semiconductor transistor, wherein the Nand FLASH memory has a single transistor added with a floating gate and a control gate, the floating gate is used for storing electrons, the surface of the floating gate is covered by a layer of silicon oxide insulator, and is coupled with the control gate through a capacitor, when negative electrons are injected into the floating gate under the action of the control gate, the storage state of the single crystal of the Nand FLASH memory is changed from "1" to "0", and when the negative electrons are removed from the floating gate, the storage state is changed from "0" to "1", and the insulator covered on the surface of the floating gate is used for trapping the negative electrons in the floating gate, thereby realizing data storage. I.e., nand FLASH memory cells are floating gate transistors that are used to store data in the form of electrical charges. The amount of charge stored is related to the magnitude of the voltage applied by the floating gate transistor.

One Nand FLASH comprises at least one Chip, each Chip is composed of a plurality of Block physical blocks, and each Block physical Block comprises a plurality of Page pages. The Block physical Block is the minimum unit of executing the erasing operation by the Nand FLASH, the Page is the minimum unit of executing the reading and writing operation by the Nand FLASH, and the capacity of one Nand FLASH is equal to the number of the Block physical Block and the number of Page pages contained in one Block physical Block and the capacity of one Page. Specifically, the flash memory medium 10 can be classified into SLC, MLC, TLC and QLC according to the voltage levels of the memory cells.

The solid state disk controller 320 includes a data converter 321, a processor 322, a buffer 323, a flash memory controller 324, and an interface 325.

The data converter 321 is connected to the processor 322 and the flash memory controller 324, respectively, and the data converter 321 is used for converting binary data into hexadecimal data and vice versa. Specifically, when the flash controller 324 writes data to the flash memory medium 310, binary data to be written is converted into hexadecimal data by the data converter 321, and then written to the flash memory medium 310. When the flash controller 324 reads data from the flash memory medium 310, hexadecimal data stored in the flash memory medium 310 is converted into binary data by the data converter 321, and then the converted data is read from a binary data page register. The data converter 321 may include a binary data register and a hexadecimal data register, among others. The binary data register may be used to hold data converted from hexadecimal to binary, and the hexadecimal data register may be used to hold data converted from binary to hexadecimal.

And a processor 322 connected to the data converter 321, the buffer 323, the flash memory controller 324 and the interface 325, wherein the processor 322 is connected to the data converter 321, the buffer 323, the flash memory controller 324 and the interface 325 through a bus or other manners, and is used for running nonvolatile software programs, instructions and modules stored in the buffer 323, so as to implement any method embodiment of the present invention.

The buffer 323 is mainly used for buffering the read/write command sent by the host 400 and the read data or write data obtained from the flash memory medium 310 according to the read/write command sent by the host 400. The buffer 323 is a type of nonvolatile computer-readable storage medium, and can be used to store nonvolatile software programs, nonvolatile computer-executable programs, and modules. The buffer 323 may include a storage program area that stores an operating system, at least one application program required for the function. In addition, the buffer 323 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the buffer 323 optionally includes memory that is remotely located relative to the processor 324. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The buffer 323 can be a static random access memory (Static Random Access Memory, SRAM) or a coupled memory (Tightly Coupled Memory, TCM) or a double rate synchronous dynamic random access memory (Double DataRate Synchronous Dynamic Random Access Memory, DDR SRAM).

A flash controller 324 connected to the flash medium 310, the data converter 321, the processor 322, and the buffer 323, and configured to access the flash medium 310 at the back end, and manage various parameters and data I/O of the flash medium 310; or, the interface and the protocol for providing access are used for realizing a corresponding SAS/SATA target protocol end or NVMe protocol end, acquiring an I/O instruction sent by the host, decoding and generating an internal private data result, and waiting for execution; or for the core processing responsible for FTL (Flash translation layer ).

The interface 325 is connected to the host 400 and the data converter 321, the processor 322 and the buffer 323, and is configured to receive data sent by the host 400, or receive data sent by the processor 322, so as to implement data transmission between the host 400 and the processor 322, where the interface 325 may be a SATA-2 interface, a SATA-3 interface, a SAS interface, a MSATA interface, a PCI-E interface, an NGFF interface, a CFast interface, a SFF-8639 interface, and an m.2nvme/SATA protocol.

Referring to fig. 2 again, fig. 2 is a schematic structural diagram of a flash memory controller according to an embodiment of the invention; the flash memory controller is applied to a solid state disk, and the solid state disk comprises at least one flash memory medium and a processor module, wherein the processor module is a central processing unit (Central Processing Unit, CPU).

As shown in fig. 2, the flash controller 10 includes a flash channel including an interface module 11, an automatic command management module 12, an IO management module 13, and a flash IO module 14, wherein,

an automatic command management module 12, connected to the interface module 11 and the IO management module 13, configured to store a plurality of microcode corresponding to the plurality of flash commands, where each microcode is configured to generate a flash command corresponding to the microcode;

specifically, the automatic command management module 12 is configured to generate and manage a flash command as needed, without requiring complex management of software, and automatically send the flash command to the flash medium when a trigger condition or an execution condition is satisfied, where the trigger condition includes a timing policy and/or a count policy. Each microcode corresponds to a flash memory command, and each microcode is used for generating the flash memory command corresponding to the microcode. For example: the automatic command management module 12 may store a plurality of preset microcode, through which the automatic command management module 12 may generate an IO operation of a corresponding flash memory command, such as an IO operation of a ZQ calibration command, and send the IO operation to the IO management module 13.

The IO management module 13 is connected with the automatic command management module 12 and is used for receiving the flash memory command sent by the automatic command management module 12;

Specifically, the IO management module 13 is configured to manage, in a traversal manner, all the IO operations from the processor module or the automatic command management module 12, that is, receive the flash memory command sent by the processor module or the automatic command management module 12.

The flash memory IO module 14 is connected with the IO management module 14 and the flash memory medium, and is used for receiving the flash memory command sent by the IO management module 13, generating an operation time sequence based on the flash memory command and interacting with the flash memory medium;

specifically, the Flash memory IO module 14 is responsible for generating a Flash command operation sequence corresponding to the IO operation, that is, a Flash command operation sequence, and interacting with the Flash memory medium.

After the automatic command management module 12 meets the triggering condition or the executing condition, the corresponding microcode is triggered to generate a corresponding flash memory command, and the IO operation corresponding to the flash memory command is sent to the IO management module 13, so that the IO management module 13 forwards the IO operation to the flash memory IO module 14, and the flash memory IO module 14 sends the IO operation to the corresponding flash memory medium.

Referring to fig. 3 again, fig. 3 is a schematic structural diagram of another flash memory controller according to an embodiment of the present invention; the flash memory controller is applied to a solid state disk, the solid state disk comprises at least one flash memory medium and a processor module, the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module 12, an IO management module 13 and a flash memory IO module 14, and the flash memory controller 10 comprises an interface module 11, an automatic command management module 12, an IO management module 13 and a flash memory IO module 14.

The interface module 11 is connected to the processor module and the IO management module 13, and is configured to receive a flash memory command sent by the processor module, and forward the flash memory command sent by the processor module to the IO management module 13, so that the IO management module 13 adds the flash memory command to a flash memory command processing sequence, where the flash memory command processing sequence is a sequence table including a plurality of flash memory commands, and the flash memory command processing sequence may be implemented by a linked list manner.

The automatic command management module 12 is connected with the interface module 11 and the IO management module 13 and is used for storing microcodes corresponding to a plurality of flash commands, and each microcode is used for generating the flash command corresponding to the microcode;

the automatic command management module 12 is configured to generate and manage a flash command as needed, without requiring complex management of software, and automatically send the flash command to the flash medium when a preset trigger condition or execution condition is met, where the trigger condition or execution condition includes a timing policy and/or a counting policy. Each microcode corresponds to a flash memory command, and each microcode is used for generating the flash memory command corresponding to the microcode. For example: the automatic command management module 12 may store a plurality of preset microcode, through which the automatic command management module 12 may generate corresponding flash memory command IO operations, such as IO operations of ZQ calibration commands, and send the IO operations to the IO management module 13. Wherein the flash commands include, but are not limited to: ZQ calibration commands, read refresh commands, flash Temperature query commands (Temperature Get), auto-Read calibration commands (AutoRead Calibration), and the like. It is understood that the flash memory command is a periodically processed command.

The invention can realize all the flash commands processed periodically and can better realize the newly added flash commands so as to reduce the processing process of the processor and lighten the burden of the processor because the automatic command management module is used for storing the microcode and generating the design mode of the needed flash commands through the microcode.

Specifically, referring to fig. 4 again, fig. 4 is a schematic structural diagram of an automatic command management module according to an embodiment of the present invention;

as shown in fig. 4, the automatic command management module 12 includes: a command management module 121 and a path management module 122, wherein the command management module 121 is connected with the path management module 122.

Wherein, the command management module 121 is used for managing flash memory commands;

specifically, the command management module 121 includes: a microcode storage module 1211, a microcode processing module 1212, an external path interface 1213, and a condition management module 1214.

Wherein, the microcode storage module 1211 is configured to store microcode corresponding to the plurality of flash commands;

specifically, the microcode storage module 1211 is mainly used to store microcode written by a user, and the microcode is used to control related operations of flash memory commands to be executed, and may store microcode required by multiple commands.

The microcode processing module 1212 is connected to the microcode storage module, and is configured to execute the microcode, generate a flash memory command corresponding to the microcode, and generate an IO operation corresponding to the flash memory command;

specifically, the microcode processing module 1212 is a processor module that executes microcode, and the microcode processing module 1212 controls the generation of the required IO operations to an external IO management module according to the flash memory command defined by the microcode.

Wherein the external access interface 1213 is connected to the microcode storage module, and is used for writing microcode into the microcode storage module;

specifically, the external access interface 1213 is used for the CPU module of the solid state disk to configure the relevant registers, write microcode into the microcode storage module 1211, and obtain the data of the relevant registers and the random access memory (random access memory, RAM).

Wherein, the condition management module 1214 is configured to determine whether a trigger condition is satisfied, where the trigger condition includes a timing policy and/or a counting policy.

Specifically, the condition management module 1214 is configured to manage whether the related flash memory command is in a transmittable state, mainly by managing whether the transmission period reaches the threshold value through a timer, and by managing whether the condition value reaches the threshold value through a comparator.

Specifically, referring to fig. 5 again, fig. 5 is a schematic diagram of a condition management module according to an embodiment of the present invention;

as shown in fig. 5, the condition management module 1214 includes: the external interface 12141, the condition register set 12142, the control state machine 12143 and the timer set 12144, wherein the solid state disk further comprises a processor module, and the external interface 12141 is respectively connected to the condition control register set 12142, the control state machine 12143 and the timer set 12144.

Wherein the external interface 12141 is respectively connected to the condition register set 12142, the control state machine 12143 and the timer set 12144, and to a processor module for interfacing with the processor module, for example: the processor module writes corresponding condition registers in the condition register set 12142 via the external interface 12141.

Wherein, the condition register set 12142 is connected to the external interface 12141 and the control state machine 12143, and the condition register set 12142 includes a plurality of condition registers, each condition register corresponds to a trigger condition.

Wherein the control state machine 12143 is connected to the external interface 12141, the condition register set 12142 and the timer set 12144 for controlling the state of the condition register set 12142, i.e. for controlling writing of the condition registers in the condition register set 12142.

The timer set 12144 is connected to the external interface 12141 and the control state machine 12143, where the timer set 12144 includes a plurality of timers, each timer is used to set a time threshold of a corresponding flash memory command, and each timer corresponds to a condition register.

The path management module 122 is connected to the command management module 121 and the IO management module, and is configured to interface with the IO management module. The path management module 122 is configured to perform management of IO resources, IO operation sending and recovery with the IO management module.

As shown in fig. 4, the path management module 122 includes: an IO reclamation module 1221, an IO resource management module 1222, and an IO transmission module 1223.

The IO recycling module 1221 is connected to the IO resource management module 1222, and is configured to recycle the completed IO operation, and update control information of the flash memory command corresponding to the IO operation;

specifically, the IO reclamation module reclaims the completed IO operation and updates the control information of the corresponding command, if the control information is returned, the return data is saved to a register or a random access memory (random access memory, RAM).

It will be appreciated that flash commands typically include control information, including, for example, status information including: executing, completing, error, etc. Alternatively, the control information includes composition information including the number of IOs, and an execution state of each IO.

The IO resource management module 1222 is connected to the IO recycling module 1221 and the IO sending module 1223, and is configured to manage resource application, resource formatting, and resource release of the automatic command management module;

specifically, the IO resource management module 1222 is configured to take charge of resource application, formatting and release management of the automatic command management module;

the IO sending module 1223 is connected to the IO resource management module 1222, and is configured to send an IO operation to the IO management module.

Specifically, the IO sending module 1223 is configured to send the IO generated by the automatic command management module 12 to an external IO management module.

The IO management module 13 is connected to the automatic command management module 12, and is configured to receive a flash memory command sent by the automatic command management module 12;

specifically, after receiving at least one flash memory command sent by the automatic command management module 12, the IO management module generates a flash memory command processing sequence, i.e. an IO List, and sends the flash memory command to the flash memory I O module 14, so that the flash memory IO module 14 generates an operation timing sequence based on the flash memory command, and interacts with the flash memory medium.

In the embodiment of the present invention, the IO management module includes a command arbitration management module, which is configured to queue the flash memory command sent by the processor module 40 and the flash memory command sent by the automatic command management module 12 according to the priority of the flash memory command, and add the queue to the flash memory command processing sequence to solve the conflict between the flash memory commands.

It will be appreciated that the IO management module 13 is managed by another set of microcode processing units, which also need to write microcode, which belongs to the prior art and is not described herein.

The flash memory IO module 14 is connected to the IO management module and the flash memory medium, and is configured to receive a flash memory command sent by the IO management module, and generate an operation timing sequence based on the flash memory command, and interact with the flash memory medium;

specifically, the flash memory IO module 14 is connected to the IO management module and the flash memory medium, and is configured to receive the flash memory command sent by the IO management module, and generate an operation sequence based on the flash memory command, where the flash memory operation sequence is used to determine an execution sequence of each flash memory command. The flash IO module 14 generates an operation sequence through the flash command, and interacts with the flash medium.

It will be appreciated that the flash IO module 14 is also managed by another set of microcode processing units, which also require microcode to be written, which is known in the art and will not be described in detail herein.

Specifically, the triggering condition comprises a timing strategy and/or a counting strategy, wherein the timing strategy is a hardware timer strategy, specifically, the hardware selects real-time running time as a period, and the triggering condition triggers execution when the real-time running time reaches a preset time threshold value, so that the flash memory command is automatically sent and managed in the solid state disk power-on period. For example, a corresponding timer is set in an initialized mode, a control state machine is operated, and if the timer reaches a preset time threshold, a corresponding condition register is set, namely, the corresponding condition register is written, so that execution of corresponding microcode is triggered, and the flash memory command sending management is automatically carried out in the life cycle of the solid state disk.

The counting strategy is a software counting strategy, the software selects a linearly-increasing numerical value, namely the counting times are taken as a period, such as the erasing times, and when the counting times reach a preset time threshold, a corresponding condition register is set, namely the corresponding condition register is written, so that execution of corresponding microcode is triggered, and the flash memory command sending management is automatically carried out in the life cycle of the solid state disk.

According to the embodiment of the invention, the flash memory command is generated by hardware, so that the software overhead and the CPU burden can be reduced, and the performance of a Solid State Disk (SSD) product is improved.

In the embodiment of the invention, the flash memory controller is applied to the solid state disk, the solid state disk comprises at least one flash memory medium, the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module, an IO management module and a flash memory IO module, wherein the automatic command management module is used for storing microcodes corresponding to a plurality of flash memory commands, and each microcode is used for generating the flash memory command corresponding to the microcodes; the IO management module is used for receiving the flash memory command sent by the automatic command management module; the flash memory IO module is used for receiving the flash memory command sent by the IO management module, generating an operation time sequence based on the flash memory command, and interacting with the flash memory medium. The flash memory command is generated by the automatic command management module, so that the burden of a processor of the solid state disk can be reduced, and the performance of the solid state disk is improved.

Referring to fig. 6 again, fig. 6 is a schematic structural diagram of an IO management module according to an embodiment of the present invention;

as shown in fig. 6, the IO management module 13 includes: a first IO distribution module 131, an IO recycling module 132, an IO acquisition module 133, a second IO distribution module 134, and a path control logic module 135, wherein,

the first IO distribution module 131, i.e. the IO Dispatcher, is configured to distribute the IO operations in the first IO List to the automatic command management module, where the first IO List is configured to sort the reclaimed IO operations;

the IO recycling module 132, i.e. the IO recycle, is configured to add the IO operation returned by the flash memory medium to a first IO List, where the first IO List is an IO List corresponding to the first IO distribution module 131;

the IO obtaining module 133, i.e. the IO Fetcher, is configured to obtain the IO operation sent by the processor module, and add the IO operation to a second IO List, where the second IO List is configured to sort the IO operation sent by the automatic command management module and the IO operation sent by the processor module;

the second IO distribution module 134, i.e. the IO Dispatcher, is configured to send the IO operation in the second IO List to the flash memory IO module, where the second IO List is the IO List corresponding to the IO obtaining module 133.

The path control logic module 135 is configured to control the order of the IO operations in the first IO List and the second IO List.

The IO management module 13 determines, through the path control logic module 135, an order of the IO operations sent by the automatic command management module and the IO operations sent by the processor module, for example: ordering is performed according to the priority.

Referring to fig. 7 again, fig. 7 is a schematic structural diagram of a solid state disk controller according to an embodiment of the present invention;

as shown in fig. 7, the solid state disk controller 100 includes: flash memory controller 10, controller module 20, data path module 30, processor module 40, and peripheral module 50.

The flash memory controller 10 is the flash memory controller in the above embodiment, which is referred to in the above embodiment and will not be described herein.

The controller module 20 is connected to the processor module 40 and the data path module 30, where the controller module 20 includes a DDR controller and a PCIe/NVMe controller, and is configured to process IO operations of different interface protocols issued by a host.

The data path module 30 is connected to the controller module 20, the flash memory controller 10 and the processor module 40, wherein the data path module 30 is connected to the interface module 11 of the flash memory controller 10, and is configured to process the IO operation issued by the host, and send the IO operation issued by the host to the interface module 11. In the embodiment of the present invention, the Data Path module 30 is a Data Path processing module.

The processor module 40 is connected to the flash memory controller 10, the controller module 20, the data path module 30, and the peripheral module 50, and is configured to send IO operations to the flash memory controller 10, or control the working processes of the flash memory controller 10, the controller module 20, the data path module 30, and the peripheral module 50. In an embodiment of the present invention, the processor module 40 is a central processing unit (Central Processing Unit, CPU).

Wherein the peripheral module 50 is connected to the processor module 40, and includes a peripheral unit, such as a sensor, for processing peripheral related operations.

In this embodiment of the present invention, the processor module 40 may send a flash command to the interface module 11, where the flash command is forwarded to the IO management module 13 through the interface module 11, and the automatic command management module 12 may also send the flash command directly to the IO management module 13, where the flash command sent by the processor module 40 and the flash command sent by the automatic command management module 12 are processed by the IO management module, where the IO management module includes a command arbitration management module, and the command arbitration management module is configured to queue the flash command sent by the processor module 40 and the flash command sent by the automatic command management module 12 according to the priority of the flash command, and add a flash command processing sequence to solve the conflict between the flash commands.

In an embodiment of the present invention, by providing a solid state disk controller, the method includes: the system comprises a flash memory controller and a processor module, wherein the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module, an IO management module and a flash memory IO module, the automatic command management module is used for storing microcodes corresponding to a plurality of flash memory commands, and each microcode is used for generating the flash memory command corresponding to each microcodes; the IO management module is used for receiving the flash memory command sent by the automatic command management module; the flash memory IO module is used for receiving the flash memory command sent by the IO management module, generating an operation time sequence based on the flash memory command, and interacting with the flash memory medium. The processor module is connected with the flash memory controller and is used for generating a flash memory command to the flash memory controller. By queuing the flash commands sent by the processor module 40 and the flash commands sent by the automatic command management module 12 and adding the flash command processing sequence, the embodiment of the invention can solve the conflict between the flash commands.

Referring to fig. 8, fig. 8 is a flowchart illustrating a flash memory command management method according to an embodiment of the invention;

As shown in fig. 8, the flash memory command management method includes:

step S10: acquiring microcode corresponding to a plurality of flash memory commands;

specifically, the microcode is pre-written or set by a user, each flash memory command corresponds to a microcode, and the microcode is used for defining a flash memory command, wherein the flash memory command comprises a ZQ calibration command. And a microcode processing module for acquiring microcode corresponding to the flash memory commands and storing the microcode in a command management module of the automatic command management module.

Step S20: triggering the microcode if a triggering condition is met, and generating IO operation of a flash memory command corresponding to the microcode, wherein the triggering condition comprises a timing strategy and/or a counting strategy;

specifically, the triggering condition includes a timing policy and/or a counting policy. The timing strategy is a hardware timer strategy, specifically, the hardware selects real-time running time as a period, and the execution is triggered when the real-time running time reaches a preset time threshold value, so that the flash memory command is automatically sent and managed in the solid state disk power-on period. For example, by initializing a corresponding timer, running a control state machine, if the set timer reaches a preset time threshold, setting a corresponding condition register, namely writing the corresponding condition register, so as to trigger execution of corresponding microcode, and automatically performing transmission management of flash memory commands in the life cycle of the solid state disk.

The counting strategy is a software counting strategy, the software selects a linear increment value (such as erasing times) as a period, and when the counting times reach a preset time threshold, a corresponding condition register is set, namely the corresponding condition register is written, so that execution of corresponding microcode is triggered, and the flash memory command sending management is automatically performed in the life cycle of the solid state disk.

Specifically, referring to fig. 9 again, fig. 9 is a schematic flow diagram of an automatic command execution flow provided in an embodiment of the present invention;

as shown in fig. 9, the automatic command execution flow includes:

step S91: editing microcode and storing;

specifically, the user edits the microcode corresponding to the plurality of flash memory commands and sends the microcode to the microcode storage module through the external access interface so that the microcode storage module stores the microcode, wherein each section of microcode corresponds to one flash memory command, and specifically, each section of microcode corresponds to the operation process of one flash memory command or a series of commands.

Step S92: initializing a condition management module;

specifically, the initializing condition management module includes: setting an operating parameter, setting an execution condition or a trigger condition of each section of microcode, etc., by checking whether a register bit field of a register corresponding to each section of microcode is set, for example: is set to 1, wherein the register is located in a condition control register set of the condition management module, and the register bit field is set by a timer, a comparator, or a processor.

Step S93: initializing and enabling a microcode processing module;

specifically, initializing a microcode processing module and enabling the microcode processing module, wherein the microcode processing module comprises that a hardware module in a closing state when being electrified is activated through a program writing register enabling bit, and after the microcode processing module is enabled, the microcode processing module enters a microcode program inlet to start to execute microcode;

step S94: entering a microcode program entry;

specifically, a microcode program entry is entered, ready to execute the microcode.

Step S95: whether to execute the section of microcode;

specifically, judging whether the section of microcode meets an execution condition or a triggering condition; if yes, go to step S96; if not, go to step S99;

step S96: executing microcode;

specifically, microcode is executed to generate flash commands, such as ZQ calibration commands, corresponding to the microcode.

Step S97: generating IO operation;

specifically, based on the flash memory command, IO operations are generated.

Step S98: transmitting IO operation;

step S99: jumping to the next section of microcode;

specifically, when the section of microcode does not meet the execution condition or the trigger condition, the execution process of the next section of microcode is entered, the sequence of the next section of microcode is determined by the programming of the programmer, and after jumping to the next section of microcode, the step S95 is returned to: judging whether to execute the sections of microcode, and executing the sections of microcode corresponding to the flash memory command in a circulating way.

Step S30: and sending the IO operation to the flash memory medium to update control information corresponding to the flash memory command and/or store data returned by the flash memory medium.

Specifically, when executing a section of microcode, a flash memory command corresponding to the section of microcode is generated, and an IO operation, such as a ZQ calibration operation, of the flash memory command corresponding to the microcode is generated, and the IO operation is sent to the flash memory medium, so that the flash memory medium executes the IO operation to update control information corresponding to the flash memory command and/or store data returned by the flash memory medium.

Specifically, referring to fig. 10 again, fig. 10 is a schematic flow chart of IO recovery according to an embodiment of the present invention;

as shown in fig. 10, the IO recovery includes:

step S101: IO recovery;

specifically, after the IO operation of the flash memory command is finished, the IO recycling module recycles the IO operation, the IO operation information is sent to the IO management module through the flash memory IO module, and then the IO operation information is sent to the automatic command management module by the IO management module, so that the IO recycling module in the automatic command management module obtains the IO operation information, and the IO operation information is sent to the IO resource management module.

Step S102: updating the information of the corresponding command and storing the returned data;

specifically, the IO resource management module updates control information corresponding to the flash memory command according to the IO operation information, and stores returned data in a relevant register and a random access memory (random access memory, RAM), where the relevant register and the random access memory (random access memory, RAM) are predefined.

In an embodiment of the present invention, the IO management module includes an IO sequence table, and after generating the IO operation of the flash memory command corresponding to the microcode, the method further includes:

inserting IO operation of the flash memory command into the IO sequence table;

and sequentially executing IO operations in the IO sequence table.

Specifically, according to the order of the IO operations in the IO sequence table, the IO operations in the IO sequence table are sequentially executed.

Referring to fig. 11 again, fig. 11 is a schematic flow chart of executing a trigger policy according to an embodiment of the invention;

as shown in fig. 11, the execution triggering strategy includes:

step S110: selecting a command trigger condition type;

specifically, the command trigger condition type includes a timing strategy and/or a counting strategy, that is, a hardware timer strategy and/or a software control counting strategy, and the user determines the trigger condition type corresponding to the flash memory command by selecting the command trigger condition type. Or determining the trigger condition type corresponding to the flash memory command according to the requirements of different flash memory commands or the product requirements. For example: in the read refresh command, the flash memory manufacturer requests 3ms, sends a read refresh command once, selects a hardware timer strategy, and sets 3ms trigger command sending. Alternatively, a ZQ command, such as a flash memory temperature query command, is sent every 1000 hours, and typically an engineer queries the flash memory temperature according to the requirements of the product application environment and different time intervals. All of the above are satisfied by the timing of the HW. The timing strategy, such as an auto-calibration command, is selected by an engineer to determine the transmission period based on the number of erasures of the flash memory, such as every 300 erasures, and the count strategy is selected if the number of erasures is maintained by software.

Step S111: hardware timer policy;

step S112: selecting a timer;

step S113: setting the corresponding relation between the timer and the condition register;

step S114: setting a timer period;

specifically, the timer period is a preset time threshold.

Step S115: triggering a writing condition register when the timing reaches a threshold value;

specifically, when the timing reaches the preset time threshold, the triggering condition or the executing condition is considered to be met, and at the moment, the writing condition register is triggered according to the corresponding relation between the timer and the condition register;

step S116: software controls a counting strategy;

step S117: selecting a counting variable;

specifically, a count variable is determined, the count variable including the number of erasures.

Step S118: determining the corresponding relation between the counting variable and the condition register;

step S119: the counting variable reaches a threshold value to trigger a writing condition register;

specifically, when the count variable reaches a preset frequency threshold, a trigger condition or an execution condition is satisfied, and the condition register is written according to the corresponding relation between the count variable and the condition register.

Referring to fig. 12 again, fig. 12 is a schematic flow chart of initializing a ZQ calibration command according to an embodiment of the invention;

As shown in fig. 12, the initialization of the ZQ calibration command includes:

step S121: writing microcode corresponding to ZQ calibration and storing the microcode;

step S122: setting the period of the timer to 1000 hours;

step S123: initializing and enabling a microcode processing module;

referring to fig. 13 again, fig. 13 is a flow chart illustrating a process of executing a ZQ calibration command according to an embodiment of the invention;

as shown in fig. 13, the execution of the ZQ calibration command includes:

step S131: whether a corresponding condition register is set or not is calibrated by ZQ;

step S132: executing microcode corresponding to ZQ calibration;

step S133: generating a ZQ calibration IO operation;

step S134: transmitting a ZQ calibration IO operation;

step S135: inserting ZQ calibration IO operations into an IO sequence table;

the IO sequence table is an IO List, and after the ZQ calibration IO operation is inserted into the IO sequence table, the execution sequence of the ZQ calibration IO operation is determined according to the sequence in the IO sequence table.

Step S136: transmitting a ZQ calibration command to the flash memory;

specifically, a ZQ calibration command is sent to the flash media.

Step S137: the flash memory completes the ZQ calibration command;

specifically, the flash media completes the ZQ calibration command.

Step S138: recovery of ZQ calibration IO operation;

Step S139: updating the corresponding command control information;

step S1310: executing other microcode;

specifically, according to the IO sequence table, executing the next section of microcode of the ZQ calibration command.

In an embodiment of the present invention, a flash memory command management method is provided and applied to the above solid state disk, where the method includes: acquiring microcode corresponding to a plurality of flash memory commands; triggering the microcode if a triggering condition is met, and generating IO operation of a flash memory command corresponding to the microcode, wherein the triggering condition comprises a timing strategy and/or a counting strategy; and sending the IO operation to the flash memory medium to update control information corresponding to the flash memory command and/or store data returned by the flash memory medium. By triggering the microcode after the triggering condition is met, IO operation of a flash memory command corresponding to the microcode is automatically generated.

Embodiments of the present invention also provide a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, such as the one processor 322 of fig. 1, to cause the one or more processors to perform the flash command management method of any of the method embodiments described above, such as performing the steps shown in fig. 8 described above.

The above-described embodiments of the apparatus or device are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for up to a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the invention, the steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The flash memory controller is applied to a solid state disk, and the solid state disk comprises at least one flash memory medium, and is characterized in that the flash memory controller comprises at least one flash memory channel, each flash memory channel comprises an automatic command management module, an IO management module and a flash memory IO module,

the automatic command management module is connected with the IO management module and used for storing and managing microcodes corresponding to a plurality of flash memory commands, and each microcode is used for generating the flash memory command corresponding to each microcode;

after the automatic command management module meets the triggering condition, triggering corresponding microcode to generate a corresponding flash memory command, and sending IO operation corresponding to the flash memory command to the IO management module, so that the IO management module forwards the IO operation to the flash memory IO module, and the flash memory IO module sends the IO operation to a corresponding flash memory medium;

the triggering condition comprises a timing strategy, wherein the timing strategy is a hardware timer strategy, and the hardware timer strategy is used for writing a corresponding condition register when a set timer reaches a preset time threshold value, so that execution of corresponding microcode is triggered.

2. The flash controller of claim 1, wherein the solid state disk further comprises a processor module, the flash controller further comprising:

The interface module is connected with the processor module and the IO management module and is used for receiving the flash memory command sent by the processor module and forwarding the flash memory command sent by the processor module to the IO management module so that the IO management module adds the flash memory command sent by the processor module into a flash memory command processing sequence.

3. The flash memory controller of claim 1, wherein the automatic command management module comprises:

the command management module is used for managing flash memory commands;

4. The flash memory controller of claim 3, wherein the command management module comprises:

And the condition management module is used for determining whether the triggering condition is met or not, and the triggering condition further comprises a counting strategy.

5. The flash controller of claim 4, wherein the solid state disk further comprises a processor module, the condition management module comprising:

the timer group is connected with the control state machine and comprises a plurality of timers, each timer is used for setting a time threshold value corresponding to the flash memory command, and each timer corresponds to a condition register;

6. The flash controller of claim 3, wherein the path management module comprises:

7. A solid state disk controller, comprising:

the flash memory controller of any one of claims 1-6;

8. A solid state disk, comprising:

the solid state disk controller of claim 7;

9. A flash memory command management method, applied to the solid state disk of claim 8, comprising:

acquiring microcode corresponding to a plurality of flash memory commands;

10. The method of claim 9, wherein the step of determining the position of the substrate comprises,

the timing strategy is a hardware timer strategy, and when the set timer reaches a preset time threshold, a corresponding condition register is written to trigger execution of corresponding microcode;

11. The method of claim 9, wherein the IO management module includes an IO sequence table, the method further comprising, after generating the IO operation of the flash command corresponding to the microcode:

inserting IO operation of the flash memory command into the IO sequence table;

and sequentially executing IO operations in the IO sequence table.