JP2010092342A - Interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit allowing data access to a serial flash memory to be performed as quickly as possible. <P>SOLUTION: The interface circuit accesses the serial flash memory wherein a program is stored, on the basis of a request of a CPU core executing the program and includes: an automatic command generation circuit which generates a read command and an address set to be issued to the serial flash memory, on the basis of a read signal and an address signal output from the CPU core; a control unit which issues the read command and the address set to the serial flash memory; and a word register wherein data read out from the serial flash memory in accordance with the read command and the address set is stored. Furthermore, the control unit is configured so as to output data which is read out from the serial flash memory and is stored in the word register, to the CPU core. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an interface circuit, for example, an interface circuit for accessing a serial flash memory.

  Conventionally, a device that stores a program of a microcomputer (hereinafter also referred to as a microcomputer) is called a program ROM. As a device used for the program ROM, a mask ROM (built-in mask ROM) incorporated in the microcomputer and a memory (for example, NOR type parallel flash memory) connected in parallel with the microcomputer are mostly used.

  However, the following problems occur regardless of which device is used. That is, when the built-in mask ROM is used, there is a problem that the chip size of the microcomputer increases as the capacity increases and the cost of the microcomputer chip increases. On the other hand, when the NOR type parallel flash memory is used, there is a problem that the number of signal lines between the microcomputer and the flash memory is large, so that it is easily affected by noise generated by other components on the board. In addition, there is a problem that the cost of the NOR type parallel flash memory is high.

  In recent years, a NOR type serial flash memory (hereinafter referred to as a serial flash memory) that can cope with an increase in capacity at a relatively low cost has appeared. Since this serial flash memory is connected to the microcomputer with significantly fewer signal lines than the parallel flash memory, it is easy to avoid the noise problem.

Conventionally, a microcomputer in which the number of device terminals is reduced by using a serial flash memory has been disclosed (Patent Document 1).
JP 2004-38560 A

  An object of the present invention is to provide an interface circuit capable of performing data access to a serial flash memory as fast as possible.

  According to one aspect of the present invention, an interface circuit that accesses a serial flash memory that stores the program based on a request of a CPU core that executes a program, the read signal and the address signal output from the CPU core An automatic command generation circuit for generating a read command and an address set to be issued to the serial flash memory, a control unit for issuing the read command and an address set to the serial flash memory, and the read command And a word register that stores data read from the serial flash memory according to an address set, and the control unit further reads the data read from the serial flash memory and stored in the word register The Serial and is configured as outputting to the CPU core, the interface circuit is provided, characterized in that.

  According to the present invention, data access to the serial flash memory can be performed as fast as possible.

  Before describing the embodiments of the present invention, the background of how the present inventor made the present invention will be described.

  As described above, there is a possibility that the serial flash memory can be used as a program ROM that is relatively easy to increase in capacity and is less affected by noise. For this purpose, it is necessary to be able to randomly access the serial flash memory from the microcomputer at a certain high speed. However, in order to access the serial flash memory, commands such as read and write and an address set are generated. This command and address set are different for each serial flash memory vendor. Furthermore, it is necessary to convert the generated command and address set into a serial signal and issue it to the serial flash memory. For this reason, there has been a problem that the data access time associated with instruction fetching and the like is significantly increased as compared with the parallel flash memory.

  As one of the countermeasures against this problem, a high-speed accessible memory such as SDRAM (Synchronous Dynamic Random Access Memory) or DDR SDRAM (Double Data Rate SDRAM) is connected to the microcomputer. There is a method of expanding to high-speed memory. According to this method, since the microcomputer only needs to access a high-speed memory after data expansion, the access time can be shortened. However, in this case, there is a problem that the circuit scale and the board area increase due to an increase in the number of components.

  As another countermeasure, there is a method of speeding up access by incorporating a cache SRAM in the microcomputer. However, in this case, there is a problem that the cost of the microcomputer chip increases.

  Therefore, the above method cannot be used in applications where the requirements for circuit scale, substrate area, and cost are severe.

  Therefore, the present inventor considered to solve the above problem by speeding up access to the serial flash memory as much as possible, and referred to as an interface circuit (hereinafter referred to as an SF interface circuit) for accessing the serial flash memory. ). In other words, the specifications (various commands and addresses) of the serial flash memory are different for each vendor, and it takes time to convert the command and address set conforming to the specifications, so this conversion is performed by hardware in the SF interface. I thought.

  Furthermore, the present inventor has noted that the serial flash memory is designed to automatically output data at subsequent addresses when a read command at a certain address is received. Then, using this specification, the data is stored in a register in the SF interface without being discarded, and the data stored in the register is output immediately upon receiving a read request for the address. It came. Thereby, the data access time such as instruction fetch can be greatly shortened.

  In addition, when an exception factor such as initialization of a microcomputer occurs, the present inventor stores the data required when the exception factor is released in a register in the SF interface, thereby causing the exception factor. I came up with a method to greatly shorten the data access time when the is released.

  Next, before describing an embodiment according to the present invention, a schematic configuration of a microcomputer including an SF interface circuit and an outline of an operation when accessing a serial flash memory will be described.

  A schematic configuration of the microcomputer 100 will be described with reference to FIG. FIG. 1 shows a microcomputer 100 and a serial flash memory 200 connected thereto. As can be seen from FIG. 1, the microcomputer 100 is connected to an external serial flash memory 200 via a dedicated bus. The dedicated bus is composed of, for example, four I / O lines, one clock line, and one chip enable line.

  The microcomputer 100 includes an SF interface circuit 10, a CPU core 20, a bus interface circuit 30, and a built-in memory 40. As can be seen from FIG. 1, these components are connected to each other by a memory data bus (MD bus).

  The CPU core 20 and the SF interface circuit 10 are a control line for transmitting control signals (BSTART signal, MRD signal, MWR signal, MACK signal) and a memory address bus (MADR bus) for transmitting a memory address signal (MADR signal). It is connected.

  The microcomputer 100 is connected to other devices (not shown) via a general bus.

  Next, the function of each component of the microcomputer 100 will be described.

  The SF interface circuit 10 accesses the serial flash memory 200 in response to a request from the CPU core 20.

  The CPU core 20 executes a program stored in the serial flash memory 200.

  The bus interface circuit 30 accesses a device connected to the general bus in response to a request from the CPU core 20.

  The built-in memory 40 is a work RAM used by the CPU core 20.

  A system clock is supplied to each component in the microcomputer 100, and each component operates in synchronization with the system clock.

Next, a method for reading data stored in the external serial flash memory 200 by the microcomputer 100 will be described.
(1) The CPU core 20 generates a command and address set conforming to the specification of the serial flash memory 200 according to a predetermined program.
(2) Next, the CPU core 20 asserts the BSTART signal (Bus Start) and the MRD signal (Memory Read), and starts the read operation. At the same time, the CPU core 20 outputs the generated command and address set to the SF interface circuit 10.
(3) Next, the SF interface circuit 10 issues the received command and address set to the serial flash memory 200 via the dedicated bus. Data read from the serial flash memory 200 is stored in a word register. When data for one word (for example, 32 bits) is prepared, the SF interface circuit 10 outputs the read data to the MD bus (to the CPU core 20), and asserts a MACK signal (Memory Acknowledge). By asserting the MACK signal, the CPU core 20 is informed that the read request has been completed.
(4) When the MACK signal is asserted, the CPU core 20 takes in the data output to the MD bus. Thereafter, the CPU core 20 deasserts the BSTART signal and ends the read operation.

  Hereinafter, four embodiments according to the present invention will be described with reference to the drawings. Constituent elements having the same function are denoted by the same reference numerals, and redundant description is omitted as appropriate.

(First embodiment)
A first embodiment will be described. This embodiment includes an automatic command generation circuit, and speeds up data access by generating a command and an address set that are conventionally performed by a CPU core using an SF interface circuit.

  FIG. 2 shows a configuration of the SF interface circuit 10A according to the present embodiment. As can be seen from FIG. 2, the SF interface circuit 10 </ b> A includes an automatic command generation circuit 1, a control unit 7 </ b> A, and a word register 8.

  The automatic command generation circuit 1 generates a read command and an address set conforming to the specifications of the serial flash memory 200 based on a read signal (MRD signal) and a memory address signal (MADR signal) output from the CPU core 20. Further, based on the write signal (MWR signal) and the memory address signal (MADR signal), a write command and an address conforming to the specification of the serial flash memory 200 are generated.

  The word register 8 stores data read from the serial flash memory 200 according to the read command and the address set. The size of the word register 8 is, for example, 32 bits, and stores one 32-bit long instruction.

  The controller 7A issues a command and an address set to the serial flash memory 200 and outputs the read data to the CPU core 20 as will be described later.

A method for reading data in the serial flash memory 200 of the microcomputer 100 in this embodiment will be described.
(1) The CPU core 20 asserts the BSTART signal and the MRD signal, and starts a read operation. At the same time, the CPU core 20 outputs a MADR signal to the MADR bus.
The address value indicated by the memory address signal does not conform to the specification of the serial flash memory 200.
(2) Next, the automatic command generation circuit 1 decodes the MRD signal and the MADR signal to generate a read command and an address set that conform to the specifications of the serial flash memory 200. Specifically, this address set is generated by converting a parallel MADR signal into a serial signal by parallel-serial conversion (P / S conversion) and adding an appropriate offset value.
(3) Next, the control unit 7A issues the read command and address set generated by the automatic command generation circuit 1 to the serial flash memory 200 via the dedicated bus. When the read data is stored in the word register 8 and data for one word (for example, 32 bits) is prepared, the control unit 7A outputs the data to the MD bus (to the CPU core 20) and outputs a MACK signal. Assert.
(4) When the MACK signal is asserted, the CPU core 20 takes in the data output to the MD bus. Thereafter, the CPU core 20 deasserts the BSTART signal and ends the read operation.

Next, a case where data is written to the serial flash memory 200 will be described. The access method in this case is as follows.
(1) The CPU core 20 asserts the BSTART signal and the MWR signal, and starts a write operation. At the same time, the CPU core 20 outputs a MADR signal to the MADR bus and write data to the MD bus. The address value indicated by the memory address signal does not conform to the specification of the serial flash memory 200.
(2) Next, the automatic command generation circuit 1 decodes the MWR signal and the MADR signal, and generates a write command and an address conforming to the specification of the serial flash memory 200.
(3) Next, the control unit 7A issues the write command and address generated by the automatic command generation circuit 1 to the serial flash memory 200 via the dedicated bus. When data is written at a desired address, the control unit 7A asserts a MACK signal.
(4) When the MACK signal is asserted, the CPU core 20 deasserts the BSTART signal and ends the write operation.

  According to the present embodiment, the command and address set conforming to the specifications of the serial flash memory are not generated by the program executed by the CPU core, but are generated by the hardware of the automatic command generation circuit. Thereby, the generation time of the command and address set is shortened, and data access to the serial flash memory can be performed as fast as possible. Further, since the command and address set generation program is not required, the program size can be reduced, and the program area of the serial flash memory can be effectively used.

(Second Embodiment)
Next, a second embodiment will be described. The present embodiment includes a data buffer having a plurality of word registers. The data buffer stores data of an address requested to be read from the CPU core and a data group composed of a plurality of data at a plurality of addresses sequentially consecutive with the address requested to be read. As a result, when there is a read request from the CPU core for an address continuous with the address read last time, the data stored in the data buffer is output to the CPU core, thereby generating and issuing a read command and an address set. The data access is made as fast as possible.

  FIG. 3 shows a configuration of the SF interface circuit 10B according to the present embodiment. As can be seen from this figure, the SF interface circuit 10B includes an automatic command generation circuit 1, a continuous address determination circuit 2B, a data buffer management circuit 3, a data buffer 4, and a control unit 7B.

  The continuous address determination circuit 2B determines whether or not the address requested this time by the CPU core 20 (the address corresponding to the address signal output from the CPU core 20 to the MADR bus) is continuous with the previously requested address. To do. That is, it is determined whether the address ady is equal to the address adx + 1 when the address requested to be read this time is ady and the address last requested to be read is adx.

  The data buffer 4 has a first word register to an Nth word register. Each of the first to Nth word registers is an n-bit register. For example, one instruction is stored in one word register. If one instruction is 32 bits long, n = 32. The number of word registers is appropriately determined according to the application of the microcomputer (digital camera, facsimile, etc.). For example, N = 6.

  When the data stored in the first word register is output to the MD bus (to the CPU core 20), the data buffer management circuit 3 converts the data stored in the second to Nth word registers into the first to Nth. Move to the -1 word register respectively. That is, the data stored in each word register of the data buffer 4 is packed by one word register. Further, the data buffer management circuit 3 determines whether or not the data buffer 4 is full. That is, it is determined whether data has been stored up to the Nth word register. When it is determined that the data buffer 4 is full, the chip enable of the dedicated bus is deasserted and the read operation is stopped.

The operation of the SF interface circuit 10B when reading data from the serial flash memory 200 will be described below.
It is assumed that there is a read request from the CPU core 20 for the data D (ady) stored at the address ady.
(1) The continuous address determination circuit 2B determines whether the address ady is continuous with the address adx for which a previous read request has been made.
(2) If the result of the continuous address determination is that the address ady is continuous with the address adx, the control unit 7B uses the data D (ady) stored in the first word register of the data buffer 4 as the MD bus (CPU core 20) and assert the MACK signal. The data buffer management circuit 3 packs the data stored in each word register of the data buffer 4 by one word register.
On the other hand, if the result of the continuous address determination is that the address ady is not continuous with the address adx, the control unit 7B causes the automatic command generation circuit 1 to newly generate a read command and an address set corresponding to the address ady. Then, the control unit 7B issues the generated read command and address set to the serial flash memory 200. The read data is stored in the first word register of the data buffer 4. When the data for one word is prepared, the control unit 7B outputs the data D (ady) to the MD bus (to the CPU core 20) and asserts the MACK signal.
(3) When the MACK signal is asserted, the CPU core 20 takes in the data output to the MD bus.
As described above, the serial flash memory 200 automatically follows the data D (ady) and subsequently the data D (ady + 1), D (ady + 2),... Stored in the addresses ady + 1, ady + 2,. Output to. These data are sequentially stored in each word register of the data buffer 4. At this time, the word register is overwritten with the newly read data even if previously read data is stored.
As described above, the SF interface circuit 10B according to the present embodiment includes not only the data of the address requested to be read, but also a plurality of addresses that are sequentially read from the serial flash memory 200 and sequentially consecutive with the address requested to be read. The data at is also stored in the data buffer 4. As a result, when the CPU core 20 makes a read request for an address continuous with the previous time, the data stored in the data buffer 4 is output as the data of the requested address without newly generating and issuing a command and address set. can do. As a result, data access time such as instruction fetch is increased.

  As described above, according to the present embodiment, data access to the serial flash memory can be performed as fast as possible.

(Third embodiment)
Next, a third embodiment will be described. One of the differences between this embodiment and the second embodiment is that the SF interface circuit according to this embodiment includes a plurality of data buffers, and the processing by the CPU core is continued until then by program branching, interrupts, and the like. Even when the address jumps to a non-address, the data access speed is increased.

  FIG. 4 shows a configuration of the SF interface circuit 10C according to the present embodiment. The SF interface circuit 10C includes an automatic command generation circuit 1, a continuous address determination circuit 2C, a data buffer management circuit 3, k data buffers 4-1, 4-2,. , 5-k and a control unit 7C.

  The data buffers 4-1, 4-2,..., 4-k are associated with address setting registers 5-1, 5-2,.

  Address setting registers 5-1, 5-2,..., 5-k are registers for storing addresses. The address requested to be read (the address corresponding to the address signal output from the CPU core 20 to the MADR bus) is stored in any one of the address setting registers 5-1, 5-2,. Stored.

  The continuous address determination circuit 2C determines whether or not an address continuous with the read requested address is stored in any of the address setting registers 5-1, 5-2,. To do.

Hereinafter, the operation of the SF interface circuit 10C when reading data from the serial flash memory 200 will be described.
It is assumed that there is a read request from the CPU core 20 for the data D (ady) stored at the address ady.
(1) The continuous address determination circuit 2C determines whether the address ady is continuous with any of the addresses stored in the address setting registers 5-1, 5-2,.
(2) As a result of the determination by the continuous address determination circuit 2C, when the address “ady” is continuous with an address stored in an address setting register (here, address setting register 5-i), the control unit 7C sets the address. The address ady is stored in the register 5-i, the data D (ady) stored in the first word register of the data buffer 4-i is output to the MD bus (to the CPU core 20), and the MACK signal is asserted.
The data buffer management circuit 3 packs the data stored in each word register of the data buffer 4-i by one word register. As a result, data D (ady + 1) is stored in the first word register. That is, the address (ady + 1) of the data stored in the first word register of the data buffer 4-i is obtained by incrementing the address (ady) stored in the address setting register 5-i by 1.
On the other hand, as a result of the determination by the continuous address determination circuit 2C, when the address ady is not continuous with any of the addresses stored in the address setting registers 5-1, 5-2,. The address ady is stored in a certain address setting register (herein referred to as the address setting register 5-i), and the automatic command generation circuit 1 newly generates a read command and an address set corresponding to the address ady. The control unit 7C issues the generated read command and address set to the serial flash memory 200. The read data is stored in the first word register of the data buffer 4-i corresponding to the address setting register 5-i. When the data for one word is prepared, the control unit 7C outputs the data D (ady) to the MD bus (to the CPU core 20) and asserts the MACK signal. Thereafter, the data buffer management circuit 3 packs the data stored in each word register of the data buffer 4-i by one word register. As a result, data D (ady + 1) is stored in the first word register. That is, the address (ady + 1) of the data stored in the first word register of the data buffer 4-i is obtained by incrementing the address (ady) stored in the address setting register 5-i by 1.
As the address setting register used when there are no consecutive addresses, for example, the one having the smallest number of codes among the address setting registers in which no address is stored is used. That is, if the address is stored in the address setting registers 5-1 and 5-2 and no address is stored in the address setting registers 5-3, 5-4, and 5-5, the address setting register 5-3 is stored. use. If there is no free address setting register, for example, the address setting register 5-1 is used.
(3) When the MACK signal is asserted, the CPU core 20 takes in the data output to the MD bus.
As described above, the serial flash memory 200 automatically follows the data D (ady) and subsequently the data D (ady + 1), D (ady + 2),... Stored in the addresses ady + 1, ady + 2,. Output to. These data are sequentially stored in each word register of the data buffer 4-i. At this time, the word register is overwritten with the newly read data even if previously read data is stored.
As can be seen from the above description, according to the present embodiment, even when the address jumps to a non-contiguous address and then returns to the original address, such as an interrupt operation, the read request is returned. The addressed data can be immediately output to the CPU core 20.

  As described above, according to this embodiment, the same effect as that of the second embodiment can be obtained, and even when a jump to a discontinuous address occurs, the data access speed is made as high as possible. Can do.

(Fourth embodiment)
Next, a fourth embodiment will be described. The present embodiment includes a reset determination circuit. When an exception factor (for example, initialization of the microcomputer or transition to the power saving mode) occurs, a program to be executed when the exception factor is canceled is stored in the data buffer in advance. This speeds up data access when the exception factor is canceled.

  FIG. 5 shows a configuration of the SF interface circuit 10D according to the present embodiment. As can be seen from this figure, the SF interface circuit 10D includes an automatic command generation circuit 1, a data buffer management circuit 3, k data buffers 4-1, 4-2,..., 4-k, and k. , 5-k, a reset determination circuit 6, and a control unit 7D.

Hereinafter, the operation of the SF interface circuit 10D according to the present embodiment will be described.
(1) The RESET signal is asserted, and the reset determination circuit 6 senses it. The reset determination circuit 6 outputs an address (hereinafter referred to as an exception address) to be read when the exception factor is canceled according to the factor (exception factor) indicated by the RESET signal.
(2) The control unit 7D stores the exception address in a certain address setting register (in this case, the address setting register 5-j).
(3) The control unit 7D causes the automatic command generation circuit 1 to generate a read command and an address set for reading the data of the exception address, and issues the generated read command and address set to the serial flash memory 200.
(4) The data stored at the exception address and the plurality of data at a plurality of addresses sequentially consecutive with the exception address are sequentially from the first word register of the data buffer 4-j associated with the address setting register 5-j. Stored.
When the data buffer management circuit 3 determines that the data buffer 4-j is full, the subsequent data is sequentially stored from the first word register of the data buffer 4- (j + 1). In this way, data necessary when the exception factor is canceled is stored in the data buffer.
(5) When the exception factor is canceled, the control unit 7D receives the request from the CPU core 20, outputs the data stored in the data buffer to the MD bus (to the CPU core 20), and outputs the MACK signal. Assert.
(6) When the MACK signal is asserted, the CPU core 20 takes in the data output to the MD bus.
As the above address setting register 5-j, for example, the one having the smallest number of codes among the address setting registers in which no address is stored is used. That is, if the address is stored in the address setting registers 5-1 and 5-2 and no address is stored in the address setting registers 5-3, 5-4, and 5-5, the address setting register 5-3 is stored. use. If there is no free address setting register, for example, the address setting register 5-1 is used.
In the above description, a plurality of address setting registers and data buffers are provided, but one may be used as in the second embodiment.
As described above, according to the present embodiment, data access when an exception factor is canceled is stored in the data buffer in advance when the exception factor is detected, so that data access when the exception factor is canceled is stored. Can be performed as fast as possible.

It is a figure which shows schematic structure of a microcomputer. It is a figure which shows the structure of SF interface circuit which concerns on 1st Embodiment. It is a figure which shows the structure of SF interface circuit which concerns on 2nd Embodiment. It is a figure which shows the structure of SF interface circuit which concerns on 3rd Embodiment. It is a figure which shows the structure of the SF interface circuit which concerns on 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Automatic command generation circuit, 2B, 2C ... Continuous address determination circuit, 3 ... Data buffer management circuit, 4 ... Data buffer, 5 ... Address setting register, 6 ... Reset determination Circuit, 7A, 7B, 7C, 7D ... Control unit, 8 ... Word register, 10,10A, 10B, 10C, 10D ... SF interface circuit, 20 ... CPU core, 30 ... Bus Interface circuit, 40 ... built-in memory, 100 ... microcomputer, 200 ... serial flash memory

Claims (5)

An interface circuit that accesses a serial flash memory that stores the program based on a request of a CPU core that executes the program,
An automatic command generation circuit that generates a read command and an address set to be issued to the serial flash memory based on a read signal and an address signal output from the CPU core;
A controller that issues the read command and address set to the serial flash memory;
A word register for storing data read from the serial flash memory in response to the read command and address set;
With
The control unit is further configured to output data read from the serial flash memory and stored in the word register to the CPU core.
An interface circuit characterized by that. An interface circuit that accesses a serial flash memory that stores the program based on a read signal and an address signal output from a CPU core that executes the program,
A continuous address determination circuit that determines whether an address corresponding to the address signal output from the CPU core is continuous with an address corresponding to the address signal output last time;
An automatic command generation circuit that generates a read command and an address set to be issued to the serial flash memory based on the read signal and the address signal output from the CPU core;
A data buffer having first to Nth word registers, the data buffer including data read from the serial flash memory in response to the read command and an address set, and the serial flash following the data A data buffer whose contents are updated by a data group consisting of an address corresponding to the address signal and a plurality of data at a plurality of consecutive addresses that are automatically read from the memory;
If the result of the determination indicates that the addresses are continuous, the data stored in the first word register of the data buffer is output to the CPU core without operating the automatic command generation circuit, When the determination result indicates that the addresses are not continuous, the read command and the address set generated by operating the automatic command generation circuit are issued to the serial flash memory, and the data whose contents are updated thereby A controller that outputs the data stored in the first word register of the buffer to the CPU core; and
An interface circuit comprising: An interface circuit that accesses a serial flash memory that stores the program based on a read signal and an address signal output from a CPU core that executes the program,
An automatic command generation circuit that generates a read command and an address set to be issued to the serial flash memory based on the read signal and the address signal output from the CPU core;
A plurality of address setting registers, each of which stores a read request address that is an address corresponding to the address signal output from the CPU core. When,
A plurality of data buffers each having first to Nth word registers, each of the data buffers being associated with a plurality of the address setting registers, and the address setting storing the read request address The data buffer corresponding to the register receives data read from the serial flash memory in response to the read command and address set, and the address signal automatically read from the serial flash memory following the data. A plurality of data buffers whose contents are updated by a data group consisting of a plurality of data at a plurality of addresses sequentially consecutive with corresponding addresses;
A continuous address determination circuit that determines whether an address that is continuous with the read request address is stored in any of the plurality of address setting registers;
When the determination result indicates that there are consecutive addresses, the read request address is stored in an address setting register that stores an address continuous with the read request address without operating the automatic command generation circuit. The data stored in the first word register of the data buffer associated with the address setting register is output to the CPU core, while the determination result indicates that there is no continuous address. The read request address is stored in one of the plurality of address setting registers, and a read command and an address set generated by operating the automatic command generation circuit are issued to the serial flash memory. The read request address whose contents have been updated by is stored. A controller that outputs the data stored in the first word register of the data buffer corresponding to the address setting register to the CPU core;
An interface circuit comprising: An interface circuit that accesses a serial flash memory that stores the program based on a request of a CPU core that executes the program,
A reset determination circuit that senses a reset signal and outputs an exception address to be read when the exception factor is canceled according to the exception factor indicated by the reset signal;
An automatic command generation circuit that generates a read command and an address set to be issued to the serial flash memory in order to read the data of the exception address output from the reset determination circuit;
A data buffer having first to Nth word registers, the data buffer including data read from the serial flash memory in response to the read command and an address set, and the serial flash following the data A data buffer whose contents are updated by a data group consisting of an address corresponding to the address signal and data of a continuous address that is automatically read from the memory;
The read command and the address set generated by the automatic command generation circuit are issued to the serial flash memory, whereby the data stored in the data buffer whose contents have been updated are released when the exception factor is canceled. A control unit for outputting to the CPU core;
An interface circuit comprising: The interface circuit according to any one of claims 2 to 4,
When the data stored in the first word register is output to the CPU core, the data stored in the second to Nth word registers is moved to the first to N−1th word registers, respectively. Further comprising a data buffer management circuit;
An interface circuit characterized by that.

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