JPH02144639A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To effectively utilize an address space or a memory space by providing the title device with a control means for variably selecting the storage capacity of a memory cell array based upon an external control signal to select a block. CONSTITUTION:The semiconductor storage device is provided with the control means 6 for variably selecting the storage capacity of the memory cell array 2 based upon an external control signal to select a block. Namely, in case of allocating and setting up areas such as a user area and an operation program area having respectively different purposes to/in the storage area of one semiconductor storage device, the selection of capacity to be required for individual areas and the selection of blocks for the individual allocation areas can be defined or controlled in accordance with external control signals PTN1, PTN2, CS1, CS2 to be applied to the control means 6. Since the function for variable selecting the storage capacity and selecting a block can be obtained by the control means 6, the restriction of the allocation of an individual semiconductor storage device to each memory area or each address space having respectively different purposes can be removed and the capacity of areas having respectively different purposes can be variably selected. Thus, the address space can be effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to storage area partitioning control technology or storage area block selection description in a semiconductor storage device. The present invention relates to a technique that is effective when applied to a semiconductor memory device with a relatively large storage capacity, in which storage areas are used for different purposes.

[Prior art]

When a conventional semiconductor memory device is supplied with an address signal from the outside, it decodes the address signal and automatically allows access to a memory cell according to the address signal. Even if the memory cell array is divided into a plurality of mats, selection of a memory mat is performed according to the decoding result of a predetermined bit included in the address signal. 5. Semiconductor storage devices, which are rejected in microcomputer systems, are used as areas for storing operating systems such as the nucleus (hereinafter simply referred to as O8). The storage area is used as a storage area for user operation programs, a storage area for data, etc. Conventionally, when allocating memory space according to such various uses, different starting addresses were allocated for each use.For example, a separate semiconductor memory device was used for each use.

In addition, as an example of literature describing semiconductor memory devices, 7
It's the Showa era! rLSI published by Ohmsha on November 30, 1959
There are handbooks JP 500 to 520. [Problem to be solved by the invention] However, different leading addresses L and =S are assigned for each application, and a separate semiconductor memory device is used for each application. However, due to the capacity required for each purpose, there is a problem in that the address space is essentially not used and becomes wasted. In addition, the storage capacity of semiconductor storage devices is increasing today, and under these circumstances, it is necessary to allocate areas for different purposes, such as an operating program storage area and a user area, to one semiconductor storage device. However, in that case, if a conventional f,4-body storage device was used, management of each area for different purposes would have to be done with just one address (for example, the user state). There is also a circuit that prohibits unauthorized access to the operating program area where access is prohibited, and a special circuit that prohibits or monitors situations in which access to other areas beyond the designated user area is prohibited. The inventor of the present invention has clarified that there is a problem in that the conventional semiconductor memory device is difficult to use in system construction because a circuit is required.

An object of the present invention is to provide a semiconductor memory device that can effectively utilize address space or memory space. Still another object is to provide a semiconductor memory device that can facilitate access management of address spaces set for each purpose in system configuration or monitoring for unauthorized access.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor memory device is constructed by providing a control means for variably selecting a memory capacity 1 and selecting a block in a memory cell array based on an external control signal. To facilitate block selection, 1. For example, the memory cell array is set as a set of m memory blocks. 1. The control means may have a logical configuration that selects a predetermined number of memory blocks or a plurality of intermediate memory blocks from among a plurality of unit memory blocks based on an external selection signal.

In addition, in order to distinguish between at-L nosing of a memory cell by an address signal and block selection, external control (3
For one or more unit memory blocks selected based on No. 13i It is preferable that the control means described in item 1 include a selection logic that allows access to the unit memory block.

[For production]

According to the above-mentioned means, when allocating and setting areas for different purposes such as a user area and an operation program area to the storage area of one semiconductor storage device, each area is allocated to each area by an external control signal given to the control means described in 1. The selection of the required capacity and the individual allocation can be defined or managed with block selection for areas. The function of variably selecting the storage capacity and selecting blocks by the control means eliminates the restriction of allocating separate semiconductor storage devices for each memory area or address space with different uses, and also makes the capacity of areas with different uses variable. Since it is selectable, it works to achieve effective use of the address space, and furthermore, there is no need for a special circuit to prohibit access that inappropriately exceeds the address space for a specific use. Facilitate access management of address spaces set for each purpose in system configuration or monitoring for unauthorized access 8
Embodiment] FIG. 1 shows a block diagram of a random access memory (also referred to as RAM) which is an embodiment of the present invention. Figure 1. The RAM 1- shown in FIG. 1 is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the memory cell array 2, denoted by 21i, is a memory cell array in which several memory cells (not shown) are arranged in a matrices. Although not particularly limited, the memory cell array 2 has eight unit memory blocks B L X < 1 = B L K 8 are collected. Each unit memory block BLKI~BL
Although not particularly limited, K8 is composed of 8 rows and Q columns, and 8
Data is input and output in bit units, that is, each unit memory block B L K 1. = B
In LK8, the data input/output terminals of the memory cells arranged in the same row are connected to the de-9 line (not shown), and the 45th memory block 7B LK1 to B
Each medium memory block 7 contains 8 data lines per M,, K 8 B L K i == U4 LK
The 8 data input/output terminals, that is, the 8 data lines are an 8-bit configured input/output gate 10G each corresponding to an individual LJ.
It is connected to eight common data lines: 3 via the i-4068, and this common data line 3 can be interfaced with the outside via the a read/write circuit 4, which includes a write circuit, an output amplification circuit, etc. 7. The above unit memory block B T, , K 1. -B
In LK8, the selection terminals of memory cells arranged in the same column are connected to each unit memory ``1 block BLK1''.
~Connected to a word line (not shown) common to BI and K8,
Selection of the word line is performed by the address space 54.': I:t, A of the input signals A1°-A i + supplied from the outside. -Ai
is supplied, and a predetermined word line is selected accordingly.

In the figure, 6 indicates the selection of the capacity required for each area by an external control signal when allocating areas such as the user area and the Yablo Jf RAM area to the memory cell array 2. To allocate the number t, select a block for the area, and select one or more unit memory blocks! 1 vs. 4. Selected by the address signal Ai+...Ai+,
This controller 6L is a controller equipped with a selection logic that allows access to a single hidden memory block, etc. This controller 6L receives block division control signals PTN1 and PTN as external control signals, although not particularly limited.
2. Block selection control signals C81, C82 and lead No. 91843 R/W are supplied. In the memory cell array 2, there are two block selectable areas by the controller 6, and which block is selected is instructed by the block selection control signals C3I and C82. The capacity of the two selectable blocks is a set of prefectural memory blocks. Block selection and block division i! determined according to the level of PTN2! i'! Control signal F
An example of block division using PTN3, PTN2 is shown in Table 1. In addition, PTNl and P in Table 1
In the column of T N 2, 1:'L Is the corresponding control signal a -1 novel? H means that the corresponding control signal is at high level.

Table 1 Is controller 6 the above? Dress signal Ai+.

” One lower memory block to be selected according to the decoding result of A i + 3 is
When included in a group of unit memory blocks selected by the Glock selection control described above, the input/output gates corresponding to the four unit memory blocks are controlled to enable input/output operations. As a control signal for this purpose, the controller 6 sends gate control signals 81 to S8 to input/output gates 10GI to 10G8.
give.

Therefore, according to the controller 6 having such selection control logic 1, for example, the block division control signal I) T
N1 is low level, and block division control signal P
When 'r N 2 is at a high level, when the block selection control signal C5I is set at a high level, unit memory blocks BLKI to BLK2 are selected. When the block selection control signal C52 is set at a high level, unit memory blocks BLKI to BLK2 are selected. BLK3 to BLK8 are selected as blocks. At this time, for example, unit memory blocks BLKI to BLK
In the screen where block 2 is selected, the address signal A i + indicating the selection of unit memory block BLK2
.

.about.Ai+, the control signal S2 is asserted to the selected one level, thereby making the memory cells included in the unit memory block BLK2 accessible.

For read/write control when accessing a memory cell, when a read operation is instructed by the 7 read/write signal R/W, the controller 6 asserts the output enable signal Oe to cause the write/read circuit 4 to perform a data read operation. When a write operation is instructed by the read/write signal R/W, the controller 6
This is performed by asserting the write enable signal we to instruct the hot reading circuit 4 to write data.

According to the above embodiment, the following effects can be obtained.

(1) For example, when allocating and setting a user area and an operation program area for different purposes in the memory cell array 2, the capacity setting of each area is determined by the combination of the levels of the block division control signals PTNI and PTN2. This can be carried out arbitrarily in units of memory blocks in the manner shown in Table 1. therefore.

The area can be divided into blocks depending on the storage capacity required for each of the user area and the operating program area. As a result, when assigning areas with different uses to the memory cell array 2, it is possible to reflect the storage capacity required for each area, increasing the degree of freedom in design, and Memory space can be used effectively.

(2) Selection of an area defined by block division can be performed using a block selection control signal.

Furthermore, when one unit memory block to be selected according to the decoding results of address signals Ai'+1 to A i + is included in the group of the 41st memory block selected by the block division selection control, Since access to memory block 1 cock at IF is allowed, the block division control signals PT N 1 , PT
By managing N2 and block selection control signals C8t and C32, a special external circuit for access prohibition control can be used to prevent situations in which the program area is illegally changed beyond the user area. It is possible to easily prevent this without using it. Therefore, the system configuration can be set up for two purposes (seat space management or tγσ viewing).

(3) The above-mentioned effects can contribute to facilitating the system design of a microcomputer system including a semiconductor memory device.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, although the above embodiment has a configuration in which the results of block division and block selection control are reflected in the control of input/output gates, the present invention is not limited to this, and the results can be reflected in the control of other circuit units. It's okay to do that. Further, in the embodiment described above, the minimum east order for block division and block selection control is configured as a unit memory block, but the capacity and number of the order memory blocks are not limited to the above embodiment and can be changed as appropriate. Accordingly, the delay and type of external control signals for block division and block selection control can also be changed. Furthermore, the number of blocks that can be selected by block selection is not limited to two.

In the above explanation, the invention made by the present inventor was mainly applied to a RAM with a relatively large storage capacity, which is the field of application in which the invention was made, but the present invention is not limited to this, and・The present invention can be widely applied to various semiconductor storage devices including only memories.The present invention is widely applicable to at least those that require allocation of areas in a memory cell array for each purpose. be able to.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, since the memory cell array is divided into blocks with variable storage capacity and block selection is possible, it becomes possible to allocate multiple areas for different purposes to the memory cell array with relatively arbitrary capacities. This has the effect that memory space or address space can be used effectively.

In addition, since access management of areas defined by block division and block selection control can be performed using control signals for block division and block selection, it is possible to prevent unauthorized rewriting of other areas beyond a predetermined area. This has the effect of easily preventing such situations without using a special external circuit for access prohibition control, and it also makes it easier to manage access to address spaces set for each purpose in the system configuration or to monitor for unauthorized access. can be converted into

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a RAM according to an embodiment of the present invention. 1...RAM, 2...memory cell array, 4...
Write/read circuit, 5...address decoder, 6
... Controller, BLK1 to BLK8... Memory block, 10GI to 10G8... Input/output gate, 81 to S8... Gate control signal, PTNI, PTN
2...Block division control signal, C8I□, C3,2.
...Block selection control signal, A, ~A 1-(-1...
・Address signal, R/W...read/write signal.

Claims (1)

Claims: 1. A semiconductor memory device comprising control means for variably selecting a memory capacity and selecting a block in a memory cell array based on an external control signal. 2. The memory cell array is a set of unit memory blocks, and the control means selects a predetermined one or more unit memory blocks from among the plurality of unit memory blocks based on an external selection signal. The semiconductor memory device according to claim 1. 3. The control means is regarded as a signal for selecting one unit memory block from all unit memory blocks for one or more unit memory blocks selected based on an external control signal. 3. The semiconductor memory device according to claim 2, further comprising selection logic that allows access to one unit memory block selected by an address bit.