JPH02121032A - Microprogram control device - Google Patents

Abstract

PURPOSE:To shorten the cycle time of microprogram control by advancing the read-out timing of the contents of a branching condition field necessitated to determine the next address of control storage, and the determining timing of the next address based on the contents of the branching condition field read out at the timing. CONSTITUTION:A part of the control storage 10 i.e., the contents of the branching condition field of a microinstruction is inputted to an address control circuit 90 in an LSI 100 not through a microinstruction register 40, and simultaneously, the address which is selected from a multiplexer 80 and is latched in an address register 50 under the control of the address control circuit 90 is transmitted to a first control storage 20 installed in the LSI 100 at high speed. Accordingly, the read-out of the contents of the branching condition field of the microinstruction from the first control storage 20 and the determination of the address to be executed next based on this read out contents is performed at early timing. Thus, the cycle time of the microprogram control is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a microprogram control device equipped with a control memory in which a group of microinstructions constituting various microprograms is stored.

(Prior Art) In recent years, with the development of LSI (Large Scale Integrated Circuit) manufacturing technology, microprogram control devices and the like are also becoming LSI. However, control memory, which forms the core of a microprogram control device, requires an extremely large memory capacity, making it difficult to combine it with other peripheral circuits on the same LSI. It was generally made up of memory.

Conventionally, the cycle time of microprogram control in a microprogram controller is such that microinstructions read from control memory are stored in a microinstruction register (M
After the microinstruction is latched into the IR), the address of the control memory (microaddress) is selected under the control of the address control circuit (address sequencer) based on the contents of the branch condition field of the latched microinstruction. It was determined by the delay time from when the next microinstruction is read out to when it is latched into the microinstruction register. This delay time does not depend greatly on the performance of the control memory external to the LSI in a microprogram control device composed of a control memory composed of an independent memory and an LSI forming a peripheral circuit of this control memory. Of course, the address (microaddress) transmission path from the LSI to the external control memory, especially the LS
Delay (delay) in the output buffer provided inside I
, and the microinstruction LSI read from control memory.
The transmission path to the internal microinstruction register, especially the LS
The delay in the input buffer provided inside the I and the delay in the microinstruction register also depend greatly. That is, as the delay in the address transmission path increases, the reading of microinstructions from the control memory becomes slower.

If the readout of microinstructions becomes slow and the delay in the microinstruction transmission path described above becomes long,
There is a delay in inputting the contents of the branch condition field to the address control circuit. In this case, the address selection control by the address control circuit is delayed, resulting in a delay in the reading of the microinstruction that should actually be executed.

(Problem to be Solved by the Invention) As described above, in a conventional microprogram control device configured with a control memory provided outside an LSI in which its peripheral circuits are formed, the control memory is transferred from the LSI to the control memory external to the LSI. Delays in the path that transmits addresses, delays in the path that transmits microinstructions read from control memory to the microinstruction register inside the LSI, and delays in the microinstruction register have a significant effect on the cycle time of microprogram control. There was a problem in that the cycle time was lengthened.

Therefore, the problem to be solved by the present invention is to make it possible to easily shorten the cycle time of microprogram control.

[Configuration of the Invention (Means for Solving the Problems) This invention provides a control memory having a first control memory having a branch condition field for microinstructions, a field (main field) excluding the branch condition field, and a first control memory having a branch condition field for microinstructions. The first control memory of the first and second control memories is formed inside the LSI together with the control memory peripheral circuit, and the first control memory is configured with a second control memory that is commonly addressed. The contents of the branch condition field of the microinstruction read from the control memory are input to the address control circuit provided in the same LSI without going through the microinstruction register, and the address selected under the control of this control circuit is set as the address. Latch the first and second
It is characterized in that the control memory is commonly addressed.

(Function) According to the above configuration, a part of the control memory, that is, a part of the branch condition field of the microinstruction is provided in the same LSI together with the peripheral circuit of the control memory as the first control memory, and the branch condition field of the microinstruction is The contents of the address can be input to the address control circuit within the same LSI without going through the microinstruction register, and the address selected from the multiplexer and latched in the address register under the control of the address control circuit can be input to the address control circuit within the same LSI. Since the configuration allows for high-speed transmission to the first control memory, the contents of the branch condition field of the microinstruction can be read from the first control memory and the address control circuit can be configured based on the read contents. Address selection control (determining the next address to be executed) can be performed at a faster timing than before,
Therefore, the cycle time of microprogram control can be shortened.

(Embodiment) FIG. 1 shows a block configuration of a microprogram control device according to an embodiment of the present invention, and 10 is a control memory for storing various microprograms. The control memory IO is composed of a first control memory (partial control memory) 20 and a second control memory (partial control memory) 30.

The first control memory 20 and the second control memory 30 have the same size in the address direction, and are commonly addressed by an address (micro address) from the MAR 50, which will be described later.

First control memory 20. At the same address in the second control memory 30, the remaining field portions (referred to as main field portions) excluding the branch condition field portion 1 of one microinstruction are distributed and stored.

The main field includes a branch address field and a control field (for controlling each part). 21 is an output line for the content of the branch condition field of the microinstruction read from the first control memory 2o; 31 is an output line for the content of the branch address field in the main field of the microinstruction read from the second control memory 3o; 32 is the second control memory 3
Output line for the contents of the control field in the main field of the microinstruction read from zero.

40 is a microinstruction register (hereinafter referred to as MIR) that latches the contents of the control field in the main field of the microinstruction read out from the second control memory 30 to the output line 32; 50 is the first control memory 2o and the second control memory 2o; control memory 30
This is a micro address register (hereinafter referred to as MAR) for latching an address (micro address) for commonly addressing . 60 is an adder that adds 1 to the address output from the MAR 50, and 7o is a stack register of last-in first-out system (LIFO system).

This stack register 7o contains the microinstruction BAL.
(BAL microinstruction), the output data of the adder 6o is stacked, and the microinstruction RTN (R
TN microinstruction), the last stacked data (as a return address) is transferred to the stack register 70.
It is designed to be read from.

80 is the content (branch address) of the branch address field of the microinstruction read from the second control memory 30 to the output line 31, and the start address 81.80 of the microprogram given from the outside. A multiplexer (hereinafter referred to as MUX) selects one of the address read from the stack register 70 (return address) and the output data of the adder 60 (+1 address) and outputs it to the MAR5D.
), 9° inputs the contents of the branch condition field of the microinstruction read out from the first control memory 20 to the output line 21 and the address control signal 91 given from the outside, and based on the input contents, M U This is an address control circuit that controls 80.

The first control memory 2o, which forms part of the control memory 10, includes peripheral circuits of the control memory 10, such as an MIR40, a MAR50° adder 60, a stack register 70, and so on. Along with MUX80 and address control circuit 90, LSI 100
formed within. On the other hand, the second control memory 30 forming the remaining part of the control memory 10 is formed by an independent memory outside the LSI 100.

Next, the operation of the configuration shown in FIG. 1 will be explained.

First, the first control memory 2o and the second control memory 30 constituting the control memory 10 are accessed by the address latched in the MAR 50. As a result, the contents of the branch condition field of the microinstruction at the specified address are read out from the first control memory 20 onto the output line 21. Also,
From the second control memory 3o, the contents of the branch address field in the main field of the microinstruction at the specified address are read out to the output line 31, and the contents of the control field are read out to the output line 32, respectively.

The contents of the branch condition field read from the first control memory 20 to the output line 21 are directly input to the address control circuit 9o. An address control signal 91 from the outside is also input to this address control circuit 9o. The address control circuit 90 selects the control memory 10 to be designated next based on the contents of both inputs.
The addresses of (the first control memory 20 and the second control memory 30) are determined, and the MUX 8
0 is switched and controlled.

Under the control of the address control circuit 90, the MUX 80 receives the contents of the branch address field (branch address) from the second control memory 30 input via the output line 31, the microprogram start address 81 from the outside, and the stack register. Address from 70 (return address),
and output data of adder 60 (+1 address)
Select one. The address selected by this MUX 80 is latched into the M A R 50 and specifies the address of the control memory IO, that is, the address of the first control memory 20 and the second control memory 30. As a result, the contents of the branch condition field of the microinstruction at the designated address are read from the first control memory 20 and input to the address control circuit 90, where they are used to determine the next address. Further, the contents of the main field of the microinstruction at the specified address are read from the second control memory 30, and the contents of the branch address field in the main field are input to the MUX 80 as a candidate for the next address, and The contents are latched by the MIR 40 and used to control each part. Note that the address control circuit 90 receives an address incremented by 1 by the adder 60 during sequence operation, an address read from the stack register 70 when executing RTN of a microinstruction, and an address given from the outside when starting processing of a new microprogram. The MUX 80 is controlled so that the microprogram start address 81 to be executed and the contents of the branch address field (branch address) from the second control memory 30 are selected by the MUX 80 when executing a microinstruction branch. .

Now, the first control memory 20 forming a part of the control memory IO exists inside the LSI too like the address control circuit 90, and moreover, the branch condition field read from the first control memory 20 to the output line 21 is The contents are LSI 100
(via a very short internal path without going through a register)
Directly input to the address control circuit 90 and stored in the control memory 10
The next address of (the first control memory 20 and the second control memory 30) is determined. Therefore, this address determination timing is based on the control memory access time.
As in the past, all microinstructions read from the control memory outside the LSI are latched into a register via the input buffer inside the LSI, and then (based on the contents of the branch condition field in the register) the microinstructions are read from the control memory. This method is significantly faster than the method that determines addresses. For this reason, M U
The control timing of the X80 is also significantly faster than before. Furthermore, even if the control timing of the MUX 80 becomes earlier, the contents of the branch address field of the main fields from the second control memory 30 are input to the MUX 80 without going through the MIR 40, so that the branch There is no problem in selecting the address at the time.

The address selected by the MUX 80 under the control of the address control circuit 90 is latched by the MIR 40 as described above, and commonly specifies the addresses of the first control memory 20 and the second control memory 30. The first control memory 20 is MA
Like R50, it exists inside LSI 100, and the second
Since the control memory 30 exists outside the LSI 100, the address transmission path (referred to as the first path) from the MAR 50 to the first control memory 20 is the MAR 50.
It is significantly shorter than the address transmission path (referred to as the second path) from the first path to the second control memory 30, and unlike the second path, the first path does not require an output buffer. The delay of this second pass is almost the same as that of the conventional method (however, unlike the conventional method, it is a path that accesses a part of the control memory, so it is expected that the buffer delay will be shortened)
. Therefore, based on the address latch timing to the MIR4D, the first control memory 20 is accessed at an earlier timing than the conventional one, and the second control memory 30 is accessed at almost the same timing as the conventional one.

In this way, in this embodiment, the time from when the address selected by the MUX 80 is latched into the MIR 40 until reading the contents of the branch condition field of the microinstruction (necessary to determine the next address) is is shortened,
Furthermore, the time from reading the contents of the branch condition field to determining the next address is also shortened. That is, according to this embodiment, the address selected by MUX80 is MIR4.
After being latched to 0, the microinstruction specified by this latched address is read from the control memory 10, the address of the microinstruction to be executed next is determined, that address is selected by the MUX 80, and the microinstruction is sent to the MIR 40. The period until latching can be significantly shortened compared to the conventional method.

[Effects of the Invention] As detailed above, according to the present invention, the timing of reading the content of the branch condition field necessary to determine the next address of the control memory, and the content of the branch condition field read at this timing. Since the timing of determining the next address based on the current address can be made earlier than in the past, the cycle time of microprogram control can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogram control device according to an embodiment of the present invention. lO... Control memory, 20... First control memory, 30.
...Second control memory, 40...Microinstruction register (
M I R), 50... Micro address register (
M A R) 80...Multiplexer (MUX),
90...Address control circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] A microprogram control device equipped with a control memory in which microinstruction groups constituting various microprograms are stored, wherein the control memory is divided into a first control memory having branch condition fields of microinstructions, It has a main field excluding the branch condition field of the instruction and including a branch address field indicating the address of the branch destination, and is composed of a second control memory that is commonly addressed with the first control memory, and A candidate address group including the branch address indicated by the branch address field in the main field of the microinstruction read from the second control memory is input, and the next microinstruction to be executed is selected from among this candidate group. a multiplexer that selects an address; an address control circuit that inputs the contents of the branch condition field of the microinstruction read from the first control memory and controls the multiplexer based on the input contents; and an address control circuit that selects an address by the multiplexer. an address register that latches the address of the first control memory and specifies the address of the first and second control memories; A microprogram control device characterized in that the circuit and the address register are formed on the same integrated circuit element.