JP3043341B2 - Microcomputer system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microcomputer including a microprocessor and a memory.

[Conventional technology]

In recent years, microprocessors have been able to process instructions at very high speeds due to improved architecture.However, the access time of programs and data read from memory is shorter than the processing time of microprocessors due to access speed limitations. It is relatively long and causes a decrease in the instruction execution time of the microprocessor. In particular, when reading and inputting instruction codes stored at consecutive addresses as in a program, most of the processing time of the entire microprocessor is in a state of waiting for instruction codes from the memory, and the processing speed of the entire microcomputer system is reduced. Is decreasing.

The microcomputer shown in FIG. 10 has a microprocessor 1000 for controlling data input / output processing and the entire microcomputer, and a multiplexed address information and instruction code output from the microprocessor 1000 and instruction code and input data for demultiplexing. And a memory 1201 for storing processing data and a program of the microprocessor 1000, and these units are composed of an address data multiplex bus 1301.
(Hereinafter referred to as “AD” bus) and the microprocessor 100
0 is a row active read signal (hereinafter referred to as “RA signal”) 1302 output to read data and a program stored in the memory 1301, and an ASTB signal 1303 output to store an address in the address latch 1205. And are connected by.

Next, the flow of address information and data on the microprocessor 1000 and the AD bus in the continuous input of a program arranged at consecutive addresses will be described with reference to FIG.

Normally, the programs are stored sequentially in a continuous memory area, and the microprocessor 1000 reads and executes these programs in accordance with the address order via the AD1301, and the program input is performed as shown in FIG. , B ₁ , B ₂ , and B ₂ .

First, the microprocessor 1000, B ₁ to the state period, AD bus 1301 a read address from the same time B ₁ state when activating the ASTB signal 1303 over the B ₂ state
Output to the top. To the RD signal 1302 to "0" in the middle of the subsequent B ₂ state, to "1" in the middle of the B _3-state. This RD signal
The 1302 active period of the read data from the memory 1201 on the AD bus 1301, a microprocessor 1000, takes in the data on the AD bus 1301 at a predetermined timing B _3-state.

One cycle of the program input data read cycle is completed by the above series of processing.

[Problems to be Solved by the Invention] As described above, although the addresses of the instructions to be executed are continuous unless an instruction that changes the processing sequence such as a branch instruction is executed, the conventional microcomputer has a The processing speed for generating addresses is slow.

Accordingly, an object of the present invention is to provide a microcomputer system with an improved processing speed.

[Means for solving the problem]

A microcomputer system according to the present invention is a microcomputer system having storage means for storing various types of processing data including instruction codes, and data processing means for performing data processing by executing instructions, wherein an address for storing address information of the storage means is provided. Indicating means, updating means for updating the content stored by the address indicating means,
Holding means for holding the output of the storage means designated and read by the address designating means, control means for controlling the updating means and controlling the holding means in synchronization with an operation clock of a microcomputer system; A first data transfer between the storage means designated and the data processing means following transmission of read address information to the address designating means in data transfer between the storage means and the data processing means; The data transfer means and the control means are controlled to an operating state, and the holding means holds read data from the storage means corresponding to the contents of the address indicating means, and the address indicating means sets the next address to be read. By storing in advance, the holding means and the data processing can be performed without sending out address information. And a second data transfer means for performing continuous data transfer between the stages.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, the microcomputer system includes a microprocessor 100 for controlling data input / output processing, arithmetic processing, and the entire microcomputer, and a read-only memory ROM 210 (for storing programs executed by the microprocessor 100 and data necessary for arithmetic operations). (Hereinafter referred to as “memory”).

The microprocessor 100 stores a processing execution unit 101 that executes instructions, an execution control unit 103 that controls the operation of the entire microprocessor 100, and instructions and data read from the memory 210 in the order in which they are read. It comprises a data queue 102 for outputting stored contents in response to a request, and an oscillator 108 for generating a clock signal 307 for operating the microprocessor 100.

From the processing execution unit 101 to the execution control unit 103, a memory 210 in the LSI 200 and a bus request signal 105 requesting activation of a data read cycle and a memory 210
An address line 104 carrying the address information of the access destination is output, and the execution control unit 103 outputs an acknowledgment signal 106 to the processing execution unit in response to the activation of the data read cycle. The microprocessor 100 controls the LSI via an AD bus 300 in which address information and data are multiplexed.
Data is read from the memory 210 in the memory 200. Oscillator 108
The clock generated from is supplied to the microprocessor 100 as a basic operation clock, and is also input to the LSI 200 as a synchronous clock for reading out instructions and data.

In LSI 200, to microprocessor 100 and the interface receives an output from the microprocessor 100, a control signal _{C 1, C 2, C 3} , C 4, the bus interface unit 201 which generates a C _6, the microprocessor 100 A pointer FP 204 (which is input from the memory 210 for storing programs and data and the AD bus 300 and is written with address information via the bus interface unit 201 and an address bus (hereinafter referred to as “ADR bus”) 218 inside the LSI 200) and C ₂ signal is controlled by) output during the read cycle of the instruction code, and another pointer DP207 (controlled by C ₃ signal output during the read cycle of the data), the incrementer to increment the contents of the FP203 and 205, Increment is controlled by the C ₁ signal output when continuous instruction reading cycle and the continuous data read cycle will be described later 20
Multiplexer MPX1 203 to select 5 outputs and DP206
Incrementer 208 to increment the contents of the C ₁
A multiplexer 207 for selecting the output of the incrementer 208 in synchronization with a signal, based on the C ₆ signal output when continuous instruction code read cycle, the internal address bus to the memory 210 selects the output of the FP203 (hereinafter "AB A multiplexer 209 for supplying as a bus 219, a code latch (hereinafter, referred to as “CDL”) 211 for storing data read from the memory 210 based on the C ₂ signal output during a continuous instruction code read cycle, based on the C ₃ signal output similarly in the continuous data read cycle, the memory 210
A data latch 212 for storing data read from the
A read buffer 221, 222, 223 is selected from the output latch 1 211, the output latch 2 212, and the output of the memory 210 based on the control signals C ₄ , C ₆ and the output of the NOR gate 219 and read out to the ADR bus 218. ing. Also NOR gate
The C ₄ and C ₆ signals are input to 219, and when both the C ₆ and C ₄ signals are “0”, the output of the NOR gate 219 becomes “1”.

Next, control signals input to and output from the microprocessor 100 and the LSI 200 will be described.

As an input control signal to the microprocessor 100,
There is a reset signal 306 for initializing hardware in the microprocessor 100. As a control signal from the microprocessor 100 to the LSI 200, an ASTB signal 301 for storing address information on the AD bus 300 in the FP 203 or the DP 206, and a row active RD signal 302 for reading data from the memory 210, , and M ₁ signal 304 for setting the read mode from the memory 210, and M ₂ signal 305 that controls the reading of the continuous instruction code and data will be described later, and sets the read mode, the continuous instruction code read will be described later and There is a basic operation clock CL307 of the microprocessor 100 used as a synchronization clock in a continuous data read cycle.

When ASTB signal 301 is "1", the read operation of the LSI200 by the level of both signals M ₁ signal 304, M ₂ signal 305 is set.

When ASTB signal 301 is "1", each level of the M ₁ signal 304, M ₂ signal 305 to "0", when the "0", the continuous data read cycle is set. Also, each level of the M ₁ signal 304, M ₂ signal 305 to "0", when the "0", the continuous data read cycle is set. Similarly, M ₁ signal 304, M ₂ signal 30
When the levels of 5 are “0” and “1”, one data read cycle is set.

Next, FIG. 2 shows a detailed diagram of the control signal generation unit 202 and will be described. Flip-flop (hereinafter referred to as “F / F”) 400
Writes the level of M ₂ signal at the rise timing of the CLK307. F / F411,412,413,414 the fall timing of ASTB signal, writes the level decoded by M ₁ signal 304, M ₂ decode 410 the level of the signal 303. Also F / F411,413,4
14 is cleared to “0” by the signal generated from the rising edge detection circuit 409 at the rising timing of the ASTB signal 305. Decoder 410, the level of the M ₁ signal 304, M ₂ signal 305 is "1", "0", "1", "1", "0", "1", when "0", "0" In order to write “1” to F / F411,412,413,414 respectively,
Set the corresponding signal output to “1”. F / F416 writes the output of the F / F 411 at the fall timing of the M ₁ signal 304. F / F411,
At 412, 413, and 414, "1" is written in the address setting cycle of the continuous instruction code read cycle, the read cycle of the continuous instruction code read cycle, the continuous data read cycle, and one data read cycle.
The output of the F / F 416 is written to the F / F 417 at the rising timing of the CLK 307. Control signal C ₁ is a signal which becomes "1" when a cycle of reading the contents of the continuous memory 210. The control signal C ₂ is output in a continuous instruction code read cycle.
M ₂ signal 305 is "0" in CLK307 is "0" and M ₁ signal 304 is a signal which becomes "1" when "1". Control signal C ₃ is a signal which becomes "1" when the continuous time data read cycle, M ₂ signal 303 is "0" in CLK307 is "0" when and ASTD signal 301 is "1". Control signal C ₄ is, RD when one data read cycle
This signal is “1” when the signal 301 is “0”. Control signal C
Reference numeral ₆ denotes a signal which becomes "1" in a continuous instruction code read cycle.

Next, the operation of the continuous instruction code read cycle will be described with reference to FIG. Continuous instruction code read cycle, the basic state for address setting (hereinafter referred to as "BR-state") and continuously reads the instruction code B _5, B
_The execution control unit 103 composed of ₆ and B ₇ states (hereinafter referred to as “CNF state”)
By outputting various control signals to 0, the instruction code read cycle of the memory 210 accompanying the instruction execution is controlled. Incidentally, when continuing the continuous instruction code reading continues B ₆ states.

First, the microprocessor 100, ASTB by B ₁ state
A signal 301 to "1", the M ₁ signal 304 to "1", the M ₂ signal 305 to "0", and outputs the address "N" on the AD bus 300. In the LSI 200, the control signal generation unit 202 sets the control signals C ₂ and C ₃ to “1”,
The address “N” is written to the DP 206 via the address latch 221 and the MPX2 207.

Next, when the ASTB signal 301 in the middle of the B ₁ states falls, F
The output of / F411 becomes "1". When the ASTB signal 301 falls to “0”, the control signal C ₂ becomes “1” and the content “N” of DP 206 is changed to FP2
Write to 03 via MPX204.

Next, down M ₁ signal 304 in the middle of B ₂ states standing,
The control signal C ₂ becomes “0”, and the content “N” of the FP 203 becomes MPX3 209
Is supplied as AB bus 219 to the memory 210 via the
An instruction code (N) corresponding to the address “N” is output from 210.

Next, when B _3-state in CLK307 becomes "1", the output becomes "1" of F / F 417, the control signal C ₁ is "1" MPX1 20
4 selects the output of the incrementer 205. When B ₃ in state intermediate CLK307 becomes "0", the control signal C ₂ is "1" and the output of the memory 210 (N) is written to the output latch 1 211. Further, 1 is added by the incrementer 204, and the address “N + 1” next to N is written to the FP 203. At the same time the control signal C ₆ is for "1", the contents of the output latch 1 (N) is output to the bus interface unit 201, RD signal 3
Since 02 is “0”, the output buffer 223 conducts, and data (N) is read onto the AD bus 300. Then, the execution control unit 103
Process is entered at the timing of the CLK307 of B ₄ states "1", and transfers the data queue 102 (N), the execution processing unit 101 which decodes the instruction code (N), corresponding to the instruction code (N) Execute

Then, M ₂ signal 303 B ₄ state becomes "1". When B ₄ in the state intermediate CLK307 is "0", the control signal C ₂ is "1"
The instruction code (N + 1) corresponding to the address "N + 1" is written into the output latch 1211.
The subsequent address “N + 2” is written in 3. At this time, the RD signal 302 becomes “1” at the same time, so that the bus interface unit 201 does not output anything on the AD bus 300. B ₅ states beginning M ₁ signal 304 rises in becomes a "1", F / F411,413,
414 becomes “0” and F / F 412 becomes “1”, but the control signal C ₁
And C ₆ remain “1”. The M ₂ signal 303 becomes "0". Since the RD signal 302 at an intermediate B ₅ state is "0",
The instruction code (N + 1) is read onto the AD bus 300.
Further, CLK307 but becomes "0", since the M ₂ signal 305 is at a "1" in B ₄ states, the B ₅ state, inverter
The output of 401 is a "0", the control signal C ₂ remains "0".

Then the output of the inverter 401 in the middle of the B ₆ states "1"
Therefore, when the CLK 307 becomes “0”, the control signal C ₂ becomes “1” and the instruction code corresponding to the address “N + 2” (N
+2) is written to output latch 1211 and AD
The instruction code (N + 2) is read onto the bus 300. At the same time, the subsequent address (N + 3) is written to the FP 203. Similarly, instruction code corresponding to the even address "N + 3" in the next B ₆ states (N + 3) are read on the AD bus 300.

At the end of the B ₇ states, M ₂ signal 305 becomes "1". Also B
_{Since the} RD signal 302 becomes "1" in the middle of the _seven states, the bus interface unit 201 sets the AD bus 300 after the instruction code (N + 3).
Do not output anything above. B In the middle of the ₇ states, the control signal
Since C ₂ becomes "1", FP203 address "N + 5" becomes, CDL211 instruction code corresponding to the address "N + 4" (N + 4) is written continuously instruction code read cycle is completed. The B ₇ states next state, the output of the inverter 401 becomes "0", the control signal C ₂ remains "0".

As described above, in the continuous instruction code read cycle, FP
Using 203 and CDL211, in synchronization with the rise of CLK307,
The instruction code stored in the memory 210 is continuously read onto the AD bus 300, and the microprocessor 100 executes a corresponding process.

Next, one data read cycle will be described with reference to FIG. One data read cycle is
B _1, B _2, B ₃ is composed of a state. In the B ₁ state,
The microprocessor 100, the ASTB signal 305 _"1", M 1 signal 3
04 "0", the M ₂ signal 303 to "1". Further, the address “K” is output on the AD bus 300.

Then, since the control signal C ₃ is "1", the address "K" is written on the DP207, data corresponding to the address "K" of the memory 21 is accessed. AS in the middle of B ₁ state
When the TB signal 301 becomes “0”, the output of the F / F 414 becomes “1”. When RD signal 302 becomes "0" at B ₂ state, the control signal C
₄ becomes “1”, the output buffer 222 conducts, and the address “K”
Is read out onto the AD bus 300 in the memory 210 corresponding to. Microprocessor 10 in the middle of B ₃ states
0 sets the RD signal 302 to “1”. Microprocessor 100
At a predetermined timing of B _3-state, enter the data (K), the process execution unit 103 is used in the calculation as data. Once the data read cycle in the control signal C ₂ is "0" for the left, the contents of the FP203 remains unchanged at address "1".

Next, a continuous data read cycle will be described with reference to FIG. Continuous data read cycle, B _1, B _2,
It is composed of B _3, B ₄ cycles, successively, when the data is read B _3-state are repeated. In B ₁ state, the microprocessor 100, the ASTB signal 305 _"1", M 1
A signal 304 to "0", the M ₂ signal 303 to "1". Also, AD bus 3
The address “L” is output on 00. Then, the control signal C ₃ is "1" next to the address latch 221 the address "L" is stored, the address "L" is written to the DP207 simultaneously. In the middle of the B ₁ state, F / F 414 is "1". B ₂ states
ASTB signal 305 is "1", since the M ₂ signal 303 becomes "0", since the F / F 413 in the middle of the B ₂ state is "1", the control signal C ₁ is set to "1". The address “L” is supplied to the memory 210 via the MPX3 209, and the data (L) in the memory 210 corresponding to the address “L” is read. When B ₃ in state intermediate CLK307 is "0", the control signal C ₃ is "1", data (L) is written to DTL212. At the same time, since the control signal C ₁ is “1”, the address “L + 1” which is the output of the incrementer 208 is written to the DP 206. Also, since the control signals C ₄ and C ₆ are both “0”, the NOR gate 219
Becomes “1”, the read buffer 222 becomes conductive, and data “L” is output onto the ADR bus 216. The bus interface unit 201 outputs data “L” on the AD bus 300. The microprocessor 100 of the next B _3-cycle CLK30
Data (L) is input at the timing when 7 is "1". Continue B
The same operation is performed in _three states. The microprocessor 100 at the end of the B ₃ state, the M ₂ signal 305 to "1". Then the output of the inverter 401 becomes "0" in B ₄ state, the control signal C ₆ be CLK307 with B ₄ states at "0" is not outputted. B ₄ states, microprocessor 100
Sets the RD signal 302 to "1" and ends the continuous data read cycle.

As described above, in the continuous data read cycle, CLK3
In synchronization with the fall of 07, the content of DP207 is updated, and the data of the memory 210 corresponding to the content of DP206 is
It can be read continuously. At this time, the control signal C ₂
Remains unchanged at "0", the contents of the FP 203 do not change. As described above, in the microcomputer described above, by the microprocessor 100 controls the M ₂ signal 305, in synchronization with the basic operation clock of the microprocessor, continuously the instruction code from the memory 210, data to be read it can. One data read can also be performed.

Next, a second embodiment of the present invention will be described with reference to FIGS.

The microcomputer shown in FIG. 3 is different from the microcomputer shown in FIG. 1 in that the memory 210 is composed of a random access memory (RAM) capable of reading and writing data, and a row active write signal WR303, A control signal C ₅ and a write buffer 224 are added. Therefore, in the present embodiment, the parts different from FIG. 1 will be described. The microprocessor 100 supplies the LSI 200 with a WR signal 303 for writing the write data to be output on the AD bus 300 to the memory 210 following the address. In FIG. 4, when the output of the F / F 414 is “1” and the R signal 303 is “0”, the output of the AND gate 500 becomes “1” and the control signal C ₅ “1” which is the output of the OR gate 504 Becomes Also, F / F50
3 writes the output of the inverter 401 at the falling timing of the CLK 307. When the output of the F / F 413 is “1”, the output of the F / F 503 is “1”, and the CLK 307 is “1”, the output of the AND gate 502 becomes “1” and the control signal C ₅ which is the output of the OR gate 504 Becomes “1”. When the control signal C ₅ is set to "1", the write data memory 2 on AD bus 300 because the write buffer 224 is dynamic state
Written to 10.

Next, a continuous data write cycle in which the microprocessor 100 continuously writes data in the memory 210 will be described with reference to the timing chart of FIG. Continuous data cycle
_{B 1, B 2, B 3} , B 4 and a state. The B ₁ and B ₂ states are the same as those in the data read cycle, and will not be described. B ₃ states, microprocessor 100 is W
The R signal 302 is set to “0”, and data (M) to be written to the address of the memory 210 corresponding to the address “M” is output on the AD bus 300. Since the output of the F / F503 in the middle of the B _3-state becomes "1", since the control signal C ₅ at the timing of the CLK307 the next B ₃ state is "1" becomes "1", the write buffer 22
3 becomes conductive, and the data (M) on the AD bus 300 is written to the memory 210 via the bus interface unit 201. The same operation in the subsequent B _3-state. Since M ₂ signal 305 becomes "1" at the end of the B _3-state, B the control signal C ₅ after the control signal C ₅ becomes "1" at the _four states "0"
Remains. B ₄ data corresponding to the address "M + 3" in the state (M + 3) is written into the memory 210.

In the above two embodiments, the internal bus ADR bus 218 of the LSI 200
Is a multiplex bus, but FIG. 9 shows a third embodiment in which the address bus and the data bus are constituted by separate buses.

The microcomputer shown in FIG. 9 adds an address latch 331 and replaces the ADR bus 218 with the address latch 331.
Address bus (hereinafter referred to as "A bus") 33
2 and multiplexer instead of output buffer 221,222,223
Except for adding an MPX4 332 and a data bus (hereinafter referred to as “D bus”) which is the output of the MPX4 332,
The configuration is the same as that of the microcomputer shown in FIG.

Therefore, in the present embodiment, portions different from FIG. 1 will be described. The LSI 200 stores the address information input from the microprocessor 100 in the address latch 331 during the "1" period of the ASTB signal 305, and outputs the address information stored in the address latch 331 to the MPX2 207 as the A bus 332. I do. MPX1 outputs the FP203 selects the output of the output or DP206 the incrementer 205 by the control of the C ₁ signal. MP
X2 and outputs the DP206 selects the output of the output or the A bus 3312 from the incrementer 208 by the control of the C ₁ signal.

MPX3 209, based on C ₆ signal and ASTB signal 301 which is output in the continuous instruction code read cycle, FP203, A Bus
332 or the output of the DP 206 is selected and output to the memory 210.
CDL211, based on C ₂ signal output when continuous instruction code read cycle, and stores the data read from the memory 210. Similarly DTL212 is based on C ₃ signal output when continuous read cycle, stores the data read from the memory 210. The MPX4 223 selects the output of the CDL 211, the DTL 212, and the memory 210 based on the control signals C ₄ and C ₆ and the output of the NOR gate 219, and outputs the selected signal to the D bus 234.

Next, the operation of the continuous instruction code read cycle will be described with reference to FIG. In the continuous instruction code read cycle, an instruction code is read continuously with a basic state for setting an address (hereinafter, referred to as a “BR state”).
B ₅ , B ₆ , and B ₇ states (hereinafter, referred to as “CNF state”).
By outputting various control signals to the SI 200, the instruction code read cycle of the memory 210 accompanying the instruction execution is controlled. To continue reading the continuous instruction code,
B Continue ₆ states.

First, the microprocessor 100, ASTB by B ₁ state
A signal 301 to "1", the M ₁ signal 304 to "1", the M ₂ signal 305 to "0", and outputs the address "N" on the AD bus 300. In the LSI 200, the control signal generation unit 202 sets the control signals C ₂ and C ₃ to “1”,
The address “N” is written to the DP 206 via the address latch 232 and the MPX2 207.

Next, when the ASTB signal 301 in the middle of the B ₁ states falls, F
The output of / F411 becomes "1". When ASTB signal 301 is falling "0", the control signal C ₂ is "1" the content of the next DP206 "N" FP2
Write to 03 via MPX204.

Then, M ₁ signal 304 in the middle of B ₂ states I falling, the control signal C ₂ is set to "0", the contents of the FP203 "N" is supplied as the AB bus 219 to the memory 210 via the MPX3 209 , Memory 21
From 0, an instruction code (N) corresponding to the address "N" is output.

Next, when B _3-state in CLK307 becomes "1", the output becomes "1" of F / F 417, the control signal C ₁ is "1" MPX1 20
4 selects the output of the incrementer 205. When B ₃ in state intermediate CLK307 becomes "0", the control signal C ₂ is "1" and the output of the memory 210 (N) is written to the output latch 1 211. Further, 1 is added by the incrementer 204, and the address “N + 1” next to N is written to the FP 203. At the same time the control signal C ₆ is for "1", the contents of the output latch 1 (N) is output to the bus interface unit 201 via the RD bus 214, RD signal 302 is "0" the output buffer 223 is rendered conductive for , Data (N) is read onto the AD bus 300. Then, the execution control unit 103 inputs the timing of CLK307 of B ₄ states "1", and transfers the data queue 102 (N),
The execution processing unit 101 decodes the instruction code (N) and executes a process corresponding to the instruction code (N).

Then, M ₂ signal 303 B ₄ state becomes "1". When B ₄ in the state intermediate CLK307 is "0", the control signal C ₂ is "1"
The instruction code (N + 1) corresponding to the address "N + 1" is written into the output latch 1211.
The subsequent address “N + 2” is written in 3. At this time, the RD signal 302 becomes “1” at the same time, so that the bus interface unit 201 does not output anything on the AD bus 300. B ₅ states beginning M ₁ signal 304 rises in becomes a "1", F / F411,413,
414 becomes “0” and F / F 412 becomes “1”, but the control signal C ₁
And C ₆ remain “1”. The M ₂ signal 303 becomes "0". Since the RD signal 302 at an intermediate B ₅ state is "0",
The instruction code (N + 1) is read onto the AD bus 300.
Further, CLK307 but becomes "0", since the M ₂ signal 305 is "1" in B ₄ states, the B ₅ state, inverter
The output of 401 is a "0", the control signal C ₂ remains "0".

Then the output of the inverter 401 in the middle of the B ₆ states "1"
Therefore, when the CLK 307 becomes “0”, the control signal C ₂ becomes “1” and the instruction code corresponding to the address “N + 2” (N
+2) is written to output latch 1211 and AD
The instruction code (N + 2) is read onto the bus 300. At the same time, the subsequent address (N + 3) is written to the FP 203. Similarly, instruction code corresponding to the even address "N + 3" in the next B ₆ states (N + 3) are read on the AD bus 300.

At the end of the B ₇ states, M ₂ signal 305 becomes "1". Also B
_{Since the} RD signal 302 becomes "1" in the middle of the _seven states, the bus interface unit 201 sets the AD bus 300 after the instruction code (N + 3).
Do not output anything above. B In the middle of the ₇ states, the control signal
Since C ₂ becomes "1", FP203 address "N + 5" becomes, CDL211 instruction code corresponding to the address "N + 4" (N + 4) is written continuously instruction code read cycle is completed. The B ₇ states next state, the output of the inverter 401 becomes "0", the control signal C ₂ remains "0".

As described above, in the continuous instruction code read cycle, FP
Using 203 and CDL211, in synchronization with the rise of CLK307,
The instruction code stored in the memory 210 is continuously read onto the AD bus 300, and the microprocessor 100 executes a corresponding process.

Next, one data read cycle will be described with reference to FIG. One data read cycle is
B _1, B _2, B ₃ is composed of a state. In the B ₁ state,
The microprocessor 100, the ASTB signal 305 _"1", M 1 signal 3
04 "0", the M ₂ signal 303 to "1". Further, the address “K” is output on the AD bus 300.

Then, since the control signal C ₃ is "1", the address "K" is written on the DP207, data corresponding to the address "K" of the memory 210 is accessed. B In the middle of _one state
When the ASTB signal 301 becomes “0”, the output of the F / F 414 becomes “1”. When RD signal 302 becomes "0" at B ₂ state, the control signal C
₄ becomes “1”, the output buffer 222 in the bus interface unit 201 becomes conductive, and the data (K) of the memory 210 corresponding to the address “K” is read out onto the AD bus 300 via the RD bus 214. B Microprocessor 100 is R in the middle of ₃ states
The D signal 302 is set to “1”. Microprocessor 100, B ₃
At a predetermined timing of the state, the data (K) is input, and the processing execution unit 103 uses the data (K) in the calculation. 1
Times of data read cycle in the control signal C ₂ is "0" for the left, the contents of the FP203 remains unchanged at address "1".

Next, a continuous data read cycle will be described with reference to FIG. Continuous data read cycle, B _1, B _2,
It is composed of B _3, B ₄ cycles, successively, when the data is read B _3-state are repeated. In B ₁ state, the microprocessor 100, the ASTB signal 305 _"1", M 1
A signal 304 to "0", the M ₂ signal 303 to "1". Also, AD bus 3
The address “L” is output on 00. Then, the control signal C ₃ is "1" next to the address latch 221 the address "L" is stored, the address "L" is written to the DP207 simultaneously. In the middle of the B ₁ state, F / F 414 is "1". B ₂ states
ASTB signal 305 is "1", since the M ₂ signal 303 becomes "0", since the F / F 413 in the middle of the B ₂ state is "1", the control signal C ₁ is set to "1". The address “L” is supplied to the memory 210 via the MPX3 209, and the data (L) in the memory 210 corresponding to the address “L” is read. When B ₃ in state intermediate CLK307 is "0", the control signal C ₃ is "1", data (L) is written to DTL212. At the same time, since the control signal C ₁ is “1”, the address “L + 1” which is the output of the incrementer 208 is written to the DP 206. Also, since the control signals C ₄ and C ₆ are both “0”, the NOR gate 219
Becomes “1”, the output of DTL212 is selected and the RD bus
Output on 214. At this time, since the RD signal 302 is “0”, the output buffer 222 becomes conductive, and the instruction code (L +
1) is read onto the AD bus 300. Microprocessor 1
00 inputs timing data (L) of the CLK307 the next B _3-cycle "1". It performs the same operation in the subsequent B _3-state. The microprocessor 100 at the end of the B ₃ state, M ₂
The signal 305 is set to “1”. Then inverter 4 in B ₄ state
Since the output of 01 is "0", CLK307 with B ₄ states "0"
Control signal C ₆ also becomes is not output. B ₄ states,
The microprocessor 100 sets the RD signal 302 to "1" and ends the continuous data read cycle.

As described above, in the continuous data read cycle, CLK3
In synchronization with the fall of 07, the content of DP207 is updated, and the data of the memory 210 corresponding to the content of DP206 is
It can be read continuously. At this time, the control signal C ₂
Remains unchanged at "0", the contents of the FP 203 do not change. As described above, in the microcomputer described above, by the microprocessor 100 controls the M ₂ signal 305, in synchronization with the basic operation clock of the microprocessor, continuously the instruction code from the memory 210, data to be read it can. One data read can also be performed.

As described above, it is clear that the effect of the high-speed memory access is not impaired even if the bus is constituted by separating the address and the data.

〔The invention's effect〕

As described above, according to the present invention, particularly in a system that requires high-speed program reading and data reading, it is necessary to add a high-speed reference function to the storage device itself. The output latch that holds the data read from the memory continuously reads ahead the data corresponding to the instruction code or data next to the instruction code read on the AD bus, and continuously outputs the basic operation clock of the microprocessor. Instruction code and data are read periodically, the instruction code and data read operations are performed almost simultaneously with the microprocessor operation, and there is almost no delay, so the access time is very short and high speed. Instruction code and data are read continuously, and the processing capability of the microprocessor It is effective to provide a high-performance microcomputer can provide memory to improve.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first microcomputer embodying the present invention, FIG. 2 is a detailed diagram of a signal generator of FIG. 1,
FIG. 3 is a block diagram of a second microcomputer embodying the present invention. FIG. 4 is a detailed diagram of a circuit (write control) added to FIG. 2 by a control signal generator used in FIG. The figure shows the timing chart of the continuous instruction code read cycle,
FIG. 6 is a timing diagram of one data read cycle,
FIG. 7 is a timing chart of a continuous data read cycle, FIG. 8 is a timing chart of a continuous data write cycle, and FIG.
FIG. 1 is a block diagram of a third microcomputer embodying the present invention, FIG. 10 is a block diagram of a conventional microcomputer, and FIG. 11 is a timing diagram of a data read cycle in a conventional example.

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Claims (1)

(57) [Claims] 1. A microcomputer comprising: storage means for storing data including an instruction code; and data processing means for performing data processing by executing an instruction, wherein the storage means and the data processing means are connected via a bus. In the system, the storage means includes: an address instructing means for storing address information; an updating means for updating contents stored in the address instructing means; and an output of storage data instructed and read by the address instructing means. Holding means for holding, means for selectively transferring an output of the holding means and an output of the read storage data to a data processing means, and controlling the updating means based on a control signal output from the data processing means And a control unit for controlling the holding unit, wherein the data processing unit performs one-time data transfer with the storage unit. Selectively outputting a first data transfer mode signal for requesting and a second transfer mode signal for requesting continuous data transfer, wherein the storage means responds to the first mode signal to execute the data processing. Means for transferring data at an address designated by the means to the data processing means via a bus line, and in response to the second mode signal, transferring data already read and held by the holding means to the bus line; And the updating of the address of the address indicating means and the reading of the data at the next address are performed in parallel, and without sending the address from the data processing means for each data transfer, the storage means sends the data to the data processing means. A microcomputer system for continuously transferring data via the bus line without interruption.