JP2721611B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller having a processor capable of pipeline processing.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, for the purpose of improving the processing speed of a programmable controller, a coprocessor dedicated to instruction execution which operates in parallel with a conventional general-purpose main processor 11 is used. It has been proposed to provide 21. Coprocessor 21
In order to speed up the processing, it has been considered to use a reduced instruction set processor (RISC processor). In this case, the source code of the sequence program designed by the user or the like and stored in the source program memory 12 is compiled and converted into a reduced instruction, and then stored in the object program memory 22. The processing is executed by the coprocessor 21 based on the object code including the reduction instruction stored in the memory 22. Compilation of the source code is performed by the main processor 11 using a compiler stored in the system memory 13. The main processor 11 is not used for executing the instructions of the sequence program, but is used for compiling the source code and for controlling peripheral devices and communication performed through the interface 14. Communication between the main processor 11 and the coprocessor 21 is performed via the bus controller 15. Here, the data bus of the main processor 11 has 16 bits, and the data bus of the coprocessor 21 has 32 bits with the object program memory 22 and 16 bits with the data memory 23. Bus controller 15
Has a function of connecting the 16-bit data bus of the main processor 11 and the 32-bit data bus of the coprocessor 21. The internal processing of the coprocessor 21 is 3
The instruction is executed in two bits, so that the instruction can be executed faster than the main processor 11 in combination with the RISC processor.

[0003] The relationship between the source code and the object code is as shown in FIG. For example, when the source code has three instructions and the number of words in each instruction is 2, 4, and 4, the number of words in the object code using the reduced instruction is, for example, 3 for each instruction in the source code. ,
7, 5, etc. In the object code, one word corresponds to one instruction. In the above example, one instruction using two words in the source code is three instructions in the object code.

[0004]

By the way, the instruction set of the coprocessor 21 is provided with a so-called pulse-type application instruction as an application instruction accompanied by differential processing for detecting a rising or falling edge of an input. In addition, the pulse-type application instruction usually has a form in which the differential processing is performed only for one scan, not for each scan. This kind of pulse type application instruction is prepared for most application instructions. For example,
Instruction PAD for performing differential processing before ADD which is an addition instruction
D and an instruction PMV for performing a differentiation process before an MV which is an instruction for transferring data in word units. When the pulse-type application instruction is used, processing that normally becomes two instructions of a differentiation instruction and an application instruction can be performed by one instruction, so that the memory capacity of the object program memory 22 is saved and the execution speed is improved. .

Now, the object program is shown in FIG.
Assume that it is as shown in FIG. Here, an instruction PADD, which is a pulse-type application instruction that detects the rising of the input only once and performs addition, is used. When the input X0 rises from off to on, an addition operation is performed, and the output Y30 is turned on. This processing is performed only for one scan, and the addition operation is not performed in subsequent scans. To perform such processing, it is necessary to hold the value of the input X0 of the previous scan. That is, in order to execute the instruction PADD in only one scan, it is necessary to keep the input X0 on once after the input X0 rises from off to on. By keeping it on after the scan, the instruction PADD
To prevent the rise from being detected and prevent the addition operation from being performed. In order to maintain the on / off state of the input X0 in this manner, as shown in FIG.
It is considered to provide a data memory 23 having the same address as the object program memory 22 and each memory cell having one bit.

For example, as shown in FIG. 5B corresponding to the ladder diagram of FIG. 5A, an instruction to take input X0 at address 0 of object program memory 22, and input X0 and data memory at address 1 It is assumed that an instruction for detecting the presence or absence of a rise by comparison with the value held in 23 and an instruction for outputting an output Y30 at address 2 are stored. When the instruction at address 0 is executed and the input X0 rises from off to on, at address 1, the data memory 23
Input X0 of the previous scan stored at address 1 of
(In the initial state, the input X0 is off.) And the input X0 obtained by executing the address 0 is detected to detect a rise, and an addition operation is performed. Thereafter, the output Y30 is obtained. Here, once the input X0 is turned on, since the address 1 of the data memory 23 is kept on thereafter,
Even if the input X0 fetched at the address 0 is on, the addition operation is not performed at the address 1.

On the other hand, as shown in FIG. 6, the execution speed of the coprocessor 21 is improved by performing pipeline processing. That is, when executing instructions in the coprocessor 21, an instruction fetch cycle IF for fetching instructions one by one from the object program memory 22, a decode cycle DEC for decoding fetched instructions, and an execution cycle EXE for executing decoded instructions Usually, it is necessary to reduce the execution time of the instruction by repeating the operation of fetching the next instruction during the decoding of one instruction. Here, instruction fetch cycle IF, decode cycle DEC, execution cycle EX
E is one machine cycle, and one machine cycle is defined, for example, for three cycles (six phases) of a clock signal.

The coprocessor 21 includes a bit processing unit that executes a basic instruction that is a 1-bit instruction, and the bit processing unit includes a bit accumulator that is an accumulator that holds 1-bit data on which arithmetic processing is performed. If the input X0 fetched at the address (0) in the object program of FIG.
1 is stored in the bit accumulator. Next, when the instruction PADD, which is a pulse-type application instruction, is fetched at the address (1), data at the same address in the data memory 23 is read at the same time. The data memory 23 stores the input X0 of the previous scan. For example, if input X0 is off (= "0") in the initial state, the value of data memory 23 is "0". In the execution cycle of the instruction PADD, the value read from the data memory 23 is compared with the value of the bit accumulator. Here, if the value read from the data memory 23 is “0” and the value of the bit accumulator is “1”, the input X0 has risen, so that the condition is satisfied and the pulse-type application instruction is executed. Then, the next instruction OTY30 is executed. Here, if "1" is written to the address (1) of the data memory 23 when the pulse type application instruction is executed, the rising edge of the input X0 is not detected after the next scan, and only one scan is performed. Can be detected.

In the coprocessor 21, the address is incremented every machine cycle, and when the address is (1), the instruction ST X0
Is decoded, and the instruction PADD is fetched. Further, when the address becomes (2), execution of the instruction ST X0, decoding of the instruction PADD, and fetching of the instruction OT Y30 are performed. Since the pipeline processing is performed in this manner, it is identified that the instruction PADD is a pulse-type application instruction in the machine cycle at the address (2), and the data memory 23 of the data memory 23 is corresponding to the instruction PADD. Although data must be written to address (1), the designated address is already (2), and there is a problem that data cannot be written to address (1). That is, if the pipeline processing is performed with the above-described memory configuration, there is a problem that the pulse-type application instruction cannot be processed.

In order to solve this problem, it is conceivable to separately manage the addresses of the object program memory 22 and the data memory 23. is there. Although it is considered that the execution of the pulse type application instruction is transferred to the main processor 11, the effect of improving the processing speed by the coprocessor 21 is reduced by half.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problem, and to simplify the address management by making the addresses of the object program memory and the data memory common and to perform the pipeline processing without any inconvenience. It is intended to provide a programmable controller.

[0012]

According to the present invention, to achieve the above object, a program memory storing a sequence program, a data memory having 1-bit memory cells each having the same address as the program memory, and
An address generator that specifies the addresses of the program memory and the data memory; an instruction register that fetches the instruction stored at the address specified by the address generator from the program memory; and an instruction that decodes the instruction stored in the instruction register A decoder, an operation unit for executing the decoded instruction, and a controller for performing fetch, decoding, and execution of one instruction in order and performing pipeline control so as to fetch the next instruction from decoding to execution. When the instruction decoded by the instruction decoder is a pulse-type application instruction which is an application instruction including a differentiation process, the controller decrements the designated address by the address generator and sets the next instruction to the instruction register. Fetch It writes data required for the differential processing to the data memory by cross, then, is the resuming fetch the next instruction.

[0013]

According to the above configuration, in a configuration in which an address is shared between a program memory and a data memory, a specified address is decremented when it is identified as a pulse-type application instruction during pipeline processing. At the same time, the fetch of the next instruction is interrupted, the data required for the differential processing is written to the data memory, and then the fetch of the next instruction is restarted. Pipeline processing can be temporarily interrupted to write required data to data memory, etc., while using simple hardware that shares addresses between program memory and data memory, but only inside the coprocessor. Can be processed by
High-speed processing becomes possible.

[0014]

FIG. 1 shows the structure of the main part of a coprocessor 21. Clock generator 31 generates a clock signal so as to synchronize internal circuits. The clock signal includes a normal synchronous clock sclk synchronized with the machine cycle.
A fetch clock fclk for giving a timing for fetching an instruction, a read clock rclk for setting a read timing for the object program memory 22 and the data memory 23, a write clock wclk for setting a write timing for the data memory 23, and a program to be described later. There is a rewrite clock cclk to the counter 41.

The instruction is read into the instruction register 32 in synchronization with the fetch clock fclk. At the same time that the next instruction is read into the instruction register 32, the previous instruction is input to the instruction decoder 33 and decoded. That is, one fetch clock fclk is generated for each machine cycle. When the instruction decoder 33 determines that the instruction is a pulse-type application instruction including a differential instruction or a differential instruction, a pulse corresponding to these instructions is generated.
These pulses are input to a controller 34 that controls the internal operation of the coprocessor 21 and at the same time, are input to a counter 36 through an OR circuit 35 to enable the counter 36 to operate. When the counter 36 is in an operable state,
Since the synchronous clock sclk is counted, as a result, the output value of the counter 36 corresponds to the total number of pulse-type application instructions including differentiation processing and differentiation instructions. The output of the counter 36 is input to the controller 34.

The controller 34 can read the value of the bit memory register 37 which takes in the value of the data memory 23, and sends and receives signals wb and rb to and from a bit accumulator (not shown). Data can be read and data can be written to the bit accumulator. Further, the controller 34 controls the operation of an MPU (ALU for multi-bit data processing) provided inside the coprocessor 21 and controls the clock generator 31 to adjust the output timing of the fetch clock fclk and the write clock wclk. It outputs a fetch enable signal fe and a write enable signal we for controlling. An increase / decrease signal for selecting whether to increment or decrement the output value of the program counter 41 from the controller 34.
inde is also output.

The output value of the program counter 41 is stored in the object program memory 22 and the data memory 23.
The increment terminal 43 for incrementing the output value and the decrementer 44 for decrementing the output value are connected to the output terminal of the program counter 41. The outputs of the incrementer 43 and the decrementer 45 are output from a selector 42 which is a multiplexer.
, And the increase / decrease signal inde is input to the selector 42, thereby selecting whether to increment or decrement the output value of the program counter 41. That is, the designated address can be increased or decreased by increasing or decreasing the output value of the program counter 41.

Hereinafter, the operation will be described by exemplifying a case where the instruction of FIG. 5 is executed. Here, for ease of explanation,
As shown in FIG. 2, numbers 1 to 7 are assigned to each machine cycle in order from the first cycle. The first cycle and the second cycle are the same as the conventional one. In the second cycle, since the address (1) is specified, the instruction PADD which is a pulse-type application instruction is fetched, and the data of the address (1) in the data memory 23 is taken into the bit memory register 37. In the third cycle, the instruction ST X0 is executed, and at the same time, the instruction PADD is executed.
Is decoded. Here, the decoding of the instruction PADD is performed in the first half of the third cycle. Also, the decoding of the instruction PADD enables the counter 36 to operate through the OR circuit 35, and the counter 36 allows the synchronous clock sc
lk is counted. In the controller 34, the instruction decoder 3
3 and the output of the counter 36, FIG.
As shown in (c), the increase / decrease signal falls from the increment to the decrement, and a request is made to decrement the output value of the program counter 41. Also, as shown in FIG. 2E, the fetch enable signal fe falls so as to inhibit the fetch of the instruction. At this time, the instruction ST X
0 is executed, and the input X0 is written to the bit accumulator by the write signal wb as shown in FIG.

In the third cycle, a request by the increase / decrease signal is issued to decrement the output value of the program counter 41. Therefore, in the fourth cycle, the address which is the output value of the program counter is (1) as shown in FIG. ). Here, since the fetch enable signal fe inhibits the fetch, the next instruction OTY30 is not fetched in the fourth cycle, and the instruction PADD is not executed.
Is performed only. At the start of the fourth cycle, the write enable signal we rises and the value stored in the bit accumulator (that is, the value of X0 in the current scan) is written to the data memory 23. In the fourth cycle, since there is no input from the instruction decoder 33 to the controller 34, the increase / decrease signal inde returns to the increment side.

At the fifth cycle, the output value of the program counter 41 is incremented to the address (2).
Is specified, the fetch enable signal fe rises in the second half of the fifth cycle, and the instruction OTY30 is fetched. In the fifth cycle, the instruction PADD is executed, and the value of the bit accumulator is compared with the value stored in the bit memory register 37 in the second cycle, and the value stored in the bit memory register 37 is set to “0”. If the value stored in the bit accumulator is 1, the rising condition is satisfied, so that the bit accumulator is set to "1". However, here, the bit accumulator is already "1". Thereafter, the control returns to the normal pipeline control. In the sixth cycle, writing to the memory is performed if the bit accumulator is “1”, but no operation is performed if the accumulator is “0”.

As described above, since the instruction execution processing is continued in the coprocessor 21 while the disturbance of the pipeline control is minimized, the address of the data memory 23 is shared with the object code memory 22. In combination with this, the hardware can be relatively simple and high-speed processing is possible. In parallel with the above operation, the MPU (processor having an ALU for processing multi-bit instructions in the coprocessor) performs register fetch and operation in the ALU in the third cycle, and stores the value of the bit accumulator in the sixth cycle. Is determined, access to the memory or writing to the register is performed. By performing such parallel processing, the processing of the application instruction portion can be performed in parallel with the processing for the differential instruction, and high-speed processing becomes possible.

In the above example, for simplicity of explanation, the pulse-type applied instruction is only the instruction PADD, but it goes without saying that other instructions follow in the actual program. If such a pulse type application instruction is placed at the head of the program, it is equivalent to executing the application instruction after the differentiation processing.

[0023]

According to the present invention, as described above, in a configuration in which an address is shared between a program memory and a data memory, when a pipeline-type application instruction is identified as a pulse type application instruction, Since the address is decremented, the fetch of the next instruction is interrupted, the data required for the differential processing is written to the data memory, and then the fetch of the next instruction is restarted, so that the pulse-type application instruction which is an application instruction including the differential processing is executed. In this case, the pipeline processing can be temporarily interrupted to write the required data to the data memory, etc., while using simple hardware that shares addresses between the program memory and the data memory. Processing can be performed only inside the processor, and high-speed processing can be performed.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment.

FIG. 2 is an operation explanatory diagram of the embodiment.

FIG. 3 is a block diagram of a programmable controller according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a relationship between a source code and an object code in the programmable controller according to the present invention.

5A is a diagram illustrating a part of an instruction represented by a ladder diagram, and FIG. 5B is an explanatory diagram illustrating a configuration of a memory.

FIG. 6 is an operation explanatory view showing a conventional operation.

[Explanation of symbols]

 31 clock generator 32 instruction register 33 instruction decoder 34 controller 41 program counter 42 selector 43 incrementer 44 decrementer

Claims (1)

(57) [Claims] 1. A program memory storing a sequence program, a data memory having 1-bit memory cells having the same address as the program memory, an address generator designating addresses of the program memory and the data memory, and an address An instruction register for fetching the instruction stored at the address specified by the generator from the program memory, an instruction decoder for decoding the instruction stored in the instruction register, an operation unit for executing the decoded instruction, A controller that sequentially fetches, decodes, and executes instructions and performs a pipeline control so that the next instruction is fetched between decoding and execution. Differential processing When it is a pulse type application instruction which is an application instruction including, the specified address by the address generator is decremented, the fetch of the next instruction to the instruction register is interrupted, and the data required for the differential processing is written to the data memory, and then A programmable controller for resuming the fetch of the next instruction.