JP2504263B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device for exchanging data with an external device by a bus cycle.

[Conventional technology]

The bus cycle is used when data is transferred to and from an external device such as a memory outside the data processing device, and determines the occupied time of the bus connecting the data processing device and the external device. The bus cycle is an integral multiple of the reference clock, and by activating the bus cycle, the bus such as the system bus is time-division controlled to execute memory read / write and I / O port input / output processing. are doing.

In a data processing device that accesses an external device by a bus cycle and transfers data, the external device that requires a recovery time, which is a device setup time required between one access and the next access, is continuously accessed. In this case, a method of setting a dummy time during which nothing is executed by software and satisfying the recovery time is conventionally used.

FIG. 10 is a block diagram showing a configuration of a conventional data processing device using such a method, and FIG. 11 is a diagram showing a bus cycle operated by the data processing device shown in FIG. FIG. 12 is a diagram showing a bus cycle when a dummy time is inserted by software.

In the data processing device 11 shown in FIG. 10, in order to transfer an instruction into the data processing device 11 via the data bus 16, the bus control unit 15 activates a bus cycle and the instruction fetching means 12 fetches the instruction. Put in. The fetched instruction is sent to the instruction decoding unit 13 by a signal from the bus control unit 15 and decoded by the instruction decoding unit 13 to determine how to execute next. When the instruction is judged, the bus control unit
15 sends the judged instruction to the instruction executing means 14, where the bus cycle is activated to execute the instruction, and one instruction is completed.

Next, with reference to FIGS. 10 to 12, a procedure for executing a plurality of instructions for continuously accessing an external device requiring a recovery time will be described.

Instruction A with instruction fetch bus cycle A1 and instruction execution bus cycle A2, and instruction B with instruction fetch bus cycle B1 and instruction execution bus cycle B2
However, if both are instructions for accessing an external device for which the recovery time q is specified, after the execution bus cycle A2 of the instruction A ends, the execution bus cycle B2 of the instruction B is activated again after the recovery time q. By doing so, the external device can be normally accessed.

However, as shown in FIG. 11, when the access instruction A and the instruction B are consecutive to the external device whose recovery time q is longer than the bus cycle, the instruction A execution bus cycle A2
Since the time from the end of the above to the start of the execution bus cycle B2 of the instruction B is only one bus cycle and is shorter than the recovery time q, the recovery time q cannot be satisfied. Therefore, in order to satisfy such a recovery time q, as shown in FIG. 12, an instruction fetch bus cycle D1 by a dummy processing instruction D is inserted by software, and the bus cycle is activated to recover the recovery time. The method of satisfying q is used. Here, the instruction D is an instruction that does not execute anything, and does not activate a bus cycle in the execution stage.

[Problems to be Solved by the Invention]

As described above, when executing a series of instructions for an external device that has a recovery time, a dummy processing instruction must be inserted by software to satisfy the recovery time. However, there was a problem that the size of the program was enlarged.

The present invention has been made to solve the above-mentioned problem, and when an instruction to access an external device having a recovery time is continuous, a non-execution state that does not activate a bus cycle is inserted to recover the recovery time. And continuous access is possible by executing continuous instructions,
It is an object of the present invention to provide a data processing device capable of preventing the program size from increasing and performing all the processing with only necessary execution software.

[Means for solving the problem]

A data processing device according to the present invention includes an instruction analysis instructing means for instructing the presence or absence of output of an insertion signal based on an analysis result of a predetermined logical instruction, and successive busses based on the instruction analysis result by the instruction analysis instructing means. Between the cycles, there is provided bus control means for outputting an insert signal for inserting a state in which the activation of the bus cycle is not executed.

Further, an effective means for activating the insertion signal output from the bus control means based on a predetermined signal is provided.

[Action]

According to the present invention, when an instruction fetched in an arbitrary bus cycle is analyzed as a predetermined instruction having a function of inserting a non-execution state, the instruction analysis instructing means sequentially follows the bus cycle. In the meantime, it has a function of instructing the bus control means that outputs an insertion signal that inserts a state that makes bus cycle activation non-execution, to output the insertion signal, so that the fetched instruction does not insert the non-execution state. If it is an instruction, the output of the insertion signal is limited. As a result, when continuously accessing an external device with a long recovery time, the recovery time can be reduced by using an instruction with a function of inserting a non-execution state as an instruction for accessing the external device. Insert non-execution state by hardware to satisfy.

Further, when the instruction analysis instructing means outputs an insertion signal for inserting a state in which the start of the bus cycle is not executed between the successive bus cycles, the valid means outputs from the bus control means based on a predetermined signal. It is possible to make the inserted signal valid and change the output state of the inserted signal.

[First Embodiment] A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (a) is a block diagram for explaining the configuration of a data processing device showing an embodiment of the present invention, and the same components as those in FIG. 10 are designated by the same reference numerals. The configuration and operation will be described below.

The instruction is fetched by the instruction fetching means 12 via the data bus 16 by the activation of the bus cycle from the bus control unit 15. The fetched instruction is sent to the instruction decoding unit 13 by a signal from the bus control unit 15, and the instruction decoding unit 13
It is decoded by and it is decided how to execute next. When the instruction is determined, the bus control unit 15 sends the determined instruction to the instruction executing means 14, where a bus cycle is activated to execute the instruction and the processing of one instruction is completed.

Further, the non-execution state insertion bus control means 17 which functions as a bus control means outputs a signal indicating a dummy state (time) which is a non-execution state in which a bus cycle is not activated for a certain period of time, and does not insert a dummy state. If the instruction fetched by the instruction fetching means 12 is decoded by the instruction decoding means 13, if the instruction includes a function for inserting a dummy state, the instruction analysis instruction means functions as non-execution. A command is output from the state insertion instruction means 18 to the non-execution state insertion bus control means 17,
A dummy state is inserted between bus cycles.

FIG. 1 (b) is a block diagram for explaining the data processing operation of the data processing device 11 shown in FIG. 1 (a) and the peripheral device. Refer to the timing chart shown in FIG. 1 (c). The operation of each part will be described below.

In the figure, reference numeral 21 denotes an instruction unit, which holds various instructions executed by the data processing device 11. 22-1 to 22-N are external devices,
Data is input to the data processing device 11 via the data bus 16 and processed data is taken in via the data bus 16. The instruction fetching means 12, the instruction decoding means 13, and the instruction executing means 14 propagate the instruction to each under the control of the bus control section 15 in synchronization with the synchronous clock CLK.

The data processing device 11 executes the command of the command unit 21 by sequentially repeating the command fetch, command decoding, and command execution in synchronization with the synchronous clock CLK. In the case of an instruction that does not insert a, the next instruction fetch process is started immediately after the instruction execution process, but as shown in the data processing mode II,
If the instruction decode result indicates that the instruction is a dummy state insertion instruction, a dummy state satisfying the recovery time is inserted, and after the recovery time has elapsed, the next instruction fetch process is started.

Next, the bus cycle processing in the data processing device shown in FIG. 1A will be described in detail with reference to FIG.

FIG. 2 is a diagram showing a bus cycle in the data processing device shown in FIG.

If there is an instruction to access an external device outside the data processing device 11, the instruction to be executed first is the data bus.
It is taken into the instruction taking means 12 via 16. Next, the instruction decoding unit 13 determines how to execute the instruction, and the instruction executing unit 14 executes the instruction in the next bus cycle, thereby completing the processing of one instruction. The instruction fetching means 12, the instruction decoding means 13, and the instruction executing means 14 all propagate an instruction under the control of the bus control unit 15 and perform operation processing. Further, when there is an instruction to access the external device, the access to the external device is performed in the instruction execution stage. That is, the external device is accessed by the execution of the execution bus cycle by the bus control unit 15.

As in the bus cycle described above, the instruction acquisition bus cycle is A1 and the instruction execution bus cycle is A2.
And an instruction B whose instruction fetch bus cycle is B1 and whose instruction execution bus cycle is B2 are both instructions that access an external device whose recovery time q1 is specified. Assume

The instruction A fetched in the instruction fetch bus cycle A1
By executing the instruction execution bus cycle A2 as an instruction having a function such that the non-execution state r is inserted after the instruction execution bus cycle A2 is executed, the first access to the external device is the bus cycle
After the dummy state is inserted in A2, the next execution bus cycle B2 is started after the recovery time q1 of the external device and the external device can be normally accessed.

If there is an instruction to access the same external device again after the end of bus cycle B2 and it is necessary to insert a non-execution state, an instruction having a function of inserting a dummy state as instruction B Is used, and if there is no need, an instruction that does not insert a dummy state may be used.

FIG. 3A is a bus cycle diagram when an external device is accessed multiple times by one instruction.

As can be seen from this figure, the instruction C is a case where the instruction fetch bus cycle is C1, the instruction execution bus cycle is C2, C3, and there are two instruction execution bus cycles C2, C3 for the external device. , An instruction having a function such that the non-execution state r is inserted into the instruction C fetched in the instruction fetch bus cycle C1 after the instruction execution bus cycle C2 and the instruction execution bus cycle C3 are executed (see FIG. 3 (b)). ), The recovery time q2 is satisfied and the external device can be normally accessed.

FIG. 3 (b) is a diagram showing an example of an instruction that can be executed by the data processing device shown in FIG. 1 (a), and shows an instruction without dummy state insertion, and is composed of an instruction part and an operand part. , For example, corresponds to an instruction to transfer a value “0” to the external device ope. Indicates an instruction with a dummy state inserted, and this instruction with a dummy state insertion inevitably adds one instruction when the same process is described by a NOP instruction as shown in FIG. 3 (c). Not only that, considering the number of bits required for all instruction analysis with NOP instructions, a considerable number of bits is required as the number of NOP instructions increases. In the case of the present invention, the number of bits in the operand part is 1 bit. The same command processing can be executed simply by adding them. Therefore, the number of NOP instruction descriptions associated with the dummy state is significantly reduced, and the program size can be prevented from increasing.

[Second Embodiment] FIG. 4 is a block diagram for explaining the configuration of a data processing device showing a second embodiment of the present invention. The same parts as those in FIG. is there. The configuration and operation will be described below.

The instruction is fetched by the instruction fetching means 12 via the data bus 16 by the activation of the bus cycle from the bus control unit 15. The fetched instruction is sent to the instruction decoding unit 13 by a signal from the bus control unit 15, and the instruction decoding unit 13
It is decoded by and it is decided how to execute next. When the instruction is determined, the bus control unit 15 sends the determined instruction to the instruction executing means 14, where a bus cycle is activated to execute the instruction and the processing of one instruction is completed.

Further, the non-execution state insertion bus control means 17 which functions as a bus control means outputs a signal indicating a dummy state (time) which is a non-execution state in which a bus cycle is not activated, and whether a dummy state is inserted or not. Means that the instruction fetched by the instruction fetch means 12 is an instruction decode means.
If the instruction has a function of inserting some dummy states at the time of being decoded in 13, the non-execution state insertion bus control means 18 to the non-execution state insertion bus control means functioning as the instruction analysis instruction means. A command is output to 17 and the number of dummy states is inserted during the bus cycle.

Next, the bus cycle processing in the data processing device shown in FIG. 4 will be described in detail with reference to FIG.

FIG. 5 is a diagram showing a bus cycle in the data processing device shown in FIG.

If there is an instruction to access an external device outside the data processing device 11, the instruction to be executed first is the data bus.
It is taken into the instruction taking means 12 via 16. Next, the instruction decoding unit 13 determines how to execute the instruction, and the instruction executing unit 14 executes the instruction in the next bus cycle, thereby completing the processing of one instruction. The instruction fetching means 12, the instruction decoding means 13, and the instruction executing means 14 all propagate an instruction under the control of the bus control unit 15 and perform operation processing. Further, when there is an instruction to access the external device, the access to the external device is performed in the instruction execution stage. That is, the external device is accessed by the execution of the execution bus cycle by the bus control unit 15.

As in the bus cycle described above, the instruction acquisition bus cycle is A1 and the instruction execution bus cycle is A2.
And an instruction B whose instruction fetch bus cycle is B1 and whose instruction execution bus cycle is B2 are both instructions that access an external device whose recovery time q1 is specified. Assume

The instruction A fetched in the instruction fetch bus cycle A1
By executing an instruction execution bus cycle A2, by preparing an instruction with the function to insert the specified number of non-execution states, the external device (external device) can be accessed first in bus cycle A2. After the specified number of dummy states are inserted, the next execution bus cycle B2 is started after the recovery time q1 of the external device, and the external device can be normally accessed. If there is an instruction to access the same external device again after the end of bus cycle B2 and it is necessary to insert a non-execution state, an instruction having a function of inserting a dummy state as instruction B May be used, and if there is no need, an instruction that does not insert a dummy state may be used.

FIG. 6A is a bus cycle diagram when an external device is accessed multiple times by one instruction.

As can be seen from this figure, the instruction C is a case where the instruction fetch bus cycle is C1, the instruction execution bus cycle is C2, C3, and there are two instruction execution bus cycles C2, C3 for the external device. , The instruction C fetched in the instruction fetch bus cycle C1 is prepared as an instruction having a function of inserting a designated number of non-execution states after the execution of the instruction execution bus cycle C2 and the instruction execution bus cycle C3. As a result, the recovery time q2 is satisfied and the external device can be normally accessed.

FIG. 6B is a diagram showing an example of an instruction that can be executed by the data processing device shown in FIG. 1A, shows an instruction without dummy state insertion, and is composed of an instruction part and an operand part. For example, it corresponds to an instruction to transfer the value “0” to the external device ope. Indicates an instruction with dummy state insertion, and with this instruction with dummy state insertion,
As shown in FIG. 6 (c), when the same processing is described by NOP instructions, not only several instructions are necessarily added, but also
Considering the number of bits required for all instruction analysis in accordance with NOP instructions, a considerable number of bits is required as the number of NOP instructions increases. The same instruction processing can be executed.
Therefore, the number of NOP instruction descriptions associated with the dummy state is significantly reduced, and the program size can be prevented from increasing.

[Third Embodiment] FIG. 7 (a) is a block diagram for explaining the configuration of a data processing device showing a third embodiment of the present invention. The same components as those in FIG. 1 (a) are designated by the same reference numerals. It is attached. Less than,
The configuration and operation will be described. The instruction is fetched by the instruction fetching means 12 via the data bus 16 by the activation of the bus cycle from the bus control unit 15. The fetched instruction is sent to the instruction decoding unit 13 by a signal from the bus control unit 15 and is decoded by the instruction decoding unit 13 to determine how to execute next. When the instruction is judged, the bus controller 15 executes the judged instruction to the instruction executing means 14
, The bus cycle is activated to execute the instruction, and the processing of one instruction is completed.

Further, the non-execution state insertion bus control means 17 which functions as a bus control means outputs a signal indicating a dummy state (time) which is a non-execution state in which a bus cycle is not activated for a certain period of time, and does not insert a dummy state. If the instruction fetched by the instruction fetching means 12 is decoded by the instruction decoding means 13, if the instruction includes a function for inserting a dummy state, the instruction analysis instruction means functions as non-execution. A command is output from the state insertion instruction means 18 to the non-execution state insertion bus control means 17,
A dummy state is inserted between bus cycles.

Further, the output signal from the non-execution state insertion bus control means 17 is given to the bus control section 15 via the non-execution state avoidance means 19 which functions as a valid means, and the input signal is valid in the bus control section 15. Only in the case of the state, control is performed so that the non-execution state is inserted into the bus cycle. That is, when the valid signal DV is in the inactive state, the bus control unit is included even if the instruction includes the function of inserting the non-execution state.
A signal is input to 15 in the invalid state, and the non-execution state is not inserted between bus cycles. When the valid signal DV is changed from the active state to the inactive state during the non-execution state, the current non-execution state is canceled midway and the next bus cycle is activated.

FIG. 7 (b) is a block diagram for explaining the data processing operation of the data processing device 11 and the peripheral device shown in FIG. 7 (a), and refer to the timing chart shown in FIG. 7 (c). The operation of each part will be described below.

In the figure, reference numeral 21 denotes an instruction unit, which holds various instructions executed by the data processing device 11. 22-1 to 22-N are external devices,
Data is input to the data processing device 11 via the data bus 16 and processed data is taken in via the data bus 16. The instruction fetching means 12, the instruction decode 13,
The instruction execution means 14 propagates instructions to each under the control of the bus controller 15 in synchronization with the clock CLK.

The data processing device 11 executes the command of the command section 21 by sequentially repeating the command fetch, command decoding, and command execution in synchronization with the synchronous clock CLK. The data processing mode shown in FIG. As shown in I, in the case of an instruction in which no dummy state is inserted, after the instruction execution processing,
Immediately, the next instruction fetch process is started. However, as shown in data processing mode II, if the instruction decode result indicates that the instruction is a dummy state insertion instruction, a dummy state satisfying the recovery time is inserted and the recovery time After the lapse of time, the next instruction fetch process is started.

Further, as shown in the data processing mode III, when the dummy state is inserted and the valid signal DV becomes inactive to shorten the dummy state, the next instruction fetch processing can be started. As a result, even if the recovery time of a specific external device is shorter than that of another external device,
The next instruction fetch process becomes possible with the recovery time effective for the external device. Therefore, it becomes possible to terminate the unnecessary dead time at a predetermined timing.

Next, the bus cycle processing in the data processing device shown in FIG. 7A will be described in detail with reference to FIG.

FIG. 8 is a diagram showing a bus cycle in the data processing device shown in FIG.

If there is an instruction to access an external device outside the data processing device 11, the instruction to be executed first is the data bus.
It is taken into the instruction taking means 12 via 16. Next, the instruction decoding unit 13 determines how to execute the instruction, and the instruction executing unit 14 executes the instruction in the next bus cycle, thereby completing the processing of one instruction. The instruction fetching means 12, the instruction decoding means 13, and the instruction executing means 14 all propagate an instruction under the control of the bus control unit 15 and perform operation processing. Further, when there is an instruction to access the external device, the access to the external device is performed in the instruction execution stage. That is, the external device is accessed by the execution of the execution bus cycle by the bus control unit 15.

As in the bus cycle described above, the instruction acquisition bus cycle is A1 and the instruction execution bus cycle is A2.
And an instruction B whose instruction fetch bus cycle is B1 and whose instruction execution bus cycle is B2 are both instructions that access an external device whose recovery time q1 is specified. Assume

The instruction A fetched in the instruction fetch bus cycle A1
By executing an instruction execution bus cycle A2, a non-execution state is inserted as an instruction with a function so that an external device can be accessed first.
After the dummy state is inserted, the next execution bus cycle B2 is started after the recovery time q1 of the external device.
External devices can be accessed normally.

If there is an instruction to access the same external device again after the end of bus cycle B2 and it is necessary to insert a non-execution state, an instruction having a function of inserting a dummy state as instruction B Is used, and if there is no need, an instruction that does not insert a dummy state may be used. In FIG. 8, the length of the non-execution state is r1, or the valid signal DV changes to the non-execution state during the non-execution state.

FIG. 9A is a bus cycle diagram when an external device is accessed multiple times by one instruction.

As can be seen from this figure, the instruction C is a case where the instruction fetch bus cycle is C1, the instruction execution bus cycle is C2, C3, and there are two instruction execution bus cycles C2, C3 for the external device. , By recovering the instruction C fetched in the instruction fetch bus cycle C1 as an instruction having a function of inserting a non-execution state after the execution of the instruction execution bus cycle C2 and the instruction execution bus cycle C3 The external device can be normally accessed by satisfying the time q2.

8 and 9 (a), if the relationship between r1 and r2 indicating the length of the non-execution state is r1> r2 and the non-execution state is constant regardless of the instruction, In FIG. 6A, it is considered that the valid signal DV is changed to the inactive state during the non-execution state.

FIG. 9 (b) is a diagram showing an example of instructions that can be executed by the data processing device shown in FIG. 9 (a), and shows an instruction without dummy state insertion, and is composed of an instruction part and an operand part. , For example, corresponds to an instruction to transfer a value “0” to the external device ope. Indicates an instruction with a dummy state inserted, and by the instruction with a dummy state inserted, one instruction is inevitably added when the same process is described by a NOP instruction as shown in FIG. 9 (c). Not only that, considering the number of bits required for all instruction analysis with NOP instructions, a considerable number of bits is required as the number of NOP instructions increases, but in the case of the present invention, the number of bits of the operand is 1 bit added. The same command processing can be executed simply by Therefore, the number of NOP instruction descriptions associated with the dummy state is significantly reduced, and the program size can be prevented from increasing.

〔The invention's effect〕

As described above, according to the present invention, the instruction analysis instructing means for instructing the presence / absence of the output of the insertion signal based on the analysis result of the predetermined logic instruction, and the bus which is succeeding the bus based on the instruction analysis result by the instruction analysis instructing means Between the cycles, the bus control means for outputting the insertion signal for inserting the state in which the start of the bus cycle is not executed is provided, so that it is not necessary to add an extra instruction to the program as in the conventional case, that is, to the software. Regardless of this, external devices can be continuously accessed while executing a bus cycle that satisfies the recovery time.

Further, since the effective means for activating the insertion signal output from the bus control means based on the predetermined signal is provided,
Since the active time of the insertion signal output from the bus control means as a signal for a fixed period can be freely shortened, an external device having a short recovery time can be efficiently and continuously accessed.

There is no need to add extra instructions to the program to satisfy the recovery time as in the past, it is possible to prevent the program size from growing and it is possible to do all the processing with only the required execution software. Produce an effect.

[Brief description of drawings]

FIG. 1 (a) is a block diagram for explaining the configuration of a data processing device showing an embodiment of the present invention, and FIG. 1 (b) is a first block diagram.
FIG. 1C is a block diagram illustrating the data processing operation of the data processing device and the peripheral device shown in FIG.
FIG. 2B is a timing chart explaining the operation of FIG. 2B, FIG. 2 is a diagram showing a bus cycle in the data processing device shown in FIG. 1A, and FIG. 3A is one instruction multiple times. A bus cycle diagram for accessing an external device, FIGS. 3 (b) and 3 (c) are diagrams showing examples of instructions that can be executed by the data processing device shown in FIG. 3 (a), and FIG. FIG. 5 is a block diagram illustrating a configuration of a data processing device showing a second embodiment of the invention, FIG. 5 is a diagram showing a bus cycle in the data processing device shown in FIG. 4, and FIG. 6 (a) is one instruction. Bus cycle diagram of a bus cycle for accessing an external device a plurality of times in FIG. 6, FIGS.
Showing an example of instructions executable by the data processing device shown in FIG.
FIG. 7 is a block diagram for explaining the configuration of a data processing device showing a third embodiment of the present invention, and FIG. 8 is a diagram showing a bus cycle in the data processing device shown in FIG. 1 (a).
FIG. 9A is a bus cycle diagram when an external device is accessed multiple times by one instruction, and FIGS. 9B and 9C.
Is a diagram showing an example of instructions that can be executed by the data processing device shown in FIG. 9 (a). FIG. 10 is a block diagram showing a configuration of a conventional data processing device using such a method. FIG. 10 is a diagram showing a bus cycle operated by the data processing device shown in FIG. 10, and FIG. 12 is a diagram showing a bus cycle when a dummy time is inserted by software. In the figure, 11 is a data processing device, 12 is an instruction fetching means, 13 is an instruction decoding means, 14 is an instruction executing means, 15 is a bus control section, 16 is a data bus, 17 is a non-execution state insertion bus control means, and 18 is The non-execution state insertion instructing means and 19 are non-execution state avoidance means. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A data processing device for delivering data to an external device in a bus cycle, and an instruction analysis instruction means for instructing the presence or absence of output of an insertion signal based on the analysis result of a predetermined logical instruction, and this instruction analysis. Bus control means for outputting an insertion signal for inserting a state in which the activation of the bus cycle is not executed between successive bus cycles based on the instruction analysis result by the instruction means. Processing equipment. 2. A data processing apparatus according to claim 1, further comprising a validating means for validating the insertion signal output from said bus control means based on a predetermined signal.