JP3531856B2 - Program control method and program control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor (MPU), DSP (Digital Signal).
The present invention relates to a program control method for controlling parallel execution of instructions in a processor such as a processor) and a program control device used for the execution.

[0002]

2. Description of the Related Art In recent years, program control devices have been developed for the purpose of executing programs at high speed or reducing the number of instructions.

As a conventional example of this type of program control device, there is a program control device described in Japanese Patent Publication No. 62-42301 which repeatedly executes instructions. Figure 8
Shows the system configuration of this program control device.

As shown in FIG. 8, this program control device has a memory (program memory) 1 in which instructions are stored.
02, a program counter 101 for giving an address signal to the memory 102, an instruction register 103 for temporarily holding the output of the memory 102, a control unit 104 for decoding the output of the instruction register 103 and outputting various control signals,
A repeat counter 105 that counts the number of times the program is repeatedly executed is configured.

Next, the operation of the conventional program control device having the above configuration will be described.

First, the repeat counter set instruction is stored in the address n of the memory 102, the instruction A is stored in the address n + 1, and the instruction B is stored in the address n + 2. In this state, the count number (count value) of the program counter 101 is n.
Then, the repeat counter set instruction stored in the address n of the memory 102 is read by the control unit 104 and stored in the instruction register 103 as an instruction code.

At the same time, the repeat count included in this instruction code receives the output of the repeat counter 105, and the instruction code stored in the instruction register 103 is repeatedly controlled until the count number of the repeat counter 105 becomes zero.

When the count number of the program counter 101 becomes n + 1 and the instruction A stored in the address n + 1 of the memory 102 is read by the control unit 104 and stored in the instruction register 103, the instruction A is executed. Will be.

Thus, the program control device
Since the next instruction is executed after waiting for the completion of the repetitive operation, there are the following problems.

That is, MPU, DS for high-speed calculation
In a control device such as P, it is necessary to execute another process in parallel with the repetitive operation. However, in the above-mentioned program control device, other process is operated in parallel while the repetitive operation is being performed. I can't. Therefore, if the above-mentioned program control device is installed in a control device such as an MPU or a DSP, the advantages of these control devices for high-speed calculation will be impaired.

As another conventional example of a program control device for solving such a problem, Japanese Patent Laid-Open No. 5-1586
There is one described in Japanese Patent Publication No. 87. This program control device achieves high-speed operation by executing another instruction in parallel with the repetitive execution processing of a certain instruction.

FIG. 9 shows the system configuration of the program control device described in Japanese Patent Laid-Open No. 158687/1993. This program control device has a memory 20 in which instructions are stored.
1 and the address signal is given to the memory 201, and the clock φ
The program counter 202 whose contents are incremented at the rising edge of 1 and the output of the memory 201 are clock φ
An instruction register 203 fetched at the rising edge of 1 and a decoder 204 for decoding the output of the instruction register 203
And an arithmetic unit A205 for performing an arithmetic operation, and a decoder register A206 for fetching data at the rising edge of the clock φ1.
And an arithmetic unit B207 for performing an arithmetic operation and a decoder register B208 for fetching data at the rising edge of the clock φ1.
A repeat control unit 209, a repeat counter 210 that uses the output of the latch 211 as an initial value, and counts down at the rising edge of the clock φ1, and a repeat counter 2
A latch 211 that holds the initial value of 10 and a sequence controller 212 that outputs an update prohibition signal are provided.

In this program control device, a repeat control unit 209, to which a repeat set instruction for instructing repeated execution is set, presets the repeat counter 210, and repeat processing stored in the memory 201 at the next address of the repeat set instruction. The instruction that is the target of is repeatedly executed.

Then, each time the instruction is repeatedly executed,
The countdown of the repeat counter 210 is performed. Subsequently, when a wait instruction for storing instruction execution synchronization is stored after the address in which the instruction to be repeatedly processed is stored in the memory 201, the repeat control unit 209 ends the repeated execution of the instruction to be repeatedly processed. It is determined whether or not. If it is confirmed that the repeated execution of the instruction has not ended, the determination operation is continued. As a result, the instruction to be repeatedly processed and the following instructions up to the wait instruction can be executed in parallel.

As described above, in the program controller disclosed in Japanese Patent Laid-Open No. 158687/1993, the repeat control instruction at the address n causes the instruction at the address n + 1, that is, n + 1.
Only the instruction to repeat one instruction stored in the address a specified number of times can be executed in parallel.

[0016]

By the way, the block execution instruction control for repeatedly executing a block instruction consisting of a plurality of instructions is often required for the repeated execution, and it is required to develop a program control device which meets this requirement. ing.

However, in the program control device disclosed in Japanese Patent Laid-Open No. 5-158687, as described above,
Only instructions that repeat one instruction a specified number of times can be executed in parallel, and parallel processing with operations involving block repeat instruction control cannot be performed. Under these circumstances, there is a great demand for the development of a program control method and a program control device capable of performing parallel processing with operations involving block repeat instruction control.

The present invention has been made in view of the above circumstances, and realizes a program control device capable of executing a block repeat instruction and a group of instructions following the block repeat instruction in parallel and capable of high-speed operation. It is an object of the present invention to provide a program control method and a program control device capable of performing the above.

Another object of the present invention is to provide a program control method and a program control device which can simplify an instruction for a block repeat instruction and reduce the number of instructions.

[0020]

A program control method according to the present invention is a program control method for a program control device having a first arithmetic unit and a second arithmetic unit, and is stored in an n-th address of an instruction memory. Based on the first instruction, from the address n + 1 to n + x (x is a positive integer of 1 or more)
A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored in the address, and addresses n + x + 1 and subsequent addresses of the instruction memory in parallel with the repeated execution of the second instruction. And instructing the second arithmetic unit to sequentially execute the instructions stored in, which achieves the above objectives.

Further, the program control method of the present invention is a program control method for a program control device having a first arithmetic unit and a second arithmetic unit, wherein the first program stored at address n of the instruction memory. Based on the command, n +
A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored at addresses 1 to n + x (x is a positive integer of 1 or more), and repeatedly executing the second instruction A third instruction that is executed in parallel with the second instruction and is stored in the instruction memory at addresses n + x + 1 and subsequent addresses, and is stored in the address n + x + y (y is a positive integer of 1 or more). repeating the steps of instructing execution instruction to the first computing unit said, the instructions from the n + x + y + 1 address of the memory n + x + y + m ( m is a positive integer of 1 or more) of the m stored in the address 4 which performs repetitive execution of When there is an instruction, the fourth instruction is stored in the repetitive control memory, and immediately after the repetitive execution by the second instruction is completed, the instruction for repetitive execution of the fourth instruction is given to the first arithmetic unit. And-up, which includes the step of sequentially executing instructions stored in parallel with the instruction of said second instruction and said 4 to the address of n + x + y + m + 1 address and later,
Thereby, the above object is achieved.

Further, the program control method of the present invention is a program control method of a program control device comprising a first arithmetic unit and a second arithmetic unit, wherein the first program stored in the n-th address of the instruction memory. Based on the command, n +
A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored at addresses 1 to n + x (x is a positive integer of 1 or more), and repeatedly executing the second instruction A third instruction that is executed in parallel with the second instruction and is stored in the instruction memory at addresses n + x + 1 and subsequent addresses, and is stored in the address n + x + y (y is a positive integer of 1 or more). If there is a step of instructing the second execution unit of the repeated execution instruction, and a fourth instruction for executing the repeated execution of m pieces stored in addresses n + x + y + 1 to n + x + y + m of the instruction memory, the second instruction by the second operator for not processing repeatedly executed, the fourth and the step of executing the repetitive processing of the instruction, the second instruction or the fourth instruction repetition process quickly end by Using the said arithmetic unit, n + x + y
The step of sequentially executing the instructions stored in the addresses after + m + 1 is achieved, whereby the above object is achieved.

Further, the program control device of the present invention is a program control device for executing the program control method according to claim 1, wherein a first instruction for instructing repetitive execution and the next and subsequent addresses of the first instruction are given. An instruction memory storing a plurality of instructions including x second instructions stored therein, a decoder that decodes the first instruction and the second instruction, and outputs various control signals; A counter for decrementing the value of the number of repeat instructions or the number of block repeats by one each time the repeat instruction is executed, and a repeat control memory for storing x repeat instructions for performing block repeat,
When the first instruction is decoded, the block repeat count and the set of repeat instruction counts are executed, while each time the second instruction is executed, the block repeat count and repeat count are sent to the counter. A repeat control device is provided for instructing a count value indicating the number of instructions, and for instructing the first arithmetic unit to end the instruction when the repetitive operation is completed, thereby achieving the above object. .

A program control device of the present invention is a program control device for executing the program control method according to claim 2, wherein the first command for instructing repeated execution and the first command in the instruction memory are executed. A plurality of instructions including a second instruction stored x times after the next address, a third instruction instructing repeated execution, and m fourth instructions for executing repetitive processing subsequent to the third instruction are stored. Instruction memory, a decoder for decoding these instructions and outputting various control signals, and a value of the repeat instruction number or block repeat number set by the first instruction and set to 1 each time the repeat instruction is executed. A counter that decrements by one, and an iterative control that stores the x second instructions and the m fourth instructions that perform the block iteration Mori and, when the instruction of the first is decoded, the block number of repetitions and the number of the repeat instruction is set in the counter,該該repetition block to said counter each time the instruction of the second is executed Number and a count value indicating the number of the repeated instructions, instructing the first arithmetic unit that the repeated operation is completed, and decoding the third instruction, the fourth operation is executed. And a repeat controller for instructing the first arithmetic unit to subsequently execute the fourth command when the second command is completed, Thereby, the above object is achieved.

Further, the program control device of the present invention is a program control device for executing the program control method according to claim 3, wherein the first command for instructing repetitive execution and the first command in the instruction memory are executed. A plurality of instructions including a second instruction stored x times after the next address, a third instruction instructing repeated execution, and m fourth instructions for executing repetitive processing subsequent to the third instruction are stored. Instruction memory, a decoder for decoding these instructions and outputting various control signals, and a value of the repeat instruction number or block repeat number set by the first instruction and set to 1 each time the repeat instruction is executed. The first counter, which decrements by one, and the third instruction,
Is set and repeated every time a repeat instruction is executed
Decrement the value of the number of instructions or block repetitions one by one
A second counter for placement, and repeated control memory for storing the x-number of the second instruction and m the fourth instruction for performing block repetition, the first instruction is decoded, the first The number of block repetitions and the number of repetition instructions are set to the counter of 1 , and the count value indicating the number of block repetitions and the number of repetition instructions is instructed every time the second instruction is executed, and the repetition calculation is performed. When the third instruction is decoded, the third instruction is decoded and the fourth instruction is issued to the second operator by the third instruction. instruction instructs to perform, with respect to the second counter, and sets the block number of repetitions and the number of the repeat instruction in the instruction of the fourth, repeating the block each time the instruction of the fourth is performed Number and repetition The count value indicating the number of instructions is instructed, and the arithmetic unit in which the second instruction and the fourth instruction have finished first sequentially execute the instructions stored in the addresses after the fourth instruction. And a repetitive control device, whereby the above object is achieved.

The operation of the present invention will be described below.

According to the configuration in which the second arithmetic unit is instructed to sequentially execute the instructions stored at addresses n + x + 1 and later of the instruction memory in parallel with the repeated execution of the second instruction, the block repetition is performed. Since the instruction and the instruction group following the block repeat instruction can be executed in parallel, a high-speed operation is possible as compared with the conventional program control device described above. Further, since one of the instructions executed in parallel is the block repeat instruction, the instructions can be simplified and the number of instructions can be reduced.

During execution of the block repeat instruction,
If a block repeat instruction is included in the instructions that are executed in parallel with that instruction, the block repeat instruction is stored in the repeat control memory, so that another block repeat execution is executed after the end of the block repeat execution being executed. In addition, since a group of instructions following the repeat instruction can be executed in parallel with these block repeat instructions, a high-speed operation can be performed as compared with the conventional program control device. In addition, with this configuration, the instructions can be further simplified and the number of instructions can be further reduced.

During execution of the block repeat instruction,
When a block repeat instruction is included in the instructions that are being processed in parallel with the instruction, the block repeat instruction is repeatedly executed by an arithmetic unit that is not performing the block repeat processing. It is possible to realize a program control device that can be realized.
Further, in this configuration as well, it is possible to execute a block repeat instruction and a block repeat instruction in an instruction that is processing in parallel with the instruction, and a subsequent instruction group in parallel, so that the program control device is further improved. High-speed calculation can be achieved.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 3 show Embodiment 1 of the program control apparatus of the present invention. First, the system configuration of the program control device will be described with reference to FIG.

This program control device decodes an instruction memory 1 in which an instruction for giving an instruction to each device described below is stored and an output from the instruction memory 1 and outputs an instruction to give an instruction to each device. The instruction decoder 2 and the data memory 3 for giving data to the arithmetic unit (arithmetic unit) A6 and the arithmetic unit B4 for performing arithmetic operations.

The calculator B4 receives data from the data memory 3, performs various calculations based on this data, and outputs the calculation result to the register B5. On the other hand, the arithmetic unit A6 receives data from the data memory 3 and the register A7,
Various calculations are performed based on this data, and a repeat calculation (block repeat calculation) for outputting the calculation result to the register A7 is performed.

In addition, the program controller is equipped with a repeat controller 8 for performing block repeat control, a block repeat counter 9 and a repeat control memory 10.

The repeat controller 8 indicates the number of block repeats and the number of repeat commands based on the block repeat command output from the instruction decoder 2. More specifically, the repeat instruction is stored in the repeat control memory 10 and the reading from the repeat control memory 3 is instructed. When the calculation is completed, the calculator A6 is instructed that the calculation is completed.

The block repeat counter 9 sets the number of block repeats and the number of repeat instructions according to an instruction from the repeat controller 8 and outputs one count value of the number of block repeats or the number of repeat instructions each time a repeat operation is performed. Clement.

Next, the state transition of the repetitive control device 8 will be described with reference to FIG. As shown in the figure, the iterative control device 8 sets a standby state (wait state) 41 in which no block iterative processing is being performed and a block iterative counter 9 for the number of block iteratives and the number of repetitive instructions, and sets them in the arithmetic unit A6. Instructed to repeatedly execute the calculation, and at the same time, the repeated control memory 10
Repetitive set state 42 in which a repetitive operation command is written to
And a repeat state 43 in which a repeat operation command is read from the repeat control memory 10 and a repeat operation is performed.
It has two states and transitions between these states.

Next, the operation of the program control device according to the first embodiment will be described with reference to FIG. This operation is shown in FIG.
The cycle 1 to the cycle 13 shown in FIG. The operation during each cycle will be described below.

<Cycle 1> First, in cycle 1, the instruction (instruction n-1) stored in the address n-1 of the instruction memory 1 is sent from the instruction memory 1 to the instruction decoder 2. Similarly, in the subsequent cycles, the instruction at each address is sent from the instruction memory 1 to the instruction decoder 2.

<Cycle 2> In cycle 2, the arithmetic unit B
4, the instruction n-1 by the instruction stored in the address n-1 of the instruction memory 1 is processed. At this time, the repetitive control device 8 is in the standby state 4
A transition from 1 to the repeated set state 42 is made.

<Cycle 3> In cycle 3, the repeat controller 8 sets the number of repeat instructions and the number of block repeats of the block repeat counter 9 based on the block repeat instruction n stored in the address n of the instruction memory 1. Here, the number of repeat instructions = 2 (three instructions) and the number of block repeats = 2 (three loops) are set in the repeat counter 9.

Then, the iterative control device 8 sets the iterative operation end flag to "0".

<Cycles 4,5> In cycles 4,5,
The repetitive instructions n + 1 and n + 2 (first block repetition) are sequentially executed by the arithmetic unit A6, and the repetitive instructions n + 1 and n + 2 are sequentially written to the repetitive control memory 10.

Then, the block repeat counter 9 decrements the number of repeat instructions by one.

<Cycle 6> In cycle 6, the arithmetic unit A
6, the repeat instruction n + 3 (block repeat 1
The second time) is executed, and the repeat instruction n + 3 is written in the repeat control memory 10.

Here, the number of repeated instructions is 0,
Since the block repeat count is 2, the block repeat count is decremented by 1 and the repeat instruction count is set to 2. At this time, the repeat control device 8 shifts from the repeat set state 42 to the repeat state 43.

<Cycles 7 and 8> In cycles 7 and 8,
The repetitive instructions n + 1 and n + 2 (second block repetition) are sequentially called from the repetitive control memory 10 and executed by the arithmetic unit A6. Further, the arithmetic unit B4 sequentially executes the instructions n + 4 and n + 5. Then, in accordance with an instruction from the repeat controller 8, the number of repeat instructions in the block repeat counter 9 is decremented by one.

<Cycle 9> In cycle 9, the arithmetic unit A
6, the repeat instruction n + 3 (second block repeat) is called from the repeat control memory 10 and executed. Further, the instruction n + 6 is executed by the arithmetic unit B4.

Here, the number of repeated instructions is 0,
Since the block repeat count is 1, the block repeat count of the block repeat counter 9 is decremented by 1 and the repeat instruction count is set to 2.

<Cycle 10, 11> Cycle 10, 1
1, the repetitive control memory 10 is operated by the arithmetic unit A6.
To repeat instructions n + 1, n + 2 (block repeat 3
The second time) is sequentially called and executed. Also, the computing unit B
4, instructions n + 7 and n + 8 are sequentially executed. Then, in accordance with an instruction from the repeat controller 8, the number of repeat instructions in the block repeat counter 9 is decremented by one.

<Cycle 12> In cycle 12, the arithmetic unit A6 calls the repetitive instruction n + 3 (third block repetition) from the repetitive control memory 10 and executes it. Further, the instruction B + 4 executes the instruction n + 9.

Here, since the number of repeat instructions is 0 and the number of block repeats is 0, the block repeat counter 9 is stopped and the repeat controller 8 sets the repeat end flag to "1".

At this time, the repeat control device 8 shifts from the repeat state 43 to the standby state 41.

<Cycle 13> In cycle 13, the arithmetic unit B4 processes the instruction n + 10.

As described above, according to the program control device of the first embodiment, the execution of the repetitive instruction by the arithmetic unit A6 and the execution of a plurality of instructions by the arithmetic unit B4 following the repetitive instruction are performed in parallel. You can That is, since the block repeat instruction and the instruction group following the block repeat instruction can be executed in parallel, one of the instructions executed in parallel in the program capable of high-speed operation is the block repeat instruction, so the instruction can be simplified. The number of instructions can be reduced.

(Second Embodiment) FIGS. 4 and 5 show a second embodiment of the program control apparatus of the present invention. The system configuration of the program control device according to the second embodiment is the same as that in FIG. 1, and therefore the same reference numerals are used in the following description.

FIG. 4 shows the internal state of the repetitive control device 8, that is, the state transition. The standby state 51 in which the block repetitive processing is not performed, the block repetitive number and the repetitive instruction number are set, and the repetitive operation is executed. And a repeat set state 52 in which a repeat operation command is written in the repeat control memory 10 at the same time, and a repeat state 53 in which the repeat operation instruction is read from the repeat control memory 10 and repeat operation is performed. Transition between.

The state transition of the repetitive control device 8 of the second embodiment differs from the state transition of the repetitive control device 8 of the first embodiment in the following points. That is, in the second embodiment, since the iterative control device 8 is configured to perform the next iterative operation subsequent to the end of the iterative operation, the repetitive set state 52 of the next iterative operation is set without the waiting state 51. Transition.

Next, the operation of the program control apparatus according to the second embodiment will be described with reference to FIG. This operation is shown in FIG.
The cycle 1 to the cycle 14 shown in FIG. The operation during each cycle will be described below.

<Cycles 1-7> During cycles 1-7,
Since the same operation as that of the first embodiment is performed by the same instruction as that of the first embodiment, the description thereof is omitted here.

<Cycle 8> In cycle 8, first, the instruction (block repeat instruction n + 6) stored in the address n + 6 of the instruction memory 1 is sent to the instruction decoder 2.

Then, the repetitive instruction n + 2 (second block repetition) is called from the repetitive control memory 10 and executed by the arithmetic unit A6. Also, the computing unit B
4 causes the instruction n + 5 to be executed. Then, the block repeat counter 9 is instructed by the repeat controller 8.
The number of repeated instructions of is decremented by one. Also,
The repetitive control unit 8 sets the number of repetitive operation waits, which indicates the number of unprocessed block repetitive instructions, to 1.

<Cycle 9> In cycle 9, the arithmetic unit A
6, the repeat instruction n + 3 (second block repeat) is called from the repeat control memory 10 and executed.

Although the number of repeated instructions is 0 here,
Since the block repeat count is 1, the block repeat count is decremented by 1 and the repeat instruction count is set to 2.

Then, the number of repeat instructions = 1 (two instructions) and the number of block repeats = 2 (three loops) are written in the repeat control memory 10 by the block repeat instruction n + 6 at address n + 6.

<Cycles 10, 11> Cycles 10, 1
1, the repetitive control memory 10 is operated by the arithmetic unit A6.
To repeat instructions n + 1, n + 2 (block repeat 3
The second time) is sequentially called and executed. Then, the block repeat counter 9 decrements the number of repeat instructions by one, and then repeat instructions n + 7 and n + 8.
Are sequentially written in the control memory 10.

<Cycle 12> In cycle 12, the arithmetic unit A6 calls the repetitive instruction n + 3 (third block repetition) from the repetitive control memory 10 and executes it. Further, the instruction B + 4 executes the instruction n + 9.

Here, the number of repeat instructions is 0 and the number of block repeats is 0. However, since the number of waits for repeat operation is 1, the number of repeat instructions and the number of block repeats are set in the block repeat counter 9. At this time, the repeat controller 8 shifts from the repeat state 53 to the repeat set state 52.

<Cycle 13> In cycle 13, the arithmetic unit A6 calls and executes the repeat instruction n + 7 (first block repeat) from the repeat control memory 10. In addition, by the arithmetic unit B4, the instruction n + 10
Is executed. Then, the block repeat counter 9 decrements the number of repeat instructions by one.

At this time, since the repeat instruction is already stored in the repeat control memory 10, the repeat controller 8 shifts from the repeat set state 52 to the repeat state 53.

<Cycle 14> In cycle 14, the arithmetic unit A6 calls and executes the repeat instruction n + 8 (the first block repeat) from the repeat control memory 10. In addition, the arithmetic unit B4 causes the instruction n + 11
Is executed.

Here, the number of repeated instructions is 0,
Since the block repeat count is 1, the block repeat count is decremented by 1 and the repeat instruction count is set to 1.

The program control device of the second embodiment can also achieve the same effects as the program control device of the first embodiment. In addition, the program control device according to the second embodiment has the advantages that the instructions can be further simplified and the number of instructions can be further reduced.

(Third Embodiment) FIGS. 6 and 7 show a third embodiment of the program control apparatus of the present invention. First, the system configuration of the program control device according to the third embodiment will be described with reference to FIG.

The program control device includes an instruction memory 21 in which an instruction for giving an instruction to each device described below is stored, and an instruction memory 2
An instruction decoder 22 which decodes the output from 1 and gives an instruction to each device, and a data memory 23 which gives data to the arithmetic unit A26 and the arithmetic unit B24 are provided.

The arithmetic unit B24 receives the data from the data memory 23, performs various arithmetic operations, and outputs the arithmetic result to the register B25 to execute repetitive arithmetic operations. Arithmetic unit A2
6 receives the data from the data memory 23 and the register A27, performs various calculations, and outputs the calculation result to the register A7.
Repeated operation is output to. In this way, the implementation
The arithmetic unit A26 and the arithmetic unit B24 in the form 3 both perform repetitive arithmetic operations.

In addition, the program controller is equipped with a repeat controller 28 for performing block repeat control, block repeat counters A29, B30, and block repeat control memories A31, B32. That is, the program control device of the third embodiment is different from the system configuration of the program control device of the first embodiment in that two repeat control memories and two block repeat counters are provided.

The repetitive control unit 28 instructs the arithmetic unit A 26 and the arithmetic unit B 24 about the block repetition number and the repetition instruction number by the block repetition instruction output from the instruction decoder 22, and the repetition instruction is stored in the repetition control memory A 31, Store in B32. Further, it instructs to read from the repetitive control memories A31 and B32. When the calculation is completed, the calculator A26 and the calculator B24 are instructed that the calculation is completed.

The block repeat counter A29 is instructed by the block repeat controller 28 to operate the calculator A26.
The number of block repeats and the number of repeat instructions for the operation performed in step S1 are set, and the count value of the number of block repeats or the number of repeat instructions is decremented by one each time a repeat operation is performed. Also, the block repeat counter B30
Sets the block repeat count and the repeat instruction count of the calculation performed by the calculator B24 according to an instruction from the block repeat control device 28, and the block repeat count or the count value of the repeat instruction count is incremented by one each time the repeat calculation is performed. Clement.

The repeat control memory A31 is for storing or reading a block repeat instruction in the arithmetic unit A26 according to an instruction from the repeat controller 28. The repetitive control memory B32 is for storing or reading a block repetitive command in the arithmetic unit B24 according to an instruction from the repetitive control device 28.

The repetitive control device 28 of the third embodiment is
The internal states have the states of FIG. 2 for the computing units 26A and 24B, respectively.

Next, the operation of the program control device according to the third embodiment will be described with reference to FIG. This operation is shown in FIG.
The cycle 1 to the cycle 13 shown in FIG. The operation during each cycle will be described below.

<Cycles 1 to 7> During cycles 1 to 7,
Since the same operation as that of the first embodiment is performed by the same instruction as that of the first embodiment, the description thereof is omitted here.

<Cycle 8> First, in cycle 8, the instruction (block repeat instruction n + 6) stored in the address n + 6 of the instruction memory 21 is sent to the instruction decoder 22.

Then, the arithmetic unit A26 calls and executes the repeat instruction n + 2 (second block repeat) from the repeat control memory A31. Further, the instruction B + 24 executes the instruction n + 5. And
The block repeat counter A29 decrements the repeat command number A by one.

At this time, the repetitive control of the arithmetic unit B24 of the repetitive controller 28 shifts from the standby state 41 to the repetitive set state 42.

<Cycle 9> In cycle 9, the arithmetic unit A
26, the repeat instruction n + 3 (second block repeat) is called from the repeat control memory A31 and executed.

Here, the number of repeat instructions A is 0, but since the number of block repeats A is 1, the number of block repeats A is decremented by 1 and the number of repeat instructions A is set to 2.

Subsequently, the repeat controller 28 determines the number of repeat instructions B = 1 based on the block repeat instruction n + 6 stored in the address n + 6 of the instruction memory 21.
(2 instructions) and the block repetition number B = 2 (loop of 3 times) are set for the repetition control of the arithmetic unit 24B. Then, the repetition calculation end flag B is set to "0".

<Cycle 10> In cycle 10, the arithmetic unit A26 calls and executes the repeat instruction n + 1 (the third block repeat) from the repeat control memory A31. Then, the block repeat counter A
The number of repeated instructions A is decremented by 29 by 29.

Further, the arithmetic unit B24 executes the repetitive instruction n + 7 (first block repetition) stored in the address n + 7 of the instruction memory 21.
Then, the repeat instruction n + 7 is written in the repeat control memory B32 according to an instruction from the repeat controller 28,
In addition, the number of repeat instructions B of the block repeat counter B30 is decremented by one.

<Cycle 11> In cycle 11, the arithmetic unit A26 and the arithmetic unit B24 both have the repetitive arithmetic flag "0", and therefore the next instruction from the instruction decoder 22 is not executed by the arithmetic units A26 and B24.

Then, the arithmetic unit A26 calls the repetitive instruction n + 2 (third block repetition) from the repetitive control memory A31 and executes it. Then, in accordance with an instruction from the repeat controller 28, the number of repeat instructions A of the block repeat counter A29 is decremented by one.

Further, the repetitive instruction n + 8 (first block repetition) at the address n + 8 is executed by the arithmetic unit B24. Then, the repeat instruction n + 8 is written to the repeat control memory B32.

Here, the number of repeat instructions B is 0, but since the number of block repeats B is 2, the number of block repeats B is decremented by 1 and the number of repeat instructions B is set to 1.

The repetitive control of the computing unit B of the repetitive controller 28 is performed from the repetitive set state 42 to the repetitive state 43.
become.

<Cycle 12> In cycle 12, since the arithmetic operation unit A26 and the arithmetic operation unit B24 both have the repetitive operation flag of "0", the next instruction from the instruction decoder 22 is not executed by the arithmetic operation units A26 and 24B.

Then, the repetitive instruction n + 3 (third block repetition) is called from the repetitive control memory A31 and executed by the arithmetic unit A26. Further, the repetitive instruction n + 7 (second block repetition) is called from the repetitive control memory B32 and executed by the arithmetic unit B24.

Here, the number of repeat instructions A is 0,
Since the block repeat count A is 0, the block repeat counters A29 and B30 are stopped and the repeat end flag A becomes "1".

At this time, the repetitive control of the arithmetic unit A of the repetitive controller 28 shifts from the repetitive state 43 to the standby state 41. Also, the block repeat counter B
The number of repeated instructions B is decremented by 30.

<Cycle 13> In cycle 13, the arithmetic unit B24 calls and executes the repeat instruction n + 8 (the second block repeat) from the repeat control memory B32.

Here, the number of repeat instructions B is 0, but since the number of block repeats B is 1, the number of block repeats B is decremented by 1 and the number of repeat instructions B is set to 1.

According to the program control device of the third embodiment, if a block repeat instruction is present in an instruction which is being processed in parallel with the block repeat instruction during execution of the block repeat instruction, the block repeat instruction is block repeated. The arithmetic unit A26 (or the arithmetic unit B2) which has not been processed
Since step 4) is repeatedly executed, it is possible to realize a program control device capable of further increasing the speed of calculation.

[0104]

According to the present invention as set forth in claim 1 or 4, in parallel with the repeated execution of the second instruction, the instructions stored at the addresses n + x + 1 and subsequent addresses of the instruction memory are sequentially executed. Since the second arithmetic unit is instructed, the block repeat instruction and the instruction group following the block repeat instruction can be executed in parallel. Therefore, it is possible to perform high-speed calculation as compared with the conventional program control device described above. Also, one of the instructions executed in parallel
Second, since it is a block repeat instruction, the instruction can be simplified and the number of instructions can be reduced.

According to the present invention as defined in claim 2 or claim 5, when a block repeat instruction is included in an instruction executed in parallel with the block repeat instruction during execution of the block repeat instruction, the block repeat instruction is executed. Since the instruction is stored in the repetitive control memory, another block repetitive execution can be performed subsequent to the end of the block repetitive execution being executed. Moreover, since the instruction group following the repeat instruction can be executed in parallel with these block repeat instructions, high-speed operation becomes possible as compared with the conventional program control device. In addition, with this configuration, the instructions can be further simplified and the number of instructions can be further reduced.

In particular, according to the present invention as defined in claim 3 or claim 6, during execution of a block repeat instruction, if there is a block repeat instruction in an instruction that is processing in parallel with the instruction, Since the block repeat instruction is repeatedly executed by the arithmetic unit that is not performing the block repeat processing, it is possible to realize a program control device capable of further increasing the speed of calculation.

In addition, even in this configuration, it is possible to execute the block repeat instruction and the block repeat instruction in the instruction which is processing in parallel with the instruction and the instruction group following the block repeat instruction in parallel. Also, the program control device can be operated at a higher speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a program processing device according to a first embodiment.

FIG. 2 is a diagram showing state transitions of the repetitive control device used in the first embodiment.

FIG. 3 is a diagram showing an operation procedure of the program processing device according to the first embodiment.

FIG. 4 is a diagram showing state transitions of the repetitive control device used in the second embodiment.

FIG. 5 is a diagram showing an operation procedure of the program processing device according to the second embodiment.

FIG. 6 is a block diagram showing a system configuration of a program processing device according to a third embodiment.

FIG. 7 is a diagram showing an operation procedure of the program processing device according to the second embodiment.

FIG. 8 is a block diagram showing a system configuration of a conventional program repeat processing device.

FIG. 9 is a block diagram showing a system configuration of a conventional program repeat parallel processing device.

[Explanation of symbols]

1,21 Instruction memory 2,22 Instruction Decoder 3,23 data memory 4,24 Operation unit B 5,25 register B 6,26 Operation unit A 7,27 Register A 8,28 Repetitive control device 9 block repeat counter 10 Repeat control memory 29 block repeat counter A 30 block repeat counter B 31 Repeat control memory A 32 Repeat control memory B

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/38

Claims (6)

(57) [Claims] 1. A program control method for a program control device comprising a first arithmetic unit and a second arithmetic unit, wherein n + 1 to n + x are assigned based on a first instruction stored in address n of an instruction memory. A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored in the address (where x is a positive integer of 1 or more); and in parallel with the repeated execution of the second instruction. , A step of instructing the second arithmetic unit to sequentially execute the instructions stored at addresses n + x + 1 and subsequent addresses of the instruction memory. 2. A program control method for a program control device comprising a first arithmetic unit and a second arithmetic unit, wherein addresses n + 1 to n + x are generated based on a first instruction stored in address n of an instruction memory. A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored in an address (where x is a positive integer of 1 or more); and during the repeated execution of the second instruction, N + x + 1 of the instruction memory executed in parallel with the second instruction
The third instruction stored in the address after the address and n +
x + y (y is a positive integer of 1 or more) comprising the steps of repeating execution instruction stored at the address and instructs the first computing element the, n + x + y + m from the n + x + y + 1 address of the instruction memory (the m 1 or more positive integer) If there is a fourth instruction that executes repeatedly m times stored in the address,
Storing the fourth instruction in a repeat control memory and instructing the first arithmetic unit to repeat execution of the fourth instruction immediately after the repeated execution of the second instruction is completed; Instruction and the fourth instruction in parallel with n + x + y + m
A program control method including a step of sequentially executing instructions stored in addresses +1 and subsequent addresses. 3. A program control method for a program control device comprising a first arithmetic unit and a second arithmetic unit, wherein addresses n + 1 to n + x are generated based on a first instruction stored in address n of an instruction memory. A step of instructing the first arithmetic unit to repeatedly execute x second instructions stored in an address (where x is a positive integer of 1 or more); and during the repeated execution of the second instruction, N + x + 1 of the instruction memory executed in parallel with the second instruction
The third instruction stored in the address after the address and n +
a step of instructing the second arithmetic unit of a repetitive execution instruction stored in the address x + y (y is a positive integer of 1 or more); If there is a fourth instruction for performing, by the second operator that is not handling the repeated execution of the instruction of the second, and the step of executing the iterative process of the fourth instruction, the second instruction or the fourth instruction using the arithmetic unit where repetition processing is completed earlier by the, n + x + y + m + program control method comprising the steps of sequentially executing instructions stored in first address after the address. 4. A program control apparatus for executing the program control method according to claim 1, wherein a first instruction for instructing repetitive execution and x second pieces stored after the next address of the first instruction. Instruction memory including a plurality of instructions, a decoder that decodes the first instruction and the second instruction and outputs various control signals, and a repeat instruction set by the first instruction A counter for decrementing the value of the number of repeat instructions or the number of block repeats each time is executed, a repeat control memory for storing x repeat instructions for block repeat, and the first instruction decoded. Then, the block repeat count and the set of the repeat instruction count are executed, while the block is sent to the counter every time the second instruction is executed. Indicates the count value indicating click repetition rate and the number of repeat instruction, and repeated at the time the operation is completed, the program controller having a repetitive control unit for instructing the end of the instruction to the first computing unit. 5. A program control apparatus for executing the program control method according to claim 2, wherein x instructions are stored after a first instruction for instructing repetitive execution and after the next address of the first instruction in the instruction memory. An instruction memory storing a plurality of instructions including a second instruction, a third instruction for instructing repeated execution, and m fourth instructions for executing an iterative process subsequent to the third instruction; A decoder that decodes an instruction and outputs various control signals; a counter that is set by the first instruction and that decrements the value of the repeat instruction number or the block repeat number by one each time the repeat instruction is executed; A repeat control memory for storing the x second instructions and the m fourth instructions for performing the block iteration, and the first instruction decoded Once, the block number of repetitions and the number of the repeat instruction is set in the counter, a count value indicating the該該repetition number of blocks and the number of the repeat instruction to said counter each time the instruction of the second is executed And instructing the first arithmetic unit that the end of the repetitive operation is completed, and storing the fourth instruction in the repetitive control memory when the third instruction is decoded, A program controller comprising: a repetitive controller for instructing the first arithmetic unit to subsequently execute the fourth instruction upon completion of the second instruction. 6. A program control device for executing the program control method according to claim 3, wherein x instructions are stored after the first address of the first instruction for instructing repeated execution and after the next address of the first instruction of the instruction memory. An instruction memory storing a plurality of instructions including a second instruction, a third instruction for instructing repeated execution, and m fourth instructions for executing an iterative process subsequent to the third instruction; A decoder that decodes an instruction and outputs various control signals; and a first instruction that is set by the first instruction and that decrements the value of the number of repeat instructions or the number of block repeats by one each time a repeat instruction is executed . The counter is set by the third instruction and the repeat instruction is executed.
The number of repeat instructions or block repeat count
A second counter that decrements by one, and x second instructions and m that perform block repetition
And repetitive control memory for storing pieces of the fourth instruction, when the instruction of the first is decoded, relative to the first counter, and sets the block number of repetitions and the number of the repeat instruction, said Each time the second instruction is executed, the block repeat count and the count value indicating the repeat instruction count are instructed, the end of the iterative operation is instructed to the first arithmetic unit, and When 3 instruction is decoded, relative to the second computing unit, the instruction of the third instructs to perform instructions fourth, with respect to the second counter <br/> data Setting a block repeat count of the fourth instruction and the repeat instruction count, designating a count value indicating the block repeat count and the repeat instruction count each time the fourth instruction is executed, and The second command and the fourth command are finished first Respect calculator, a program controller having a repetitive control unit for sequentially executing instructions stored in the address of the instructions after the fourth.