JPH04346129A - Method and device for program repeat control - Google Patents

Abstract

PURPOSE:To offer a program repeat processor whose repeat counter set instruction execution cycle is substantially zero. CONSTITUTION:A memory 1 stores a repeat counter set instruction 32 as a repeat process control instruction behind an instruction A31 to be processed repeatedly. A decoder register 5, a repeat counter 8, an instruction detection signal 10, a repeat control part 11, and gates 16 and 17 are also provided. Consequently, the execution of the instruction A31 and the execution of the repeat counter set instruction 32 are performed in parallel and the execution of the repeat counter set instruction 32 is shortened to a substantially zero cycle.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program repeat control method and apparatus for controlling the repeated execution of one instruction in a microprocessor.

0002

[Background Art] In recent years, efforts have been made to achieve high-speed program execution or to reduce the number of words in instruction memory.
A program repeat processing device has been devised, as shown in Japanese Patent No. 42301, which repeatedly executes an instruction once fetched.

An example of the above-mentioned conventional program repeat control device will be described below with reference to the drawings.

FIG. 7 shows a block diagram of a conventional program repeat control device. In FIG. 7, 71 is a repeat counter that counts the number of times the program is repeatedly executed (synonymous with the number of repeats), 72 is a memory that stores instructions, 73 is a program counter that provides an address to the memory 72, and 74 is used to temporarily store the output of the program memory 72. The holding instruction register 75 is a control unit that decodes the output of the instruction register and outputs various control signals.

The operation of the conventional program repeat control device configured as described above will be explained below. First, as shown in FIG. 8, the repeat counter set instruction 81 is placed at address n of the memory 72, and the instruction A8 is placed at address n+1.
Instruction B83 is stored at addresses 2 and n+2, respectively. In this state, when the program counter 73 reaches n, a repeat counter set instruction 81 is stored in the instruction register 74, and the number of repeats (7 in this case) included in the instruction code is stored in the repeat counter 71. The control unit 75 receives the output of the instruction register 74 and then transfers the instruction stored in the instruction register 74 to the repeat counter 71.
The control is repeated until becomes zero. When the program counter 73 reaches n+1 and the instruction A82 is stored in the instruction register 74, the instruction A82 will be executed seven times as shown in FIG. (Tokuko Showa 62-42301
Publication No.)

[0006]

However, in the above configuration, as shown in FIG. 9, the execution cycle of the repeat counter set instruction appears explicitly. On the other hand, digital signal processing processor (Digital Sign
al Processor (hereinafter referred to as DSP) often repeatedly executes one instruction or a group of instructions several thousand times, but when using a conventional program repeat control device, as mentioned above, non-operating instructions such as the repeat counter set instruction are executed repeatedly. This has the problem of consuming thousands of machine cycles to execute an instruction, which is a major hindrance to high-speed calculation, which is the purpose of a DSP.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a program repeat processing device in which the repeat counter set instruction execution cycle is substantially 0 cycles.

[0008]

[Means for Solving the Problems] The present invention provides a first instruction to be repeatedly executed and a second instruction stored at an address next to the first instruction and instructing repeated execution of the first instruction. a program counter that provides an address signal to the memory; an instruction register that temporarily stores the contents of the memory indicated by the program counter; and a decoder that decodes the output of the instruction register and outputs various control signals. , a register that temporarily holds the output of the decoder, a counter that is preset by the second instruction and whose value is decremented by 1 each time execution of the first instruction is completed, and instructions other than the second instruction are decoded by the decoder. When the program counter is incremented, the instruction register is instructed to capture the memory output, and the register is instructed to capture the decoded output, and the decoder decodes the second instruction. When the program counter is incremented, the instruction register is instructed to be prohibited from receiving the memory output, and the register is instructed to be prohibited from receiving the decoded output from now on. In the execution cycle of the second instruction, the counter is instructed to write the number of repetitions specified by the first instruction, and the counter decreases its value by 1 each time the execution of the first instruction is completed. If it is indicated that the specified number of repetitions have been performed, the program counter is set to resume incrementing the contents, the instruction register is set to resume fetching the memory output, and the register is set to resume fetching the decoded output. The program repeat control device includes a control means for instructing restart of operation.

[0009]

[Operation] With the above-described configuration, the present invention has the above-mentioned structure. After starting execution of the first instruction to be repeatedly processed in the memory,
In parallel with this, the second command instructs the repeated execution of the first command, and the control means controls the repeated execution of the first command.

0010

Embodiment A program repeat control device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a program repeat control device according to an embodiment of the present invention, and as shown in FIG. 2, this device operates with two-phase clocks φ1 and φ2. In Figure 1, 1 is a memory that stores instructions, 2 is a program counter that provides an address signal to memory 1 and whose contents are incremented at the rising edge of the φ1 clock, and 3 is an instruction register that captures the output of memory 1 at the rising edge of the clock φ1. , 4 is a decoder that decodes the output of the instruction register 3, 5 is a decoder register that takes in the output of the decoder 4 at the rising edge of the clock φ1,
6 various control signals which are the output of the decoder register 5; 7
8 is a latch that captures a part of the output of instruction register 3 at the rising edge of clock φ2; 8 is a repeat counter that takes the output of latch 7 as its initial value and counts down at the rising edge of clock φ1; 10 is a command detection signal which becomes "1" when the decoder 4 decodes a repeat counter set command 32 described later, 11 is a zero detection signal 9 and a command detection signal 10 as inputs. The internal state is changed at the rising edge of clock φ2, and a preset signal 12 and a count permission signal 13, which will be described later, are sent to the counter 8, and a gate 16, which will be described later, is sent to the counter 8.
12 is a repeat control unit that outputs an update prohibition signal 14 (described later) to a gate 17 (described later), a decoder register update prohibition signal 15 (described later) to a gate 17 (described later);
A preset signal 13 instructs the repeat counter 8 to capture the output of the clock φ1 at the rising edge of the clock φ1.
A count permission signal instructs to count down at the rising edge of clock φ1; 14 is an update prohibition signal that prohibits the program counter 2 and instruction register 3 from updating the contents; 15 is a signal that prohibits the decoder register 5 from updating the contents. Decoder register update prohibition signal to be prohibited; 16 is a gate that ANDs the update prohibition signal 14 and clock φ1 and outputs the result to the program counter 2 and instruction register 3; 17 is the logic of the decoder register update prohibition signal 15 and clock φ1. This is a gate that takes the product and outputs the result to the decoder register 5.

FIG. 3 shows the contents of the memory 1, in which an instruction A31 to be repeatedly executed is stored at address n, and a repeat counter set instruction 32 that instructs repeated execution of the instruction at address n+1 is stored at address n+1. But n+2, n+3
An instruction B33 and an instruction C34 each executed once are stored at the address.

Furthermore, FIG. 4 shows changes in the internal state of the repeat control section 11. The repeat control unit 11 has three internal states: a wait state 41, a repeat counter set state 12, and a repeat counter countdown state 43. To transition from the wait state 41 to the repeat counter set state 42, the decoder 4 issues a repeat counter set command 3.
This is performed using the clock φ2 when the instruction detection signal 10 indicating that the command detection signal 2 is detected is "1". Transition from the repeat counter set state 42 to the repeat counter countdown set state 43 is performed unconditionally at clock φ2. The transition from the repeat counter countdown set state 43 to the wait state 41 occurs at the clock φ when the zero detection signal 9, which indicates that the content of the repeat counter 8 is zero, is "1".
It is done in 2. Further, in each state, the output signal of the repeat control section 11 is as shown in FIG.

Further, FIG. 6 shows the state of each element and the movement of each signal constituting the program repeat device shown in FIG. 1. FIG. 6 shows the cycle numbers used in the following explanation, and each cycle is φ1, φ as shown in FIG.
It consists of two clocks: 2.

Regarding the program repeat control device configured as described above, FIGS. 1 and 3, FIG. 4, FIG.
The operation will be explained using FIG. 6 with reference to the cycle numbers shown in FIG. (1) Cycle number = 1 - Program counter 2: Incremented by clock φ1 and the content becomes n. -Memory 1: Access address n. (2) Cycle number = 2 - Program counter 2: Incremented by clock φ1 and the content becomes n+1. -Memory 1: Access address n+1. - Instruction register 3: At clock φ1, fetch instruction A31, which is the content of address n accessed in the previous cycle. - Decoder 4: Performs decoding processing of instruction A31. (3) Cycle number = 3 - Program counter 2: Incremented by clock φ1 and the content becomes n+2. -Memory 1: Access address n+2. - Instruction register 3: At clock φ1, fetch repeat counter set instruction 32, which is the contents of address n+1 accessed in the previous cycle. - Decoder 4: As a result of decoding the repeat counter set instruction 32, the instruction detection signal 10 is set to "1". - Decoder register 5: Takes in the decoding result of instruction A31 decoded by decoder 4 in the previous cycle at clock φ1. As a result, some of the various control signals 6 become active and the instruction A31 is executed. - Repeat control unit 11: Since the instruction detection signal 10 becomes "1", the internal state changes from the wait state 41 to the repeat counter set state 42 at clock φ2. As a result, the output of the repeat control section becomes as shown in the repeat counter set state in FIG. - Latch 7: Takes in the part indicating the number of repeats from the repeat counter set instruction 32 stored in the instruction register 3 at clock φ2. (4) Cycle number = 4 - Program counter 2: Incremented by clock φ1 and the content becomes n+3. -Memory 1: Access address n+3. - Instruction register 3: At clock φ1, fetch instruction B33, which is the contents of address n+2 accessed in the previous cycle. - Decoder 4: Performs decoding processing of instruction B33. - Decoder register 5: Since the decoder register update prohibition signal 15 is "1", the clock φ1 is blocked by the gate 17. Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the decoding result of instruction A31. Therefore, instruction A31 is executed following the previous cycle. - Repeat counter 8: Since the preset signal 12 is "1", it takes in the value 3 held by the latch 7 at clock φ1. - Repeat control unit 11: Internal state changes from repeat counter set state 41 to repeat counter countdown state 43 at clock φ2. As a result, the output of the repeat control section becomes as shown in the countdown state of the repeat counter in FIG. (4) Cycle number = 5 to 6 - Program counter 2: Since the update prohibition signal 14 is "1", the clock φ1 is blocked by the gate 16. Therefore, the contents of the program counter 2 do not change and remain n+3. -Memory 1: Access address n+3. - Instruction register 3: Since the update prohibition signal 14 is "1", the clock φ1 is blocked by the gate 16. Therefore, the contents of the instruction register 3 remain unchanged and remain the instruction B33. - Decoder 4: Performs decoding processing of instruction B33. - Decoder register 5: Since the decoder register update prohibition signal 15 is "1", the clock φ1 is blocked by the gate 17. Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the decoding result of instruction A31. Therefore, instruction A31 is executed following the previous cycle.・Repeat counter 8: Count permission signal 13 is “1”
Therefore, the countdown is performed using the clock φ1. - Repeat control section 11: Since the zero detection signal 9 indicating that the content of the repeat counter 8 has become zero is "0", there is no internal state change. Then its output will also be the same as the previous cycle's state. (5) Cycle number = 7 - Program counter 2: Since the update prohibition signal 14 is "1", the clock φ1 is blocked by the gate 16. Therefore, the contents of the program counter 2 do not change and remain n+3. -Memory 1: Access address n+3. - Instruction register 3: Since the update prohibition signal 14 is "1", the clock φ1 is blocked by the gate 16. Therefore, the contents of the instruction register 3 remain unchanged and remain the instruction B33. - Decoder 4: Performs decoding processing of instruction B33. - Decoder register 5: Since the decoder register update prohibition signal 15 is "1", the clock φ1 is blocked by the gate 17. Therefore, the contents of the decoder register 5 maintain the state of the previous cycle, that is, the decoding result of instruction A31. Therefore, instruction A31 is executed following the previous cycle.・Repeat counter 8: Count permission signal 13 is “1”
Therefore, the countdown is performed using the clock φ1, but
This time, the result is zero, so zero detection signal 9 is set to “1”.
- Repeat control section 11: Since the zero detection signal 9 is "1", the internal state changes to the wait state 41 at clock φ2.Then, its output becomes as shown in the wait state in FIG. (6) Cycle number = 8 - Program counter 2: Since the update prohibition signal 14 has become "0", counting up is restarted.Then, the contents of program counter 2 become n+4. -Memory 1: Access to address n+4.・Instruction register 3: Since the update prohibition signal 14 has become "0", the fetching of the instruction register 3 output at the clock φ1 of the memory 1 output is resumed. The resulting content becomes instruction C34. - Decoder 4: Performs decoding processing of instruction C34. - Decoder register 5: Since the decoder register update prohibition signal 15 has become "0", the import of the decoder 4 output into the decoder register 5 is resumed. As a result, the content becomes the decoding result of instruction B33, and instruction B33 is executed. - Repeat counter 8: Since all control signals to repeat counter 8 are "0", it does not perform any operation. - Repeat control unit 11: Since the command detection signal 10 is "0", it maintains the waiting state shown in FIG. 5. (7) Cycle number = 9 - Program counter 2: The program counter is incremented by clock φ1, and its contents become n+5. -Memory 1: Access address n+5.・Instruction register 3: Takes in the output of memory 1 at clock φ1. - Decoder 4: Performs decoding processing of the output of the instruction register 3. - Decoder register 5: Takes in the decoding result of instruction C34, which is the output of decoder 4, at clock φ1. Therefore, instruction C34 will be executed.

As described above, according to this embodiment, the memory 1
In this example, a repeat counter set instruction 32, which is a repeat processing control instruction, is placed after the instruction A31 to be subjected to repeat processing.
, a decoder register 5, a repeat counter 8, an instruction detection signal 10, a repeat control section 11, and a gate 16.
7, the execution of the instruction A31 and the execution of the repeat counter set instruction 32 are executed in parallel.
The repeat counter set instruction 32 can be executed in virtually 0 cycles.

In this embodiment, the number of repeats is included in the repeat counter set instruction 32, but it may be given here from a register not shown.

[0018]

As described above, the present invention provides a repeat counter set instruction, which is a repeat processing control instruction, after an instruction to be subjected to repeat processing in a memory, and a decoder register, a repeat counter, and a repeat control section. The instruction execution and the repeat counter set instruction can be executed in parallel, and the repeat counter set instruction can be executed in substantially 0 cycles.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a program repeat processing device in an embodiment of the present invention.

FIG. 2 is a diagram showing clocks used in the same embodiment.

FIG. 3 is a diagram showing the contents of the memory 1 in the same embodiment.

FIG. 4 is a diagram showing internal state transitions of the repeat control section 11 in the same embodiment.

FIG. 5 is a diagram showing the output of the repeat control section 11 in the same embodiment.

FIG. 6 is a diagram showing an instruction execution process for explaining the operation in the same embodiment.

FIG. 7 is a block diagram of a conventional program repeat processing device.

FIG. 8 is a diagram showing the contents of a memory 72 in the conventional example.

FIG. 9 is a diagram showing an instruction execution process for explaining the operation in the conventional example.

[Explanation of symbols]

1 Memory 2 Program counter 3 Instruction register 4 Decoder 5 Decoder register 8 Repeat counter 11 Repeat control section 16 Gate 17 Gate

Claims (2)

[Claims] Claim 1: Pipeline processing of instruction fetch stage, decode stage, and execution stage, and cycle n
As a result of instruction decoding at the decode stage, if the instruction instructs to repeatedly execute the instruction currently in the execution stage m times, then in the execution stage after cycle n+1, the process performed in the execution stage of cycle n is repeated m times. A program repeat control method that executes programs repeatedly. 2. A memory that stores at least a first instruction to be repeatedly executed and a second instruction that is stored at an address next to the first instruction and instructs to repeatedly execute the first instruction; a program counter that provides an address signal to a memory; an instruction register that temporarily stores the contents of the memory indicated by the program counter; a decoder that decodes the output of the instruction register and outputs various control signals; a register for temporary holding, a counter that is preset by the second instruction and whose value is decremented by 1 each time execution of the first instruction is completed, and when the decoder decodes an instruction other than the second instruction, Incrementing the contents to the program counter, capturing the memory output to the instruction register,
The register is instructed to capture the decoded output, and when the second instruction is decoded by the decoder, the program counter is prohibited from incrementing the contents thereafter, and the instruction register is instructed to capture the memory output. Instructs the register to prohibit the subsequent capture of the decoded output, and further instructs the counter to write the number of repetitions specified by the first instruction in the execution cycle of the second instruction. However, if the counter decreases its value by 1 every time the execution of the first instruction is completed, and the result indicates that the specified number of repetitions has been performed, the program counter is instructed to restart the increment operation of the contents. A program repeat control device comprising control means for instructing an instruction register to resume the fetching operation of the memory output, and a control means for instructing the register to restart the fetching operation of the decoded output.