JPH064283A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide the microprocessor which can cancel the external memory access of ineffective instruction fetch. CONSTITUTION:When a pipeline flash signal 117 or an advanced lunch signal 118 is detected by a logic gate 103 and the external memory access of instruction fetch being in course of access is made ineffective, an instruction fetch cancel signal 104 is generated indicating that the external memory access of this instruction fetch is ineffective. Consequently, the program execution speed is increased because the wait time of the external memory access of next effective fetch due to that of unnecessary instruction fetch is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor which has a pipeline processing mechanism and performs external memory access for instruction fetch.

[0002]

2. Description of the Related Art In a microprocessor,
Execution of each instruction includes instruction fetch, instruction decode, operand address calculation, operand data fetch,
After several cycles of sequential operations such as execution of operations and writing of results, the process ends. 2. Description of the Related Art Conventionally, a microprocessor has a pipeline processing mechanism in which, in order to achieve high-speed processing, these operations are divided and carried out in a flow-like manner, so that execution of a plurality of instructions is performed simultaneously at the same time. There is something.

FIG. 5 is a block diagram showing a conventional microprocessor having a pipeline processing mechanism. In the figure, 501 is a conventional microprocessor, 105 is a memory, and 502 is a response circuit. Reference numeral 106 denotes a pipeline processing mechanism in the microprocessor 501, which includes a plurality of stages. 106A is an instruction fetch stage (hereinafter, IF stage), 106B is a decode stage (hereinafter, D stage), 106C is an operand address calculation stage (hereinafter, A stage), 1
06D is an operand fetch stage (hereinafter referred to as OF stage), 106E is an instruction execution stage (hereinafter referred to as E)
It is called a stage). 107 is the IF stage 106
A program counter in A, 108 is an external memory access control unit (hereinafter referred to as an access unit) in the microprocessor 501. 109 is a microprocessor 50
1 and a clock signal input to the response circuit 502, 11
0 is a reset signal input to the microprocessor 501 and the response circuit 502. 111 is the access unit 10
8 is an address strobe signal (hereinafter referred to as an AS signal) input to the response circuit 502, and 112 is the access unit 1.
08 is a data strobe signal (hereinafter referred to as a DS signal) input to the response circuit 502, and 113 is the response circuit 50.
2 is a data transfer complete signal (hereinafter referred to as a DC signal) input to the access unit 108.

Reference numeral 114 denotes the access unit 10 from the memory 105.
8 is an external data bus to be input. 115A-11
5E is an internal data bus of the microprocessor 501, and 115A is from the access unit 108 to the IF stage 10.
6A, 115B to IF stage 106A to D stage 106B, 115C to D stage 106B to A stage 106C, 115D to A stage 106C to OF stage 106D, and 115E to OF stage 10.
Input from 6D to E stage 106E, respectively.
Reference numeral 116 denotes an instruction fetch external memory access request signal (hereinafter referred to as an IF request signal) input from the IF stage 106A to the access unit 108. Reference numeral 117 denotes E stage 106E to IF stage 106A, D stage 1
06B, A stage 106C, and OF stage 106
It is a pipeline flash signal (hereinafter referred to as a flash signal) input to each stage of D. Reference numeral 118 is a preceding branch signal input from the D stage 106B to the IF stage 106A.

FIG. 6 is a block diagram showing an example of the response circuit 502. In the figure, 109 to 113 are the same as those shown in FIG. Reference numeral 601 is a logic gate, 602 is a delay circuit, and 603 is a flip-flop (hereinafter referred to as FF).
Is. The logic gate 601 receives the DS signal 112 and the reset signal 110 and outputs an internal signal 604.
The delay circuit 602 has a reset signal 110 and an AS signal 11
1 and the clock signal 109 are input, and the internal signal 605
Is output. The internal signal 604 and the internal signal 605 are input to the FF 603, and the DC signal 113 is output.

FIG. 7 is a timing chart for explaining the operation in the case where a pipeline flush occurs while the microprocessor 501 is accessing the memory 105 for fetching an external memory. In FIG. 7, 109, 111-114, 116-
Reference numeral 118 is the same as that shown in FIG.

FIG. 8 is a timing chart for explaining the operation in the case where a preceding branch occurs while the microprocessor 501 is accessing the memory 105 for external memory access for instruction fetch. In FIG.
109, 111 to 114, 116 to 118 are the same as those shown in FIG.

Next, the operation will be described. In the following description, it is assumed that the memory 105 stores the instruction code and has the performance of being accessible in 6 cycles of the clock signal 109. It is assumed that the signals 110 to 113 and 116 to 118 have negative logic. Further, one cycle is two cycles of the clock signal 109. The transition point from the L level to the H level of the signal is described as rising, and the transition point from the H level to the L level is described as falling.

First, the operation of each block in the microprocessor 501 will be described with reference to FIG. When performing the instruction fetch, the IF stage 106A sets the IF request signal 116 to the L level for one cycle of the clock signal 109 and requests the access unit 108 to activate the external memory access for the instruction fetch. When the access unit 108 detects that the IF request signal 116 has become L level,
If the external memory is not being accessed, the external memory access is started immediately using the value held in the program counter 107 as an address. If the external memory is being accessed, the external memory access is made using the value held in the program counter 107 as the address from the end. Start. Access section 1
The instruction code fetched from the memory 105 by the external memory access 08 is input to the IF stage 106A via the internal data bus 115A. The IF stage 106A, which has fetched the instruction code, inputs the instruction code to the D stage 106B via the internal data bus 115B in the next cycle, and at the same time, the program counter 1
07 is incremented to fetch the next instruction code. The D stage 106B has an internal data bus 115B.
The instruction code received via the internal data bus 1 is decoded and the D code which is the decoding result is decoded in the next cycle.
Input to A stage 106C via 15C. The A stage 106C calculates the address of the operand as required by the D code received via the internal data bus 115C, and in the next cycle, outputs the D code and the address value of the operand to the OF stage 106D via the internal data bus 115D. input. The OF stage 106D uses a path (not shown) depending on the address value of the operand received via the internal data bus 115D, if necessary.
The operand is fetched through the access unit 108, and the D code and the operand are input to the E stage 106E through the internal data bus 115E in the next cycle. The E stage 106E executes an instruction with the D code and operand received via the internal data bus 115E.

The stages 106A to 106E operate in parallel. When a branch instruction is executed at the E stage 106E, it is necessary to execute the instruction at the branch destination address after the execution of the branch instruction. However, in each stage of 106A to 106D, since the processing of the instruction following the branch instruction in the address order has already been performed, it is necessary to invalidate these processing and cause the IF stage 106A to fetch the instruction of the branch destination address. There is. Therefore, when the E stage 106E executes the branch instruction,
The flash signal 117 is set to L level for one cycle of the clock signal 109. Each of the stages 106A to 106D is initialized when it detects that the flash signal 117 has become L level. Also, the IF stage 106A
After initialization by the flash signal 117, sets the branch destination address value in the program counter 107 from the E stage 106E via a path not shown, and starts instruction fetch of the branch destination address.

Among the instructions, there is a preceding branch instruction. The preceding branch instruction is a branch instruction for reducing the time loss due to pipeline flush at the time of executing the branch instruction in the E stage 106E, and is detected in the D stage 106B. When the decoded instruction is the preceding branch instruction, the D stage 106B calculates the address of the branch destination and sets the preceding branch signal 118 to the L level for one cycle of the clock signal 109. The IF stage 106A outputs the preceding branch signal 118.
When it is detected that the L level has become L level, it is initialized. Further, the IF stage 106A sets the address value of the branch destination to the D stage 106 after initialization by the preceding branch signal 118.
Program counter 10 from B via a route not shown
7 is set and the instruction fetch of the branch destination address is started.

Next, the operation of the response circuit 502 will be described with reference to FIG. The logic gate 601 outputs the DS signal 112.
Is at the H level or the reset signal 110 satisfies the L level condition, the internal signal 604 is at the H level, and when the above condition is not satisfied, the internal signal 604 is at the L level. When the AS signal 111 becomes L level, the delay circuit 602 counts the rising of the clock signal 109 from the rising of the clock signal 109 while the AS signal 111 is at L level, and the rising number of the clock signal 109 becomes 5 Then, the internal signal 605 is set to the H level, and the internal signal 605 is set to the L level at the next rising of the clock signal 109. Further, the delay circuit 602 is initialized when the reset signal 110 becomes L level, and sets the internal signal 605 to L level.

The FF 603 is set when the internal signal 605 becomes H level, and sets the DC signal 113 to L level,
When the internal signal 604 becomes H level, it is reset and DC
The signal 113 is set to H level. Therefore, DC signal 1
13, the AS signal 111 becomes L level, and the AS signal 1
While 11 is at L level, it becomes L level at the fifth rising edge of the clock signal 109 counted from the rising edge of the clock signal 109, and becomes H level at the next rising edge of the DS signal 112. When the reset signal 110 becomes L level, the delay circuit 602 is initialized and D
The C signal 113 becomes H level.

The operation when the pipeline flush occurs while the microprocessor 501 is accessing the memory 105 for external memory for instruction fetch will be described with reference to FIGS. 5, 6 and 7. FIG. Hereinafter, for convenience of explanation, in FIG.
I am wearing 18. Further, the rising edge of the clock signal 109 from the cycle n-1 to the cycle n is described as a rising edge of the cycle n, and the falling edge of the clock signal 109 during the cycle n is described as a falling edge of the cycle n. The instruction A is fetched from the cycle 1. At the rising edge of cycle 1, the IF stage 106A sets the IF request signal 116 to the L level, and the access unit 108 is not accessing the external memory.
An external memory access for fetching the instruction A is started using the value held in the program counter 107 as an address, and the address is given to the memory 105 via an external address bus (not shown). At the trailing edge of cycle 1, the access unit 108 sets the AS signal 111 to the L level and gives an address. At the rising edge of cycle 2, the access unit 108 sets D
The S signal 112 is set to L level to indicate that data is being read. The access unit 108 returns the AS signal 111 to the H level at the trailing edge of the cycle 2.

The memory 105 outputs the code of the instruction A on the external data bus 114 during the cycle 5. Response circuit 5
02 is the fifth rising edge of the clock signal 109 (the rising edge of the cycle 2) of the clock signal 109 while the AS signal 111 is at the L level (the rising edge of the cycle 6).
At the rising edge), the DC signal 113 is set to the L level to indicate that valid data (the code of the instruction A in this case) has been output to the external data bus 114. Access unit 10
When detecting that the DC signal 113 has become the L level, 8 reads the data on the external data bus 114 (in this case, the code of the instruction A) and transfers the instruction A of the instruction A to the IF stage 106A via the internal data bus 115A. Give the code. The access unit 108 sets the DS signal 112 to H level at the next rise of the clock signal 109 (rise of cycle 7).
It returns to the level and indicates that the microprocessor 501 has completed reading the data (in this case, the code of the instruction A).

The response circuit 502 returns the DC signal 113 to the H level at the rising edge of the DS signal 112 (the rising edge of the cycle 7). The external memory access for fetching the instruction A is completed in the above 6 cycles of 1 to 6. IF stage 1
06A increments the value held in the program counter 107, and fetches the instruction B from cycle 7 in the same manner as fetching the instruction A. Here, from the falling edge of the cycle 8 to the falling edge of the cycle 9, the flash signal 117 is
Suppose you have reached the level. At the fall of cycle 8, 106
Each stage from A to 106D is initialized. The IF stage 106A outputs the address value of the branch destination to the E stage 106.
Program counter 10 from E via a route not shown
7, the IF request signal 116 is set to the L level from the rising edge of the cycle 9 to the rising edge of the cycle 10 in order to start fetching the instruction X at the branch destination address. However, since the external memory access for fetching the instruction B is in progress, the access unit 108 makes the start of the external memory access for fetching the instruction X wait until the end of the external memory access for fetching the instruction B. When the external memory access for fetching the instruction B is completed at the rising edge of the cycle 13, the access unit 108 discards the code of the instruction B read, and the external memory for fetching the instruction X is operated in the same operation as the fetch of the instruction A from the cycle 13. Access.

The operation when the preceding branch occurs while the microprocessor 501 is accessing the memory 105 for external memory for instruction fetch will be described with reference to FIGS. 5, 6 and 8. The six cycles of cycles 1 to 6 are the same as the external memory access operation for fetching the instruction A in cycles 1 to 6 of FIG. The IF stage 106A increments the value held in the program counter 107, and fetches the instruction B from cycle 7 in the same manner as the fetching of the instruction A. Here, it is assumed that the preceding branch signal 118 is at the L level from the fall of the cycle 8 to the fall of the cycle 9. At the trailing edge of cycle 8, the IF stage 106A is initialized, the branch destination address value is set in the program counter 107 from the D stage 106B via a path not shown, and the fetch of the instruction Y at the branch destination address is started. In order to do so, the IF request signal 116 is set to the L level from the rising of the cycle 9 to the rising of the cycle 10. However, since the external memory access for fetching the instruction B is in progress, the access unit 108 makes the start of the external memory access for fetching the instruction Y wait until the external memory access for fetching the instruction B ends. When the external memory access for fetching the instruction B is completed at the rising edge of the cycle 13, the access unit 108 discards the code of the read instruction B, and performs the same operation as the fetch of the instruction A from the cycle 13 to the external memory for fetching the instruction Y. Access.

[0018]

Since the conventional microprocessor is constructed as described above, if a pipeline flush or a preceding branch occurs during an instruction fetch external memory access, the fetch is performed by this external memory access. Although the instruction to be executed (instruction B in FIGS. 7 and 8) is invalid, the next valid instruction (instruction X and instruction Y in FIGS. 7 and 8) until this external memory access is completed.
There was a problem that external memory access for fetching could not be started.

The present invention has been made in order to solve the above problems, and provides a microprocessor capable of canceling an external memory access of an instruction fetch invalidated by a pipeline flush or a preceding branch during the access. With the goal.

[0020]

The microprocessor according to the present invention detects that either the flash signal or the preceding branch signal is detected and the external memory access of the currently fetched instruction fetch is invalid. The detection means for outputting the instruction fetch cancel signal shown is provided.

[0021]

The instruction fetch cancel signal according to the present invention indicates the external memory access of the instruction fetch currently being accessed when a pipeline flush or a preceding branch occurs.
It can be forcibly terminated via an external circuit.

[0022]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1, 105 to 118 are the same as those of the conventional example shown in FIG. 101 is a microprocessor according to an embodiment of the present invention, 102 is a response circuit, 103
Is a logic gate provided as a detection means in the microprocessor 101. The flash signal 117 and the preceding branch signal 118 are input to the logic gate 103. 1
Reference numeral 04 is an instruction fetch cancel signal 104 output from the logic gate 103. The instruction fetch cancel signal 104 is input to the response circuit 102.

FIG. 2 is a block diagram showing an embodiment of the response circuit 102. In FIG. 2, 104, 109 to 113
Is the same as that shown in FIG. 201 to 204 are logic gates, 205 is a delay circuit, and 206 is a flip-flop (hereinafter referred to as FF). Logic gate 201 is D
The S signal 112 and the reset signal 110 are input and the internal signal 207 is output. The logic gate 202 receives the reset signal 110 and the instruction fetch cancel signal 104, and outputs an internal signal 208. The clock signal 109, the DS signal 112, and the instruction fetch cancel signal 104 are input to the logic gate 203 and the internal signal 209 is output. The delay circuit 205 receives the AS signal 111, the clock signal 109, and the internal signal 208, and receives the internal signal 2
10 is output. The internal signal 209 and the internal signal 210 are input to the logic gate 204, and the internal signal 211 is output. The FF 206 receives the internal signal 207 and the internal signal 211, and outputs the DC signal 113.

FIG. 3 is a timing chart for explaining the operation when the pipeline flush occurs while the microprocessor 101 is accessing the memory 105 for external memory fetching an instruction.
In FIG. 3, 104, 109, 111 to 114, 11
6 to 118 are the same as those shown in FIG.

FIG. 4 is a timing chart for explaining the operation when the preceding branch occurs while the microprocessor 101 is accessing the memory 105 for external memory access for instruction fetch. In FIG.
104, 109, 111-114, 116-118 are the same as those shown in FIG.

Next, the operation will be described. In the following description, the instruction fetch cancel signal 104 has a negative logic.

First, the instruction fetch cancel signal 104 will be described with reference to FIG. The logic gate 103 is
While one of the flash signal 117 and the preceding branch signal 118 satisfies the L level condition, the instruction fetch cancel signal 104 is set to the L level, and when the above condition is not satisfied, the instruction fetch cancel signal 1
04 is set to H level.

Next, the operation of the response circuit 102 will be described with reference to FIG. The logic gate 201 outputs the DS signal 112
Is at the H level or the reset signal 110 satisfies the L level condition, the internal signal 207 is at the H level, and when the above condition is not satisfied, the internal signal 207 is at the L level. The reset signal 110 of the logic gate 202 is L
The internal signal 208 is set to the L level while the level or the instruction fetch cancel signal 104 satisfies the L level condition, and the internal signal 20 is set when the above condition is not satisfied.
8 is set to H level. The logic gate 203 sets the internal signal 209 to the H level while the clock signal 109 is at the H level, the DS signal 112 is at the L level, and the instruction fetch cancel signal 104 is at the L level, and the above conditions are satisfied. When there is not, the internal signal 209 is set to L level. When the AS signal 111 becomes L level, the delay circuit 205 receives the clock signal 10 while the AS signal 111 is at L level.
The clock signal 109 that counts the rising edge of the clock signal 109 from the rising edge of 9 and has a count of 5
The internal signal 201 is set to the H level at the rising edge of, and the internal signal 210 is set to the L level at the next rising edge of the clock signal 109. In addition, the delay circuit 205 uses the internal signal 208.
Is initialized when L becomes L level, and the internal signal 210 becomes L level. Therefore, the delay circuit 205 is initialized when the reset signal 110 satisfies the L level or the instruction fetch cancel signal 104 satisfies the L level.

The logic gate 204 sets the internal signal 211 to the H level while the internal signal 209 satisfies the H level condition or the internal signal 210 satisfies the H level condition, and outputs the internal signal 211 when the above condition is not satisfied. Set to L level. F
The F206 is set when the internal signal 211 becomes H level, sets the DC signal 113 to L level, and the internal signal 207
Is reset to H level and DC signal 113 is set to H level.
Level. Therefore, the DC signal 113 becomes the L level at the fifth rising edge of the clock signal 109 counted from the rising edge of the clock signal 109 while the AS signal 111 becomes the L level, and the next DS
The signal 112 rises to the H level. Also, DS
When the signal 112 is at L level, that is, when the microprocessor 101 is accessing the memory 105 and the instruction fetch cancel signal 104 becomes L level, the delay circuit 205 is initialized and the DC signal 113 is generated.
Becomes L level at the rising of the clock signal 109 while the instruction fetch cancel signal 104 is at the L level, and becomes H level at the next rising of the DS signal 112. When the reset signal 110 goes low, the delay circuit 205 is initialized and the DC signal 113 goes high.

The operation when the pipeline flush occurs while the microprocessor 101 is accessing the memory 105 for external memory for instruction fetch will be described with reference to FIGS. 1, 2 and 3. 6 of cycles 1-6
The cycle is the same as the operation of external memory access for fetching the instruction A in cycles 1 to 6 of FIG. 7 of the conventional example. The IF stage 106A increments the value held in the program counter 107, and fetches the instruction B from cycle 7 in the same manner as the fetching of the instruction A. Here, from the falling edge of the cycle 8 to the falling edge of the cycle 9, the flash signal 117
Is at the L level. At the falling edge of cycle 8, I
The F stage 106A is initialized, the address value of the branch destination is set in the program counter 107 from the E stage 106E via a path not shown, and the fetch of the instruction X at the branch destination address is started. From the rising edge to the rising edge of the cycle 10, the IF request signal 11
Set 6 to L level. However, since the external memory access for fetching the instruction B is in progress, the access unit 108 makes the start of the external memory access for fetching the instruction X wait until the end of the external memory access for fetching the instruction B.

Further, since the flash signal 117 changes to the L level from the falling edge of the cycle 8 to the falling edge of the cycle 9, the instruction fetch cancel signal 104 changes to the L level from the falling edge of the cycle 8 to the falling edge of the cycle 9. Become.
In the response circuit 102, when the DS signal 112 is at the L level, that is, the microprocessor 101 makes the memory 10
Since the instruction fetch cancel signal 104 becomes L level while accessing 5, the delay circuit 205 is initialized, and the DC signal 113 is the clock signal 109 of the clock signal 109 while the instruction fetch cancel signal 104 is L level. At the rising edge (at the rising edge of cycle 9), the L level is reached.
When detecting that the DC signal 113 has become L level, the access unit 108 reads the data on the external data bus 114 (in this case, valid data is not output) and discards it. The access unit 108 returns the DS signal 112 to the H level at the next rise of the clock signal 109 (rise of the cycle 10). The response circuit 102 is a DS
D at the rise of the signal 112 (rise of the cycle 10)
The C signal 113 is returned to the H level. Therefore, cycle 1
At the rising edge of 0, the external memory access for fetching the instruction B is forcibly terminated, and the external memory access for fetching the instruction X at the branch destination address is performed in the same operation as the fetch of the instruction A from the cycle 10. That is, FIG.
The external memory can be accessed three cycles earlier than the conventional example.

The operation when the preceding branch occurs while the microprocessor 101 is accessing the memory 105 for external memory for instruction fetch will be described with reference to FIGS. 1, 2 and 4. The 6 cycles of cycles 1 to 6 are the same as the external memory access operation for fetching the instruction A in cycles 1 to 6 of FIG. The IF stage 106A is
The value held in the program counter 107 is incremented, and the instruction B is fetched from cycle 7 in the same manner as the instruction A fetch. Here, it is assumed that the preceding branch signal 118 is at the L level from the fall of the cycle 8 to the fall of the cycle 9. At the falling edge of cycle 8, the IF stage 106
A is initialized and the address value of the branch destination is set to the D stage 10
Program counter 1 from 6B via a route not shown
Set to 07 to start fetching the instruction Y at the branch destination address.
The IF request signal 116 is set to the L level during the rising edge of. However, since the external memory access for fetching the instruction B is in progress, the access unit 108 makes the start of the external memory access for fetching the instruction Y wait until the external memory access for fetching the instruction B ends.

Since the preceding branch signal 118 has changed to the L level from the fall of the cycle 8 to the fall of the cycle 9, the instruction fetch cancel signal 104 is at the L level from the fall of the cycle 8 to the fall of the cycle 9. become. In the response circuit 102, when the DS signal 112 is at the L level, that is, the microprocessor 101 makes the memory 105
Since the instruction fetch cancel signal 104 has changed to the L level during access to the delay circuit 205, the delay circuit 205 is initialized and the DC signal 113 rises in the clock signal 109 while the instruction fetch cancel signal 104 is at the L level. At the (rising edge of cycle 9), the L level is reached. When detecting that the DC signal 113 has become L level, the access unit 108 reads the data on the external data bus 114 (in this case, valid data is not output) and discards it. The access unit 108 returns the DS signal 112 to the H level at the next rise of the clock signal 109 (rise of the cycle 10). The response circuit 102 is a DS
D at the rise of the signal 112 (rise of the cycle 10)
The C signal 113 is returned to the H level. Therefore, cycle 1
At the rising edge of 0, the external memory access for fetching the instruction B is forcibly ended, and the external memory access for fetching the instruction Y at the branch destination address is performed in the same operation as the fetch of the instruction A from the cycle 10. That is, FIG.
The external memory can be accessed three cycles earlier than the conventional example.

[0034]

As described above, according to the present invention, the instruction fetch cancel signal indicating that the external memory access is invalid is output when either the flush signal or the preceding branch signal is detected. Since it was configured to
When a pipeline flush or a preceding branch occurs, this instruction fetch cancel signal is used to externally indicate that the external memory access of the instruction fetch currently being accessed is invalid, and the external memory access of this instruction fetch is forced. Can be terminated. Therefore, it is possible to reduce the waiting time for the external memory access of the next valid instruction fetch due to the wasteful external memory access of the instruction fetch, which has the effect of increasing the program execution speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microprocessor according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of a response circuit.

FIG. 3 is a timing chart for explaining an operation in the case where a pipeline flush occurs while a microprocessor is accessing an external memory for fetching an instruction from a memory.

FIG. 4 is a timing chart for explaining an operation in the case where a preceding branch occurs while the microprocessor is performing external memory access for instruction fetch to the memory.

FIG. 5 is a block diagram showing a conventional microprocessor.

FIG. 6 is a configuration diagram showing an example of a conventional response circuit.

FIG. 7 is a timing chart for explaining an operation in the case where a pipeline flush occurs while a conventional microprocessor is accessing an external memory for instruction fetch to a memory.

FIG. 8 is a timing chart for explaining an operation in the case where a preceding branch occurs while a conventional microprocessor is accessing an external memory for instruction fetch to a memory.

[Explanation of symbols]

 101 Microprocessor 103 Logic Gate (Detecting Means) 104 Instruction Fetch Cancel Signal 106 Pipeline Processing Mechanism 117 Pipeline Flush Signal 118 Preceding Branch Signal

Claims (1)

[Claims] 1. A microprocessor having a pipeline processing mechanism for accessing an external memory for instruction fetch, wherein a pipeline flush signal output when the pipeline processing mechanism executes a branch instruction and a preceding branch instruction are decoded. And a preceding branch signal that is output at a time, and when either one of the signals is detected, a detection unit that outputs an instruction fetch cancel signal for indicating that the external memory access currently being executed is invalid A microprocessor provided with.