JPH0212429A - Information processor with function coping with delayed jump - Google Patents

Abstract

PURPOSE:To execute a conventional code as well as a code generated for delayed jump by stopping update of a program counter at the time of a conditional jump instruction. CONSTITUTION:When a jump instruction or a conditional jump instruction is executed in the NOP insertion mode, a jump instruction detection signal 14 is true. When a mode bit indicates the NOP insertion mode at this time, the input to an instruction register (IR) 22 is switched from an instruction buffer (IRB) 20 to a NOP code generating circuit 21. The input to a program counter 23 is not the output of a normal incrementer (INC) 24 and the current value of the program counter 23 is fed back. Consequently, not a prefetched instruction but the NOP code from a NOP code generating circuit 21 is loaded to the IR 22 by the next clock, and the NOP instruction is inserted. Thus, the conventional code as well as the code generated for delayed jump is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an information processing device (hereinafter referred to as a computer) having a delayed jump function.

(Prior Art) Column a in FIG. 5 shows an example of a machine language instruction sequence in mnemonic code. In a pipelined computer, 10
Fetch the instruction word at address 101 while executing address 0, and
The speed is increased by fetching the instruction word at address 102 while the instruction word at address 01 is being executed. Since the instruction at address 102 is a jump instruction, the pipeline mechanism does not work effectively with a simple briefetch. There are two methods to avoid disrupting pipeline processing as much as possible.

The first is 103, which has been briefetched during the execution of a jump instruction.
This is a method of designing hardware such that the instruction at address 105 is discarded and the instruction at address 105, which is the jump destination, is fetched again. The second is delayed jump. This is the instruction following the jump instruction (in this example, ADDA at address 103).
, B) is always executed before the jump instruction at address 102 is executed. The first method is a conventional method, but the hardware, mainly the control system, becomes complicated, which tends to limit speeding up of machine cycles. The second method is to leave the control related to jump instructions to software and simplify the hardware.
It has been attracting attention in recent years. In the delayed jump described below regarding this method, the execution of addresses 102 and 103 will overlap if the code in column a of FIG. 5 is used as is. Therefore, a NOP instruction is inserted immediately after the jump instruction (column b in FIG. 5). FIG. 6 shows the execution progress of the instruction sequence in column b of FIG. 5 for each machine cycle. Each instruction is fetched from memory (IF) by the clock in FIG.
The instruction is decoded (ID) and executed (E
X) be done. For the jump instruction at address 102, the branch destination address is calculated during execution of clock 4 and is loaded into the program counter. Therefore, instruction fetch from the branch destination address cannot be started until clock 5. The instruction at address 103 is executed at clock 5 before the jump destination is determined, but since it is a NOP, there is no problem. Although this allows correct results to be obtained, performance deteriorates because a NOP instruction is executed for each jump instruction. Therefore, when the instruction immediately before the jump is unrelated to the jump condition, the instructions are replaced as shown in column C of FIG. 5, and the NOP instruction is deleted.

FIG. 7 shows the execution progress for each machine cycle of the instruction sequence in column C of FIG. 5, and it shows that correct results are obtained quickly. As described above, if a compiler is prepared that has the function of generating code into which a NOP instruction is inserted and, if possible, replacing the jump instruction with the instruction immediately before it, it is possible to support the delayed jump mechanism. However, there was a problem in that the conventional object code itself (column a in FIG. 5) could not be executed. FIG. 8 shows a case where this is intentionally executed. The correct result is z=(A+1), but in this case it becomes Z - (A + B +l), which is an incorrect result.

(Problems to be Solved by the Invention) As described above, computers with a delayed jump mechanism have the drawback that conventional object code cannot be executed as is. The present invention aims to solve this problem and provide a computer that can execute both conventional code and code generated for delayed jumps.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problem, the present invention has a mode bit indicating whether the NOP instruction insertion mode is valid or invalid and a NOP code generation circuit, and has a NOP code generation circuit when a jump instruction is executed. If the mode bit is valid, a NOP instruction is inserted into the instruction string.

(Function) With this configuration, conventional code can be executed as is, and code generated for delayed jumps can also be executed.

(Example) The present invention will be explained below.

FIG. 1 shows an example of the internal configuration of a computer.

All registers in FIG. 1 are edge triggered.

The drive mode bit (10) in the control register is set to “
Whether to insert a NOP instruction immediately after executing a jump instruction
stipulates. A mode in which a NOP instruction is not inserted is called a "normal mode", and a mode in which a NOP instruction is inserted is called a "NOP insertion mode". In the "normal mode", the instruction code currently being executed is held in the instruction register (221R), and the next instruction that has been pre-fetched is held in the instruction buffer (201RB). The operation code section of the instruction is decoded by the control section (25), and control signals for each section are generated. When a jump instruction or conditional jump instruction is executed in the "NOP insertion mode", the jump instruction detection signal (14) becomes true. At this time, if the mode bit is "NOP insertion mode", I
The input of R is switched to the NOP code generation circuit instead of the IRB. Furthermore, the current PC value is fed back to the program counter, rather than the normal incrementer (INC) output.

As a result, at the next clock, the NOP code is loaded into the IH from the NOP code generation circuit (21) instead of the brifetched instruction. In other words, a NOP instruction has been inserted. The jump signal is the program counter (2
3PC) increment is also suppressed. This is to prevent the PC from advancing too much when executing the inserted NOP instruction.

FIG. 2 shows the execution progress of the unconditional jump command. At clock 4, the jump destination address is calculated, and at clock 5, the PC
loaded into. A NOP is internally generated at clock 5 due to the jump instruction detection signal, and the jump destination instruction is fetched at clock 5 and executed at clock 6.

Next, we will discuss conditional jump instructions. FIG. 3 shows the progress of execution when a conditional jump instruction (Jun+p Minus in this example) is satisfied. The jump destination address is calculated at clock 4 and loaded into the PC at clock 5. A NOP is internally generated at clock 5 due to the jump instruction detection signal, and the jump destination instruction is fetched at clock 5 and executed at clock 6. FIG. 4 shows the execution progress of a conditional jump instruction (Jump Minus in this example) when the condition is not satisfied.

Due to the jump instruction detection signal, the PC holds address 203 for clocks 4 to 5. As a result, the next instruction after the jump instruction is correctly fetched from address 203 at clock 5.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a computer that can execute both conventional codes and codes generated for delayed jumps by switching the mode bits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a computer according to an embodiment of the present invention, FIG. 2 is a diagram showing the execution progress of an unconditional jump instruction in NOP insertion mode, and FIG. 3 is a diagram showing the execution progress of an unconditional jump instruction in NOP insertion mode.
Figure 4 shows the execution progress when the conditional jump is established.
FIG. 8 is a diagram showing the progress of instruction execution for each machine cycle in the P insertion mode. 10... Running mode bit 11... Flag 12... Arithmetic logic operation unit 13...
・Register file 14...Jump instruction detection signal 20...
・Instruction buffer (IRB) 21...NOP code generation circuit 22...Instruction register (IR) 23
...Program counter (PC) 24...
・・Incrementer (INC) 25 ・・・Control unit

Claims (2)

[Claims] (1) In an information processing device that has an instruction in which the value of the program counter can change discontinuously and has a delayed jump mechanism that executes the instruction at the next address of the previous instruction and then executes the instruction at the jump destination address, at least A mode bit is provided to indicate "normal mode" and "NOP insertion mode",
In normal mode, delayed jump operation is performed and NOP
In the insert mode, a NOP instruction is generated inside the computer and inserted into the instruction stream immediately after the jump instruction is executed, and the program counter is stopped from being updated at least when a conditional jump instruction is executed. Functional information processing device. (2) The delayed program according to claim 1, wherein the instruction in which the value of the previous program counter can change discontinuously includes at least one of an unconditional jump instruction, a conditional jump instruction, a call instruction, and a return instruction. Information processing device with jump support function.