JP3211791B2 - Loop processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a loop processing method, and more particularly to a loop processing method having a condition execution function.

[0002]

2. Description of the Related Art Since a signal processing application often executes the same processing repeatedly, a general DSP (digital signal processor) has a built-in mechanism for speeding up loop processing. Conventionally, in this type of loop processing method, a hardware circuit dedicated to loop processing is provided and loop processing is executed at high speed without overhead, as shown in, for example, JP-A-3-201131.

FIG. 5 is a block diagram showing a configuration of a conventional loop processing system. In FIG. 5, the loop control unit 50
Counts down the number of remaining loops stored in the loop count register 52 each time the loop reaches the end of the loop in the loop processing program.
If the contents of the loop count register 52 are equal to 0, the program execution is controlled so that the processing is terminated without branching when the contents of the loop count register 52 are equal to 0.

The operation instructions and data transfer instructions described in the loop processing program are executed in the product-sum operation unit 54 and the load / store units 56 and 58. Reference numeral 60 denotes load / store units 56 and 58.
Is a data memory that temporarily stores data output from the CPU and transfers data to a register file 62 described later. The register memory 62 reads an instruction execution unit input and writes an execution result. .

FIG. 6 is a diagram showing an assembler program when a loop instruction is implemented by applying a conventional loop processing method to a DSP and an FIR filter is realized by software using the loop instruction. FIR
The filter consists of typical loop processing that can be accelerated by a loop instruction. Note that the symbol ":" in FIG. 6 and the number described on the left side thereof indicate the line number, and do not indicate the contents of the program itself.

In FIG. 6, "LOOP" described on the second line
N-1 ”is the symbol“ 」” described in the second line and the fourth
The instruction sequence between the symbols "@"
This is an instruction to execute once. Other, third
“Rk = Rk + Ri * R” described in the line and the fifth line
"j" is an instruction for performing a product-sum operation on the contents of the registers Rj, Ri, and Rk, and "Rk = * Ri ++" is a register R
The data in the memory having the contents of i as an address is stored in a register R
k is an instruction for incrementing the contents of Ri after loading into register k. "* Ri ++ = Rk" is an instruction for incrementing the contents of Ri after storing the contents of register Rk in a memory location having the contents of register Ri as an address. is there.

The above "k", "i", and "j" represent register numbers, and the number of execution cycles of these instructions is one. Also, a plurality of instructions described in each line are executed in the same cycle, and the symbol “;” means the end of each line. By using loop instructions, it is possible to create a loop processing program with a small number of instructions (ie, a small code size).

[0008]

The conventional DS
In P, the execution result of a certain instruction could be used in the next cycle, but it may not be available in the next cycle by increasing the operating frequency.
For example, assume that one must wait four cycles before the result of a load instruction becomes available. In this case, a program corresponding to the program shown in FIG. 6 is as shown in FIG.

FIG. 7 shows a conventional loop processing method.
FIG. 14 is a diagram illustrating an FIR filter realization program that causes a problem when an SP loop instruction is implemented. In FIG.
Since the product-sum operation instruction shown in the fifth line must wait for the result of the load instruction in the fifth line executed during the previous loop iteration, a NOP (no operation) is included in the loop processing body. , A plurality of cycles are inserted, and the efficiency of program execution deteriorates.

It is fatal for a DSP requiring real-time processing to degrade program execution performance due to a useless cycle in which no instruction is executed. As shown in FIG.
The above problem can be improved by unrolling a part of the loop. FIG. 8 is a diagram showing a program obtained by improving an FIR filter realization program which becomes a problem when a loop instruction of a DSP is implemented using a conventional loop processing method.

As shown in the sixth line in FIG. 8, while waiting for the result of the load instruction, another instruction sequence (the seventh, eighth, and ninth lines) obtained by loop unrolling is executed. This makes it possible to execute a program without useless cycles. However, although the execution performance of the program is improved, there is a disadvantage that the number of instructions in the program is increased. As described above, in the conventional loop processing method, there is a problem that the code size of the loop processing program is increased in order to prevent the execution performance of the program from deteriorating due to the increase in the number of cycles required for executing the load instruction and the like.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a loop processing method for suppressing an increase in code size as the number of cycles required for executing an instruction increases. .

[0013]

According to the present invention, a pre-loop processing in a loop processing program is performed by conditionally executing an instruction sequence (lines 6, 7, 8, and 9 in FIG. 8) corresponding to the main body of the loop processing. The number of instructions in the section (lines 1, 2, 3, and 4 in FIG. 8) and the post-processing section (lines 11, 12, 13, and 14 in FIG. 8) is reduced.

More specifically, a loop control means (loop control unit 1) for instructing information on the number of loop repetitions.
2) and condition instructing means (condition code registers 16, 18, and 20) for designating a condition for condition execution according to the information on the number of times of loop repetition ; Writing control means (condition determination control unit 14) for controlling writing of the calculation result to the storage means based on the calculation result. Further, the present invention, the loop control means, the finger
In parallel with the above-mentioned operation, loop processing execution control is performed. Further, the present invention is characterized in that the information on the number of repetitions of the loop is information indicating that the information is any of the first time, the last time, or another state of the loop. I do.

As described above, the provision of the means for conditionally executing the instruction sequence in the loop processing body according to the number of iterations of the loop allows the partial instruction sequence in the loop processing body to be firstly executed in the loop for the first time. And in the last round, another part of the instruction sequence in the same loop processing body can be executed as a post-processing unit. As a result, although the instruction sequence of the loop processing body is still required, the instruction sequence of the pre-processing unit and the post-processing unit is not required, so that the code size of the loop processing program is reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a loop processing method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a loop processing method according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a register for loop count, which stores the remaining number of loops. Reference numeral 12 denotes a loop control unit, which counts down the remaining number of loops stored in the loop count register 10 each time the loop reaches the end of the loop in the loop processing program. When the content of the loop count register 10 is equal to 0, the execution of the program is controlled so that the loop processing is terminated without branching. The loop controller 12 controls the loop and outputs a control signal 12a indicating that the loop is the first time, the last time, or another repetition.

The condition determination control unit 14 loops whether or not to write the execution result of the instruction execution unit including the product-sum operation unit 22 and load / store units 24 and 26 to a register file 30 or data memory 28 to be described later. Control is performed based on the contents of the count register 10.
The above-described instruction execution unit includes condition code registers 16 to 20 that hold condition codes specified in each instruction code, and performs calculations and data transfer. The data memory 28 transfers data to and from the register file 30. The register file 30 is used to read an instruction execution unit input and write an execution result.

The above-described loop processing method according to the embodiment of the present invention is different from the conventional loop processing method shown in FIG. 5 in that the structure shown in FIG. Condition determination control unit 14, Condition code registers 16-2
0, and their associated signal lines 12a, 16b, 18
b, 20b, 14a, 14b, and 14c are newly added points. An ordinary DSP has a configuration in which an instruction fetch unit and an instruction decoder are added before this method, and signal lines 10a, 16a, 18a, and 20a are outputs from the instruction decoder.

The condition determination control unit 14 includes a control signal 12a for instructing a state of the first time, the last time of the loop, or another repetition state, and signal lines 16b, 18
b, 20b via the condition code registers 16, 18,
20 is input, and each instruction execution result 22a, 24a, 2 in the register file 30 or the data memory 28 is input.
Signals for controlling the writing of 4b, 26a, 26b, 28a, 28b are output via signal lines 14a, 14b, 14c.

The loop control unit 12 receives the number of remaining loops, which is held in the loop count register 10 and is output via the signal line 10b, and controls the loop processing based on this value. The value obtained by subtracting 1 from the value is output via the signal line 10c. In addition, the first time of the loop,
A control signal indicating that the state is the last one or another state at the time of repetition is output via the signal line 12a.

The loop count register 10 receives, via a signal line 10a, the number of loops obtained by decoding a loop instruction before starting execution of loop processing. During the execution of the loop processing, the value of the remaining number of loops counted down is transmitted from the loop control unit 12 to the signal line 10.
c, and the held content is output to the loop control unit 12 via the signal line 10b.

The condition codes obtained by decoding the instruction codes are input to the condition code registers 16, 18, and 20 via signal lines 16a, 18a, and 20a. The condition code registers 16, 18, and 20 hold them and output them via signal lines 16b, 18b, and 20b. The condition codes to be held in the condition code registers 16, 18, and 20 are information specified by the programmer in the program, and are described in each instruction code.

According to this condition code, each instruction: 1. An instruction that is not executed at the first and last times of the loop, but is always executed at other times. 2. An instruction that is not executed at the last time of the loop, but is always executed at other times. Indicates that it is one of the instructions that are not executed at the beginning of the loop, but are always executed at other iterations.

The outputs 30a, 30b, and 30c of the register file 30 are input as operation operands to the product-sum operation unit 22, and the result of the product-sum operation for these operands is output via a signal line 22a. The load / store unit 24 has an output 30 of the register file 30.
d and 30e are input as a memory address and store data, respectively, and the input address and store data are input to the data memory
8 is output. At the same time, the value obtained by incrementing the address is output to the register file 30 via the signal line 24a.

Outputs 30f and 30g of the register file 30 are input to the load / store unit 26 as memory addresses and store data, respectively, and the input addresses and store data are applied to signal lines 26c and 2 respectively.
The data is output to the data memory 28 via 6b. at the same time,
The value obtained by incrementing the address is output to the register file 30 via the signal line 26a.

The data memory 28 stores store data 24b output from the load / store units 24 and 26,
A control signal instructing whether or not writing 26b to the data memory 28 is input via the signal lines 14b and 14c. At the time of the store operation, the signal line 24 is set at a position in the memory indicated by the memory address output via the signal line 24a in accordance with the availability of the availability signal input via the signal line 14b.
The store data output via b is written. Similarly, the propriety signal output via the signal line 14c is also output via the signal line 26b to the position in the memory indicated by the memory address output via the signal line 26c, depending on the propriety of this signal. Store data is written. On the other hand, during the load operation, the signal lines 28a,
The load data is read out via the respective terminals 28b.

The register file 30 includes a signal line 30
a, an operation input output to the product-sum operation unit 22 via the a, 30b, 30c, a memory address and store data output to the load / store unit 24 via the signal lines 30d, 30e, and a signal Lines 30f, 30
The memory address and the store data output to the load / store unit 26 via g are read. Then, a write enable / disable signal is input via the signal lines 14a, 14b, and 14c, and the operation result of the product-sum operation unit 22, the load data, and the updated address are written according to the enable / disable of each signal.

Next, the operation of this embodiment will be described. First, the condition codes held in the condition code registers 16, 18, and 20 are stored in signal lines 16b and 18 respectively.
b and 20b are input to the condition determination control unit 14.
At the same time, the first time, the last time,
Alternatively, a control signal indicating any state at the time of repetition is also transmitted to the condition determination control unit 1 via the signal line 12a.
4 is input.

The loop control unit 12 controls the loop based on the number of remaining loops output via the signal line 10b, as in the conventional loop processing method. At the same time, at the start of the loop processing, a signal indicating the first time of the loop is output via the signal line 12a, and at the last time of the loop processing, a signal indicating the last time is output via the signal line 12a. At the time of other loop repetition, a signal indicating that it is neither the first time nor the last time is output via the signal line 12a.

In the condition determination control unit 14, the signal lines 16b,
Based on the condition code input via the signal lines 18b and 20b and the control signal output via the signal line 12a, the instruction execution unit ( It is determined whether or not the execution result of the product-sum operation unit 22, the load / store units 24, 26) can be written to the register file 30 or the data memory 28.

Then, the write enable / disable information corresponding to each of the instruction execution units (the product-sum operation unit 22, the load / store units 24, 26) is transmitted to the signal lines 14a, 14a.
The data is input to the register file 30 and the data memory 28 via b and 14c. The signal line 16b and the signal line 1
4a corresponds to the product-sum operation unit 22, and the signal line 18b,
14b corresponds to the load / store unit 24, and the signal lines 20b and 14c correspond to the load / store unit 26.

In parallel with these operations, an instruction execution unit (product-sum operation unit 22, load / store unit 2)
In (4, 26), the product-sum operation and the load / store are executed in parallel. The product-sum operation unit 22 performs a product-sum operation on three data input from the register file 30 via the signal lines 30a, 30b, and 30c. If the control signal 14a from the condition determination control unit 14 is writable, the operation result output via the signal line 22a is written to the register file 30, otherwise it is not written.

During the load operation, the load / store unit 22 transfers the memory address input from the register file 30 via the signal line 30d to the data memory 28 via the signal line 24c. Then, the data in the memory indicated by this address is transferred to the signal line 28a.
Is loaded from the data memory 28 to the register file 30 via the. If the control signal output from the condition determination control unit 14 via the signal line 14a is writable, the load data 28a is written to the register file 30, otherwise it is not written.

On the other hand, at the time of the store operation, the memory address and store data input from the register file 30 to the load / store unit 24 via the signal lines 30e and 30f are transferred to the data memory 2 via the signal lines 24c and 24b.
8 is transferred. If the signal output via the signal line 14b is writable, the store data output via the signal line 24b is written to a location in the memory indicated by the address output via the signal line 24a, otherwise. If not written.

In both cases of load and store, in parallel with these processes, the address used for the memory access is incremented and then output via the signal line 24a and output via the signal line 14b. If the signal is writable, the content output via signal line 24a is written to register file 30, otherwise it is not written.

The load / store unit 26 transfers a memory address input from the register file 30 via the signal line 30f to the data memory 28 via the signal line 26c during a load operation. Then, data in the data memory 28 indicated by the address output via the signal line 26c is loaded from the data memory 28 to the register file 30 via the signal line 28b.

Control signal 14c from condition determination control unit 14
Is writable, the load data output via the signal line 28b is written to the register file 30, otherwise it is not written. On the other hand, during store operation,
Memory addresses and store data input from the register file 30 to the load / store unit 26 via the signal lines 30f and 30g are transferred to the data memory 28 via the signal lines 26c and 26b.

If the signal output via the signal line 14c is writable, the store data output via the signal line 26b is written to the data memory 28, otherwise it is not written. In both cases of load and store, in parallel with these processes, the address used for memory access is incremented and then output via the signal line 26a and the signal output via the signal line 14c is written. If yes, the content output via signal line 26a is written to register file 30, otherwise it is not written.

Next, the present embodiment will be described more specifically. Now, the loop controller 12 shown in FIG. 1 outputs “01” via the signal line 12a at the first time of the loop, outputs “10” at the last time of the loop, and outputs “10” at the time of the other iterations. 00 ”is output.

FIG. 2 is a diagram showing a field configuration in the instruction code. In the example shown in FIG. 2, bits 15 and 14 of the 16-bit length field have condition code f
It is 1 and bits 13 to 0 of the field are operation codes f2 for specifying an instruction-specific operation. When the condition code f1 is “00”, it means that the instruction including the present condition code is not executed at the first and last times of the loop, and is always executed at other times.

When the condition code f1 is "01", it means that the instruction including the present condition code is not executed at the last time of the loop, and is always executed at other times. Further, when the condition code f1 is “10”, it means that the instruction including the present condition code is not executed at the first time of the loop, and is always executed at other times.

FIG. 3 is a block diagram showing the configuration of the condition determination control unit 14 in FIG. The 2-bit signal output from the loop control unit 12 via the signal line 12a and the signal line 16
b, 18b, and 20b, the 2-bit condition code is input to the condition determination control unit 14, and the determination circuit 4
Whether write to the register is possible or not is determined by 0, 42, and 44, and the determination result is output via the signal lines 14a, 14b, and 14c.

When the signal input via the signal line 12a is "00" (that is, when the signal is neither the first time nor the last time of the loop), the determination circuit 40 outputs "1" which means that writing is possible, to the signal line Output via 14a. Signal line 12
When the signal input via signal line a is "01" (i.e., the first time of the loop), the condition code input via signal line 16b matches the signal input via signal line 12a (i.e., , When the condition code input via the signal line 16b is “01”, which is an instruction to be executed at the first time of the loop), “1” via the signal line 14a
Is output, and when they do not match, "0" which means that writing is disabled is output.

When the signal input through the signal line 12a is "10" (ie, the last time of the loop), the signal line 1
When the condition code input via the signal line 6b matches the signal input via the signal line 12a (that is, the condition code input via the signal line 16b is "10" and "1" is output via the signal line 14a only when the instruction is to be executed (if the instruction is to be executed). The determination circuits 42 and 44 also perform the same processing on the condition codes input via the signal lines 18b and 20b, respectively.
A write enable / disable signal is output via the signal lines 14b and 14c.

FIG. 4 shows the implementation of a loop instruction in a DSP based on the present embodiment, and FIG.
FIG. 6 is a diagram obtained by rewriting the assembler program of FIG. Of the instruction sequence in the loop, the instruction with the condition code "01" is prefixed with the symbol "@", and the instruction with the condition code "10" is prefixed with the symbol "@", and these symbols are designated by the programmer. . FIG.
Since the program shown in FIG. 8 does not have the pre-loop processing unit and the post-loop processing unit, the number of instructions is almost halved as compared with the program shown in FIG.

The embodiment of the present invention has been described above. In the present embodiment, the case where the number of instruction execution units is 3 has been described. However, it is apparent that the present invention can be applied to other cases. In addition, it is apparent that the present invention can be implemented similarly to the present invention not only in the first or last loop, but also in the case of executing the condition every other time such as the second and third times. Further, it is apparent that the present invention can be realized in the same manner as in the present invention even if various modifications are made to the condition designation method and designation contents in the condition code.

[0047]

As described above, according to the present invention, the instruction sequence for the loop pre-processing unit and the instruction sequence for the post-processing unit can be executed by conditionally executing the instruction sequence in the loop based on the number of loop repetitions. Since it becomes unnecessary, there is an effect that the code size in the loop processing program can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a loop processing method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a field configuration in an instruction code.

FIG. 3 is a block diagram showing a configuration of a condition determination control unit 14 in FIG.

FIG. 4 is a diagram in which a loop instruction in a DSP is implemented based on the present embodiment, and the assembler program of FIG. 6 is rewritten using the loop instruction.

FIG. 5 is a block diagram showing a configuration of a conventional loop processing method.

FIG. 6 is a diagram illustrating an assembler program when a loop instruction is implemented by applying a conventional loop processing method to a DSP, and an FIR filter is realized by software using the loop instruction.

FIG. 7 is a diagram showing an FIR filter realization program which becomes a problem when a DSP loop instruction is implemented using a conventional loop processing method.

FIG. 8 is a diagram showing a program obtained by improving an FIR filter realization program which causes a problem when a DSP loop instruction is implemented using a conventional loop processing method.

[Explanation of symbols]

12 loop control unit ( loop control unit ) 14 condition determination control unit ( write control unit) 16, 18, 20 condition code register (condition instruction unit)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (3)

(57) [Claims] And 1. A loop control means for indicating information relating to the number of iterations of the loop, the condition instructing means for specifying a condition for conditional execution in accordance with the information about the number of iterations of the loop, information about the number of iterations of the loop And a control program for controlling the writing of the operation result to the storage means based on the condition .
A loop processing method comprising: a writing control unit. 2. The loop processing method according to claim 1, wherein said loop control means performs loop processing execution control in parallel with said instruction . 3. The loop according to claim 1, wherein the information on the number of times the loop is repeated is information indicating that the state is any of the first time, the last time, and other times of the loop. Processing method.