JP2880459B2 - Variable word length VLIW instruction processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an improvement in a variable word length VLIW instruction processor.

[0002]

2. Description of the Related Art Conventionally, as a method for improving the performance of a processor, there is a parallel instruction execution method for simultaneously executing two or more instructions by parallel processing.

For example, US Pat. No. 4,833,599 discloses a VLIW (very
A processor is shown that uses a long instruction word (Long Instruction Word) to execute multiple instructions simultaneously in parallel. In this processor, the number of instructions included in one VLIW instruction can be 20 or more, but the VLIW instruction word length is fixed.

However, in the conventional VLIW instruction processor, since the VLIW instruction word length is fixed, when a large number of instructions close to the maximum number of instructions that can be executed in parallel are executed, extremely high performance is obtained. As shown in the figure, when the number of instructions to be executed in parallel is small, the instruction instruction information included in the VLIW instruction has a large number of “NOP” (no execution). Although the instruction of "NOP" is an instruction, it has a drawback that it is extremely useless from the viewpoint of effective use of the instruction memory.

On the other hand, US Pat. No. 5,241,636 discloses a processor having two execution modes, a mode for executing one instruction and a mode for executing two instructions simultaneously in parallel. In this US patent, the execution mode is switched by designating a predetermined field included in the instruction.

VL using the field in the above instruction
"MICROPROCESS" as an IW instruction processor
SOR REPORT ”, DECEMBER 5,19
94, pp. 12-15 proposes a processor in which a field indicating the number of instructions is provided in a VLIW instruction to make the VLIW instruction word length variable.

[0007]

However, in the above-mentioned VLIW instruction processor, the VLIW instruction word length is variable, so that the instruction memory can be used effectively and
Although it has the advantage of enabling the simultaneous execution of a large number of instructions, it is necessary to provide a field indicating the number of instructions in the VLIW instruction. The instruction format is different from the instruction without the instruction, and as a result, it is difficult to execute the object program created and compiled for the conventional processor, and to maintain the compatibility of the object program with the conventional processor. It was difficult.

The present invention has been made in view of the above problems, and has as its object
An object of the present invention is to provide a VLIW instruction processor that can effectively use an instruction memory, can execute a large number of instructions simultaneously, and can execute an object program of a conventional processor.

Still another object of the present invention is to provide a case where the maximum number of instructions that can be simultaneously executed by a processor is different between different models of a VLIW instruction processor, or that the number of instructions included in a VLIW instruction can be simultaneously executed by the processor. An object of the present invention is to provide a VLIW processor that can always execute a VLIW instruction even when the number of instructions is larger than the maximum number of instructions.

[0010]

In order to achieve the above object, the present invention provides, in summary, a VLIW instruction word length register for storing a VLIW instruction word length, or the number of instructions for storing the number of instructions included in the VLIW instruction. Provide a register. Further, in the present invention, the number of instructions included in the VLIW instruction is divided by the number of execution units (the maximum number of instructions that can be executed in parallel by the processor), and its quotient m and remainder δ are obtained. After repeating the number of times m, the number of instructions equal to the remainder δ is executed.

In other words, the variable word length VLIW instruction processor according to the first aspect of the present invention comprises a plurality of execution units for executing instructions, a VLIW instruction word length register for storing the VLIW instruction word length, and a VLIW instruction word length. VL containing instructions
Upon receiving the IW instruction, the VLIW instruction word length in the VLIW instruction word length register rewrites the VLIW instruction word length of the VLIW instruction word length register, and based on the VLIW instruction word length stored in the VLIW instruction word length register. And an instruction control unit for controlling parallel execution of instructions by all or some of the execution units.

According to a second aspect of the present invention, in the variable word length VLIW instruction processor according to the first aspect, the VL
The VLIW instruction including the instruction of the word length of the IW instruction
It is characterized in that a word length rewriting instruction for rewriting the VLIW instruction word length is included in a plurality of instructions constituting the W instruction.

According to a third aspect of the present invention, in the variable word length VLIW instruction processor according to the second aspect, the word length rewriting instruction is executed by any one of the plurality of execution units. Features.

According to a fourth aspect of the present invention, in the variable word length VLIW instruction processor according to the first aspect, the VL
The VLIW instruction including the instruction of the IW instruction word length is a VLIW instruction having a field indicating the VLIW instruction word length.

According to a fifth aspect of the present invention, in the variable word length VLIW instruction processor according to the fourth aspect, the VL
A dedicated execution unit for rewriting the VLIW instruction word length stored in the IW instruction word length register;
The VLIW instruction word length indicated in the field in the instruction is decoded, and the VLIW instruction word length stored in the VLIW instruction word length register is read.
Decoding and control means for controlling the execution unit dedicated to rewriting so as to rewrite the LIW instruction word length to the decoded VLIW instruction word length is additionally provided.

According to a sixth aspect of the present invention, in the variable word length VLIW instruction processor according to the first aspect, one V
The LIW instruction comprises a plurality of instructions, the plurality of instructions having the same predetermined bit length, and the instruction control unit controlling the VLIW instruction word length stored in the VLIW instruction word length register.
There is provided an instruction number calculating means for calculating the number of instructions included in one VLIW instruction by dividing the LIW instruction word length by the predetermined bit length.

According to a seventh aspect of the present invention, in the variable word length VLIW instruction processor according to the first aspect, the instruction control unit partitions a plurality of instructions constituting one VLIW instruction into a plurality of instruction groups. It is characterized by comprising a control means for executing instructions in parallel for each instruction group.

According to an eighth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh aspect, the control means sets a number of instructions constituting one VLIW instruction as a dividend and a number of the execution units as a divisor. And dividing means for obtaining the quotient and its remainder, and when the quotient is not “0”,
Using the plurality of execution units, the simultaneous parallel execution of the number of instructions equal to the number is repeated by the number of quotients, and thereafter, if the remainder is not "0", the number of executions equal to the number of the remainder is repeated. And an instruction control means for executing instructions in parallel in a parallel manner when the quotient is "0", using an execution unit having a number equal to the number of the remainders. It is characterized by having.

According to a ninth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, the VLIW instruction having a word length rewriting instruction is one of an instruction group executed at the last time. Contains the word length rewriting instruction.

According to a tenth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, the VLIW instruction having a word length rewriting instruction is:
The word length rewriting instruction is included in a group of instructions executed immediately before the last round.

According to an eleventh aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, the VLIW instruction having a word length rewriting instruction is:
The word length rewriting instruction is included in a group of instructions executed two times before the last round.

The twelfth aspect of the present invention provides the ninth aspect,
The variable word length VLIW instruction processor according to claim 10 or 11, wherein the instruction control unit is a VLIW instruction processor.
The first execution is performed in a VLIW instruction following the VLIW instruction including the word length rewriting instruction according to the position of the instruction group including the word length rewriting instruction in a plurality of instruction groups forming the W instruction. It is characterized by having instruction fetch pipeline control means for inhibiting instruction fetch.

According to a thirteenth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, a certain VLIW instruction includes a branch instruction in an instruction group executed at the last time. It is characterized by being performed.

According to a fourteenth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, a certain VLIW instruction includes an instruction group to be executed immediately before the last one. It is characterized in that a branch instruction is included therein.

According to a fifteenth aspect of the present invention, in the variable word length VLIW instruction processor according to the seventh or eighth aspect, a certain VLIW instruction includes an instruction group executed two times before the last instruction. It is characterized in that a branch instruction is included therein.

The invention according to claim 16 is the invention according to claim 1.
3. The variable word length VLIW according to claim 14 or claim 15.
In the instruction processor, the instruction control unit includes:
Execution of an instruction to be executed for the first time in a VLIW instruction following the VLIW instruction including the branch instruction in accordance with a position of the instruction group including the branch instruction in a plurality of instruction groups constituting the LIW instruction; It is characterized by having an execution pipeline control means and a write pipeline control means for canceling each write operation.

The invention according to claim 17 is the invention according to claim 16.
In the variable word length VLIW instruction processor described above, the instruction control unit further includes a branch destination address holding register for storing a branch destination address of a branch instruction included in the VLIW instruction.

The invention according to claim 18 is the variable word length VLIW instruction processor according to claim 1, wherein the VLI
The VLIW instruction word length stored in the W instruction word length register is:
It is characterized by being initialized when power is turned on and when the system is reset.

According to a nineteenth aspect of the present invention, in the variable word length VLIW instruction processor according to the first aspect, the VLI
The VLIW instruction word length stored in the W instruction word length register is:
When executing an object program for a processor that executes a VLIW instruction having the same instruction format and a different number of execution units from the VLIW instruction, the VLIW instruction executed immediately before the head of the object program is executed. It is characterized by being rewritten by a word length rewriting instruction included in the instruction.

The variable word length VLIW of the invention according to claim 20
The instruction processor receives a plurality of execution units that execute instructions, an instruction number register that stores the number of instructions included in the VLIW, and a VLIW instruction that includes an instruction of the number of instructions, and receives the VLIW instruction based on the number of instructions in the VLIW instruction. An instruction control unit that rewrites the number of instructions in the instruction number register and controls parallel execution of instructions by all or some of the plurality of execution units based on the number of instructions stored in the instruction number register. It is characterized by.

The invention according to claim 21 is the invention according to claim 20.
In the variable word length VLIW instruction processor described above, the VLIW instruction including the instruction of the number of instructions includes an instruction number rewriting instruction for rewriting the number of instructions among a plurality of instructions constituting the VLIW instruction.

The invention according to claim 22 is the invention according to claim 21.
The variable word length VLIW instruction processor according to the item, wherein the instruction number rewriting instruction is executed by any one of the plurality of execution units.

The twenty-third aspect of the present invention provides the twentieth aspect.
In the variable word length VLIW instruction processor described above, the VLIW instruction including the instruction of the number of instructions is a VLIW instruction having a field indicating the number of instructions.

[0034] The invention according to claim 24 is the invention according to claim 23.
A dedicated execution unit for rewriting the number of instructions stored in the number-of-instructions register, and decoding the number of instructions indicated in the field in the VLIW instruction; And a decoding / control means for controlling the execution unit dedicated to rewriting so that the number of instructions stored in the execution unit is rewritten to the number of decoded instructions.

According to a twenty-fifth aspect of the present invention, there is provided the twentieth aspect.
In the variable word length VLIW instruction processor described above, the instruction control unit is provided with control means for dividing a plurality of instructions constituting one VLIW instruction into a plurality of instruction groups and executing the instructions in parallel for each of the instruction groups. Features.

According to a twenty-sixth aspect of the present invention, there is provided the above-mentioned twenty-fifth aspect.
In the variable word length VLIW instruction processor described above, the control means uses a number of instructions constituting one VLIW instruction as a dividend, a number of the execution units as a divisor, and a division means for obtaining a quotient and its remainder. If the number is not "0", the parallel execution of the same number of instructions is repeated by the number of quotients using the plurality of execution units, and if the remainder is not "0", Simultaneous parallel execution of instructions is performed using the number of execution units equal to the number of remainders. On the other hand, when the quotient is “0”, simultaneous parallel execution of instructions is performed using the number of execution units equal to the number of remainders. And an instruction control unit for performing the execution.

According to a twenty-seventh aspect, in the twenty-fifth aspect,
27. The variable word length VLIW instruction processor according to claim 26, wherein the VLIW instruction having an instruction number rewriting instruction includes the instruction number rewriting instruction in an instruction group executed at the last time.

The invention according to claim 28 is the invention according to claim 25.
27. The variable word length VLIW instruction processor according to claim 26, wherein the VLIW instruction having an instruction number rewriting instruction is included in a group of instructions executed immediately before the last instruction number. It is characterized by the following.

According to the twenty-ninth aspect of the present invention, there is provided the method as set forth in the twenty-fifth aspect.
27. The variable word length VLIW instruction processor according to claim 26, wherein the VLIW instruction having an instruction number rewriting instruction is included in an instruction group executed two times before the last instruction number. It is characterized by the following.

According to a thirty-first aspect of the present invention, there is provided the second aspect of the present invention.
7. A variable word length VLIW according to claim 28 or claim 29.
In the instruction processor, the instruction control unit includes:
A VLI following the VLIW instruction including the instruction number rewriting instruction according to the position of the instruction group including the instruction number rewriting instruction in a plurality of instruction groups constituting the LIW instruction.
It is characterized by having instruction fetch pipeline control means for suppressing the fetch of the instruction executed first time in the W instruction.

According to a thirty-first aspect of the present invention, there is provided the method as set forth in the twenty-fifth aspect.
27. The variable word length VLIW instruction processor according to claim 26, wherein a certain VLIW instruction includes a branch instruction in a group of instructions executed at the last time.

The thirty-second aspect of the present invention relates to the twenty-fifth aspect.
27. The variable word length VLIW instruction processor according to claim 26, wherein a certain VLIW instruction includes a branch instruction in an instruction group to be executed immediately before the last time.

The thirty-third aspect of the present invention provides the above-mentioned twenty-fifth aspect.
27. The variable word length VLIW instruction processor according to claim 26, wherein a certain VLIW instruction includes a branch instruction in an instruction group executed two times before the last time.

The invention according to claim 34 is the third invention.
34. The variable word length VLIW according to claim 32 or claim 33.
In the instruction processor, the instruction control unit includes:
Execution of an instruction to be executed for the first time in a VLIW instruction following the VLIW instruction including the branch instruction in accordance with a position of the instruction group including the branch instruction in a plurality of instruction groups constituting the LIW instruction; It is characterized by having an execution pipeline control means and a write pipeline control means for canceling each write operation.

The invention according to claim 35 is the invention according to claim 34.
In the variable word length VLIW instruction processor described above, the instruction control unit further includes a branch destination address holding register for storing a branch destination address of a branch instruction included in the VLIW instruction.

The invention according to claim 36 is the invention according to claim 20.
The described variable word length VLIW instruction processor is characterized in that the number of instructions stored in the instruction number register is initialized at power-on and at system reset.

The invention according to claim 37 is the invention according to claim 20.
In the variable word length VLIW instruction processor described above, the number of instructions stored in the instruction number register is the same as the instruction format, and the number of execution units differs from the VLIW instruction
When an object program for a processor that executes an IW instruction is executed, the object program is rewritten by an instruction number rewriting instruction included in the VLIW instruction executed immediately before the head of the object program. I do.

The variable word length VLIW according to claim 38.
An instruction processor, comprising: a plurality of execution units for executing instructions; and an instruction control unit for controlling execution of the instructions by the execution units. A VLIW instruction processor having a variable word length. Division means for obtaining a quotient and its remainder by using the number of instructions included as a dividend and the number of execution units as a divisor, and when the quotient is not "0", using the plurality of execution units to equal the number The simultaneous parallel execution of the number of instructions is repeated by the number of the quotients. Thereafter, if the remainder is not "0", the instructions are simultaneously executed in parallel using the execution units of the number equal to the number of the remainders. , The quotient is “0”
In the case of (1), there is provided instruction control means for executing instructions in parallel in parallel using the number of execution units equal to the number of the remainders, and a plurality of instructions constituting one VLIW instruction by the above configuration Is divided into a plurality of instruction groups, and instructions are executed in parallel for each of the instruction groups.

The thirty-ninth aspect of the present invention relates to the thirty-eighth aspect.
In the variable word length VLIW instruction processor described above, the instruction control unit further includes a branch destination address holding register for storing a branch destination address of a branch instruction included in the VLIW instruction.

According to the above construction, the VLIW instruction included in the VLIW instruction
The VLIW instruction word length or the instruction number stored in the VLIW instruction word length register or the instruction number register is rewritten and updated based on an instruction of the instruction word length or the instruction number, for example, the instruction word length or the instruction number rewriting instruction. Therefore, when the VLIW instruction word length is short or the number of instructions is updated to be small, "N
OP "(no execution) instruction is reduced or eliminated, and the instruction memory is effectively used. On the other hand, in the case of a normal instruction (object program) having no field indicating the VLIW instruction word length, the power-on or system The initial value of the VLIW instruction word length register or the number of instructions stored in the VLIW instruction word length register or the instruction register is initialized to an initial value, that is, the instruction word length according to each model by initial program loading (IPL) executed at the time of resetting Therefore, the object program of the conventional processor is executed with the initially set instruction word length as a fixed value.The VLIW instruction has a format in which a plurality of instructions are arranged, but in some cases, the VLIW instruction has a format. The start data may be added to the front part and the end data may be added to the rear part.

The same applies to the case where an instruction number register for storing the number of instructions included in the VLIW instruction is provided. That is, if the bit lengths required to define each of the plurality of instructions included in the VLIW instruction are all the same width, the VLIW instruction word length and the number of instructions included in the VLIW instruction word are as follows:
A 1: 1 correspondence can be taken. For example, when the instruction word length of the VLIW instruction is 64 bytes, the bit length of one instruction is 4 bytes.
When it is a byte, it can be calculated that the number of instructions included in the VLIW instruction is 16. Therefore, as described above, both a VLIW instruction having a field indicating the number of instructions and an object program of a conventional processor can be executed.

Further, in the invention according to claim 38 and claim 39, the quotient m is calculated using the obtained quotient m and the remainder δ.
When = 0, the number of instructions L (= remainder δ) is executed in parallel, and when the quotient m is m ≠ 0, the number of instructions equal to the number of execution units of the processor is executed in parallel. Is repeated the number of times of the quotient m, and when the remainder δ is not “0”, instructions of the same number as the remainder δ are executed in parallel.
Therefore, even when the maximum number of instructions that the VLIW processor can execute in parallel at the same time differs, or when the number of instructions included in the VLIW instruction is larger than the maximum number of instructions that can be executed in parallel by the processor, the quotient m is set to If the number is set to be equal to or less than the maximum number of instructions that can be executed in parallel, the VLIW instruction can always be executed.

[0053]

Embodiments of the present invention will be described below with reference to the drawings.

The meanings of "instruction" and "VLIW instruction" used in the embodiment of the present invention are defined as follows. This definition applies to the above description as well. That is, an instruction refers to a task that is performed for each execution unit, although one or a plurality of execution units are included in an element configuring the processor. The VLIW instruction is a group of one or a plurality of instructions recognized by the compiler as being executed by the processor at one time.

(First Embodiment) FIG. 1 shows the overall configuration of a variable word length VLIW instruction processor according to the present invention.

In the figure, reference numeral 1 denotes an instruction control unit;
a to 2n are a predetermined number N of execution units, 4 is a register file, 5 is an instruction cache, 6 is a data cache, 7
Is a memory management unit, 8 is a bus control unit, and 9 is a main storage device.

The instruction control unit 1 has an instruction cache 5
From the execution units 2a to 2n
To start the execution of the instruction and control the execution of the instruction.

The execution units 2a to 2n start the execution of the instruction in response to the instruction execution start instruction from the instruction control unit 1, read the necessary operands from the register file 4, and store the execution result of the instruction in the register file 4. Write. When executing an instruction to load an operand into the register file 4 or an instruction to store an operand from the register file 4, the execution units 2a to 2n send a load request or a store request to the memory management unit 7 and an operand address. Is sent. Further, when executing the branch instruction, the execution units 2a to 2n send information of branch taken / not taken and a branch address to the instruction control unit 1.

The memory management unit 7 determines whether or not the instruction corresponding to the address of the instruction control unit 1 requesting the instruction fetch exists in the instruction cache 5. As a result of the determination, the instruction corresponds to the instruction cache 5. If there is no command, the bus control unit 8 is requested to transfer the corresponding command from the main storage device 9.

Further, the memory management unit 7 determines whether or not data corresponding to the address for requesting loading of the operand from the execution units 2a to 2n into the register file 4 exists in the data cache 6, and As a result of the determination, when there is no corresponding data in the data cache 6, the bus control unit 8 is requested to transfer the corresponding data from the main storage device 9.

Further, the memory management unit 7 determines whether or not the data to be rewritten corresponding to the address requesting the storage of the operand from the register file 4 from the execution units 2a to 2n exists in the data cache 6. If the result of the determination is that there is data corresponding to the data cache 6, the data from the register file 4 is written to the data cache 6, and whether the data to be rewritten exists in the data cache 6 is determined. Main storage device 9 for the bus control unit 8
Request to store the corresponding data.

FIG. 2 shows the internal configuration of the instruction control unit 1.

In the figure, 11 is a VLIW instruction word length register, 12 is an instruction number (L) calculating means, and 13 is an execution unit number (N) register. 21 is one VL
This is control means for dividing a plurality of (L) instructions constituting the IW instruction into a plurality of (m or m + 1) instruction groups and executing instructions in parallel for each of the instruction groups. This control means 21
Consists of a dividing means 14 and an instruction controlling means 23. Further, the instruction control means 23 includes a constant “1” adder 15
And a multiplexer 16 having two inputs and one output, and a repetition control means 18 in the VLIW instruction.

In FIG. 2, reference numeral 17 denotes a two-input one-output multiplexer; 19, multiplication means; 20a to 20n, a predetermined number N of two-input, one-output multiplexers;
2n is a predetermined number N of instruction registers, 24a to 24n are predetermined number N of decoding / execution control means, 26 and 27 are N-input 1-output multiplexers, 28 is a branch destination address holding register, 29 is a 3-input 1-output multiplexer. , 30 are an instruction fetch address register, and 31 is an adder.

The VLIW instruction word length register 11 stores the IP
VLIW of object program executed first after completion of L (initial program loading)
The instruction word length is set as an initial value, and the execution unit number N is set in the execution unit number register 13 by the IPL.

Here, in a narrow sense, the IPL refers to loading a program such as a loader in a state where no program is stored in the main storage device 9. However, here, furthermore, prior to loading, an initial setting of the processor and a test of normal operation are performed, and as a result,
When it is determined that the program is operable, a series of operations from loading the program to allowing the processor to execute the loaded program is called IPL. FIG. 13 shows the details of the IPL. In the figure, the IPL is
Triggered after powering on the processor or after performing a system reset on the processor. After that,
Prior to loading, after performing initial settings of the processor, such as writing an initial set value to a predetermined register, in order to perform a predetermined number N of tests to determine whether various operations of the processor are performed normally, first, , Set the test number counter to “0” and then set the test number counter to “1”.
The first test is performed by counting up only, and it is determined whether or not the test result is correct. If the test result is not correct, the IPL is immediately terminated as an abnormal case. On the other hand, if the first test is correct, it is determined whether or not the number of times of the test is the predetermined number N. If there is no abnormality in the test result, it is determined that operation is possible, the program is loaded, and the processor is allowed to execute the loaded program. At least once, when an abnormality is detected in the test result, a measure such as turning on a warning lamp or sounding a warning buzzer is performed.

One of the N execution units 2a to 2n is the VLIW instruction word length register 11 VLIW.
When executing the instruction word length rewriting instruction (word length rewriting instruction) (described later), the multiplexer 26 selects the VLIW instruction word length sent from the corresponding execution unit, and
It is taken into the LIW instruction word length register 11.

The instruction number (L) calculating means 12 calculates the V
The number of instructions L is calculated from the VLIW instruction word length output from the LIW instruction word length register 11. In the present embodiment, VLI
It is assumed that the W instruction is composed of L 4-byte instructions. Therefore, the VLIW instruction word length output from the VLIW instruction word length register 11 is divided by 4 bytes. Specifically, the number-of-instructions (L) calculating means 12 obtains the number L of instructions by shifting the VLIW instruction word length output from the VLIW instruction word length register 11 right by two bits.

The dividing means 14 comprises an instruction number calculating means 12
Is set as the dividend, the number of execution units N output from the execution unit number register 13 is set as the divisor, and division is performed to obtain the quotient m and the remainder δ.

The adder 15 adds “1” to the quotient m, and the multiplexer 16 selects the quotient m when the remainder δ is “0”, and adds the addition result when the remainder δ is not “0”. Select m + 1.

The VLIW instruction repetition control means 18 comprises:
The instruction control unit executes N instructions in one VLIW instruction the number of times equal to the quotient m, and further executes the number of instructions equal to the remainder δ when the remainder δ is not “0”. 1 controls the whole.

The multiplexer 17 has one VLI.
When the W instruction is processed, if the quotient m is m ≠ 0, first the selection of N output from the execution unit number register 13 is repeated m times, and then the remainder δ output from the division means 14 becomes “ Only when it is not 0 ", the remainder δ is selected,
When the quotient m is m = 0, the remainder δ output from the dividing means 14 is selected.

The multiplying means 19 includes a multiplexer 17
Is multiplied by “4” (specifically, in this embodiment, the lower 2 bits are shifted to the left by 2 bits to “0”), and the increment of the instruction fetch address is calculated.

The multiplexers 20 a to 20 n
Under the control of the LIW in-instruction repetition control means 18, the instruction read from the instruction cache 5 or "NOP" is selected. Here, the VLIW-instruction repetition control means 18 sets "NO"
In the case where control is performed to select “P”, when the remainder δ is not “0”, among the N instructions read from the instruction cache 5, N−δ instructions from the rear are replaced by the next VLI.
When included in the W instruction, and as described later, a VLIW instruction word length register 1
There is a case where the IF stage (instruction fetch stage) of the next VLIW instruction is suppressed before the rewriting of 1 is completed.

The outputs of the multiplexers 20a to 20n are
It is set in the instruction registers 22a to 22n.

The decryption / execution control means 24a to 24n
Decodes the outputs of the instruction registers 22a to 22n and instructs the execution units 2a to 2n to start executing the instructions, respectively. Therefore, the instruction registers 22a to 22n
If the instruction stored in any one of the above is a VLIW instruction word length rewrite instruction, the corresponding decoding / execution control means decodes the instruction, and the corresponding execution unit sets the VLIW instruction word length register. A rewrite instruction having a VLIW instruction word length of 11 is executed.

The instruction fetch address register 30 always stores the address of the instruction to be fetched.
That is, when the branch instruction is not established, the increment of the address output from the multiplication means 19 is added to the address of the instruction fetch address register 30 by the adder 31, and the addition result is selected by the multiplexer 29, and the instruction fetch is performed again. The data is taken into the address register 30. On the other hand, when the branch instruction is taken, the branch address sent from the execution unit executing the branch instruction is input to the multiplexer 2.
7 and is taken into the branch destination address reservation register 28.

The VLIW-instruction repetition control means 18 controls a plurality of multiplexers 17, 20 a to 20 n, 29, etc. so that all instructions including branch instructions are executed. An appropriate address is selected and taken into the instruction fetch address register 30.

Hereinafter, the operation of the VLIW instruction processor according to the present embodiment will be described with reference to the program shown in FIG. When a description is given using a program that is actually used, a long program needs to be tracked. Therefore, a simplified program is used in FIG. 3 so that the gist of the present invention can be easily understood. In the figure, the VLIW instruction 1, the VLIW instruction 2, and the VLIW instruction 3 each have the number of instructions "2", the number of instructions from the VLIW instruction 4 to the VLIW instruction 8 becomes "L", and the VLIW instruction 9, VLIW instruction 9, VLIW instruction
The instruction number becomes “2” again by the instruction 10. Even in a program to be actually used, similarly to FIG. 3, at first, an execution environment of a VLIW instruction having a small number of instructions is prepared by using a VLIW instruction having a small number of instructions, and then a VLIW instruction having a large number of instructions is set as a high VLIW instruction processor. Demonstrate performance,
Thereafter, post-processing is generally performed by a VLIW instruction having a small number of instructions.

When the IPL is completed normally, “8” is initially set in the VLIW instruction word length register 11 and the number of execution units N is stored in the execution unit number register 13 (N is larger than “2” in FIG. 3). Is assumed) is stored.
The instruction fetch address register 30 stores the start address of the program by IPL. When the instruction control unit 1 requests an instruction fetch request from the instruction cache 5 and the memory management unit 7 at the same time, there is no valid data in the instruction cache yet, and therefore, a series of data transfer from the main memory 9 to the instruction cache 5 is performed. The operation is performed.

The instruction number calculation means 12 outputs the instruction number “2”, and the division means 14 outputs a quotient “0” and a remainder “2”. The multiplexer 16 is a constant “1” adder 1
5 is selected as output "1".

The VLIW in-instruction repetition control means 18 sends the data from the instruction cache 5 to the multiplexers 20a to 20n for the first two, and the remaining N-
Control is performed to select “NOP” for two of them. V
Upon receiving a signal indicating that the fetch request data from the memory management unit 7 has been transferred to the instruction cache 5, the LIW-intra-instruction repetition control means 18
Is instructed to fetch data.

The VLIW instruction processor according to the present embodiment operates in a pipeline, and the basic pipeline includes IF (instruction fetch), DEC (instruction decoding / issuing), EX (execution), and WB (register writing). ), And each stage normally operates in one cycle.

FIG. 4 shows the pipeline operation of the VLIW instruction processor for instructions from VLIW instruction 1 to VLIW instruction 4. In the IF stage of the VLIW instruction 1, since there is no valid data in the instruction cache as described above, a series of operations for transferring data from the main storage device 9 to the instruction cache 5 are performed.

At the same time as the VLIW instruction 1 proceeds to the DEC stage, the VLIW instruction 2 proceeds to the IF stage.
VLIW instruction 1, VLIW instruction 2, and VLIW instruction 3 are 1
Processing proceeds in a cycle pitch pipeline.

In the DEC stage of VLIW instruction 3, V
The instruction included in the LIW instruction 3, for example, the instruction 31 is the VLI
One execution unit detects that the instruction is a rewrite instruction having a W instruction word length, and notifies the repetition control unit 18 within the VLIW instruction. In the DEC stage of this VLIW instruction 3, VL
The IW-instruction repetition control means 18 has issued an instruction fetch request for the VLIW instruction 4, but at this time, the VLIW instruction 4
Until the new VLIW instruction word length is stored in the instruction word length register 11, it is not known whether the VLIW instruction word length will increase or decrease.
Until two instructions included in the LIW instruction 3 enter the WB stage, all the multiplexers 20a to 20n output "NO".
P ”, and then, when two instructions included in the VLIW instruction 3 enter the WB stage,
The number of instructions L is written to the VLIW instruction word length register 11 by the LIW instruction word length rewriting instruction, and the quotient m and the remainder δ are output by the dividing means 14, and when the quotient m is m ≠ 0, The multiplexers 20a to 20n are controlled to select all the data from the instruction cache 5 so that the DEC stage for the first N instructions of the VLIW instruction 4 is started in the cycle of.

The first N instructions of VLIW instruction 4 are DE
At the same time as proceeding to the C stage, the adder 3 selected by the multiplexer 29 is stored in the instruction fetch address register 30.
1 is taken in. The fetched address is a value obtained by adding N × 4 output from the multiplying means 19 to the head address of the VLIW instruction 4.

In order to process the last δ instructions of the VLIW instruction 4 at the same time as proceeding to the m-th DEC stage of the VLIW instruction 4, in the IF stage, the VLIW instruction internal repetition control means 18 controls the multiplexers 20a to 20a. 20n
On the other hand, control is performed so that the data from the instruction cache 5 is selected up to δ from the top, and “NOP” is selected for the remaining N−δ. The multiplying means 19 outputs δ × 4 and the instruction fetch address register 30 stores V in the next cycle.
The address obtained by adding m (N × 4) + δ × 4 to the head address of the LIW instruction 4, that is, the head address of the VLIW instruction 5, is fetched.

Subsequently, VLIW instruction 5 and VLIW instruction 6
And VLIW instruction 7 are executed in the same manner as VLIW instruction 4.

The VLIW instruction 8 includes a VLIW instruction word length rewriting instruction, and the VLIW instruction 8 has a VLIW instruction 8 according to the location of the VLIW instruction 8 where the instruction is located.
The IF stage of the W instruction 9 may or may not be suppressed. The suppression control of the IF stage in this case will be described with reference to FIGS. 5, 6, and 7. FIG.

In FIG. 5, a VLIW instruction word length rewriting instruction is included in the last group of instructions processed in the VLIW instruction 8, and a VLIW instruction word length rewriting instruction is detected in the DEC stage of this instruction group. And the IF of VLIW instruction 9
The stage is suppressed for two cycles. At the beginning of the WB stage of the group of instructions processed at the end of VLIW instruction 8, VLI
When the W instruction word length register 11 is updated, the VLI
The IF stage of the W instruction 9 operates.

In FIG. 6, a VLIW instruction word length rewrite instruction is included in an instruction group processed immediately before the last of the VLIW instruction group 8, and the VLIW instruction word is rewritten in the DEC stage of the instruction group. When a long rewrite instruction is detected, V
The IF stage of the LIW instruction 9 is suppressed by one cycle.
At the beginning of the WB stage of the instruction group processed immediately before the end of the VLIW instruction 8, the VLIW instruction word length register 11
Is updated, the IF stage of the VLIW instruction 9 operates.

In FIG. 7, the VLIW instruction word length rewriting instruction is included in the instruction group processed two instructions before the last among the instruction groups of the VLIW instruction 8, and the instruction two words before the last instruction is included. At the DEC stage of the group, a VLIW instruction word length rewrite instruction is detected. At the start of the WB stage of this instruction group, the VLIW instruction word length register 11 is updated, and at the same time, the IF stage of the VLIW instruction 9 starts. Therefore,
The suppression of the IF stage by updating the VLIW instruction word length register 11 does not occur.

FIG. 8 shows a repetition control means 18 in a VLIW instruction.
2 shows an example of pipeline control means for controlling the pipeline operation.

In the figure, reference numeral 41 denotes a multiplexer, 4
2 is an IF number register, 43 is a DEC number register, 4
4 is an EX number register, 45 is a constant subtractor, and 46 and 4
7, 48 are N-input OR circuits, 49 is IF pipeline control means, 50 is DEC pipeline control means, 51 is EX pipeline control means, and 52 is WB pipeline control means.

The multiplexer 41 selects the output of the multiplexer 16 when the output of the constant subtracter 45 is "0", and selects the output of the constant subtractor 45 when the output of the constant subtractor 45 is not "0". Select output.

According to the IPL, "1" is stored in the IF number register 42, "0" is stored in the DEC number register 43, and EX
“0” is stored in the number register 44 as an initial value. These three number registers indicate how many instruction groups to be processed in the VLIW instruction (the number of instructions included in the instruction group is N or δ) are left.

A VLIW instruction word length rewriting instruction is detected by one of the N decoding execution control means 24a to 24n, and this VLIW instruction word length rewriting instruction is sent through an N-input OR circuit 46 to an IF pipe. When transmitted to the line control means (instruction fetch pipeline control means) 49, the IF pipeline control means 49 suppresses the IF stage for two cycles when the output of the DEC number register 43 is "1", and When the output of the number register 43 is “2”, the IF stage is suppressed for one cycle, and when the output of the DEC number register 43 is “3” or more, control is performed not to suppress the IF stage.

Next, the operation of the branch instruction will be described with reference to FIGS. 9, 10, 11, and 12.

Prior to the specific description, in the VLIW instruction processor according to the present embodiment, there is no restriction on the position of the branch instruction in the VLIW instruction, and the branch destination always points to the start address of the VLIW instruction. VLI
Branch after executing the instruction following the branch instruction in the W instruction. This means that the beginning of the "VLIW instruction is one that the compiler recognizes as a logical execution by the processor at one time.
One or more instructions ".

In FIG. 9, a branch instruction is included in the instruction group processed last in the instruction group belonging to the VLIW instruction A, and the branch is taken at the end of the EX stage of the instruction group processed last. Then, the branch destination address is written to the instruction fetch address register 30 at the WB stage of this instruction group. The VLIW instruction B and the VLIW instruction C, which must not be executed due to the branch taken, are overrun by one extra cycle and are canceled in the WB stage and the EX stage, respectively. Since the IF stage of the instruction group processed first of the branch destination VLIW instruction P and the WB stage of the instruction group processed last of the VLIW instruction A have the same cycle, the overhead of the branch instruction in the case of FIG. Is two cycles.

In FIG. 10, the last one of the VLIW instruction D is 1
The instruction group processed immediately before includes a branch instruction. The branch taken is determined at the end of the EX stage of the instruction group processed immediately before the end, and the instruction fetch is performed at the WB stage of this instruction group. The branch destination address is written to the address register 30. VLIW not to be executed due to branch taken
Instruction E has been overrun by one extra cycle and has been canceled in the EX stage. An IF stage of an instruction group to be processed first of the branch destination VLIW instruction Q;
Since the EX stage of the instruction group processed at the end of the W instruction A has the same cycle, the overhead of the branch instruction in the case of FIG. 10 is one cycle.

In FIG. 11, the last two VLIW instructions F
A branch instruction is included in the instruction group processed immediately before, and it is determined that the branch is taken at the end of the EX stage of the instruction group processed two steps before the end. At the beginning of the WB stage of this instruction group, , The multiplexer 29 selects not the head address of the next VLIW instruction following the VLIW instruction F, but the head address of the branch destination VLIW instruction R, and stores the head address of the branch destination VLIW instruction R in the instruction fetch address register 30. Written. Therefore, in the case of FIG. 11, no overhead is caused by the branch instruction.

In FIG. 12, the last three VLIW instructions G
The instruction group processed immediately before includes a branch instruction. At the end of the EX stage of the instruction group processed three times before the end, branch establishment is determined, and at the beginning of the WB stage of this instruction group. , The start address of the branch destination VLIW instruction S is
It is written into the branch destination address holding register 28 once. One cycle later, the output of the branch destination address reservation register 28 is selected by the multiplexer 29 and written into the instruction fetch address register 30. Therefore, no overhead is caused by the branch instruction in the case of FIG.

Next, the operation from FIG. 9 to FIG. 12 will be described with reference to FIG.

In FIG. 8, N execution units 2a to 2
2n, the branch taken is detected by the EX pipeline control means 51 and the WB pipeline control means 52 via the N-input OR circuit 48.
Is transmitted to

The EX pipeline control means (execution pipeline control means) 51 latches the branch establishment information and the value obtained by subtracting the output of the IF number register 42 from the output of the EX number register 44 at the beginning of the next cycle. , "Branch taken"
If the two conditions of “the difference is“ 0 ”or negative” are satisfied, the EX stage one cycle later is canceled.

Further, the WB pipeline control means (write pipeline control means) 52 outputs
From the output of the X number register 44 to the DEC number register 43
Latched at the beginning of the next cycle
When the two conditions of “branch taken” and “difference is“ 0 ”or negative” are satisfied, the WB stage one cycle later is canceled.

Further, the WB pipeline control means 52
If two conditions of “branch taken” before latching and “output of EX number register 44 is“ 3 ”or less” are satisfied, any one of N execution units 2a to 2n
The multiplexer 2 sends the branch destination address sent from the
The selection is made by 7 and 29, and control is performed so as to be taken into the instruction fetch address register 30 in the next cycle.

In addition, the WB pipeline control means 5
2 is one of the N execution units 2a to 2n when two conditions of "branch taken" before latching and "output of EX number register 44 is" 4 "or more" are satisfied.
The multiplexer 2 sends the branch destination address sent from the
In the next cycle, the instruction is taken into the branch destination address reservation register 28, and then the output of the EX number register 44 becomes "3", and the instruction group corresponding to the EX number "3" is transferred to the WB stage. At the same timing as the process proceeds, the output of the branch destination address reservation register 28 is selected by the multiplexer 29, and the output is taken into the instruction fetch address register 30.

Therefore, according to the operation of the branch instruction described above, an instruction that must be executed after the branch instruction in the same VLIW instruction can be embedded more flexibly than the delayed branch instruction method.

Next, the fact that a VLIW instruction processor having a VLIW instruction word length register 11 characteristic of the present invention can use a program library of a conventional VLIW instruction processor having no register 11 will be described with reference to FIG. .

In FIG. 14, VLIW instruction group A is
Includes a LIW instruction word length rewrite instruction. The VLIW instruction group B is one program included in a program library of a conventional VLIW instruction processor. In the description of this operation, an example will be described in which after executing the VLIW instruction group A up to the VLIW instruction 3, all the conventional VLIW instruction groups B are executed, and then returning to the VLIW instruction group A.
In FIG. 14, as in FIG. 3, the program is simplified so that the gist of the invention can be easily understood.

In FIG. 14, VL of VLIW instruction group A
In the instructions 11 and 12 of the IW instruction 1 and the instruction 21 of the instruction 2, the data used in the VLIW instruction group B is prepared so as to be referred to by the instructions constituting the VLIW instruction in the VLIW instruction group B. Next, the VLIW instruction group A
Of the VLIW instruction group 2 of the VLIW instruction group A in the instruction 22 of the VLIW instruction 2
The start address of the instruction 8, that is, the return address is set.
Instruction 31 of VLIW instruction 3 in VLIW instruction group A includes V
The LIW instruction word length rewriting instruction includes an instruction for rewriting the instruction word length to the instruction word length of the VLIW instruction group B used in the conventional VLIW instruction processor. The word length is rewritten to this instruction word length. VLIW of VLIW instruction group A
The instruction 32 of the instruction 3 includes a branch instruction that branches first at the beginning of the conventional VLIW instruction group B. Therefore, the instruction 32 branches at the beginning of the VLIW instruction group B, and the VLIW instruction having the number of instructions L is 5,
6. Execute steps 6 and 7. The last VLIW instruction 7 includes a branch instruction having the branch address of the contents of the “0” th register of the register file 4. By executing this instruction, the VLIW instruction 8 of the VLIW instruction group A of the present invention is executed. Return to The VLIW instruction 8 has the same number L of instructions as the number L of the VLIW instructions 5, 5, 6, and 7 in the VLIW instruction group B.
The VLIW instruction 8 includes a VLIW instruction word length rewriting instruction, and the VLIW instruction word length is rewritten by this instruction. Therefore, after that, VLIW
In the instruction group A, the VLIW instructions 9 and 10 whose instruction length is rewritten, for example, the number of instructions = 2 are executed. When returning from the VLIW instruction group B to the VLIW instruction group A, the VLIW instruction word length register 11 has not yet been rewritten. The VLIW instruction word length of the VLIW instruction of the VLIW instruction group B must be the same.

In this embodiment, a VLIW instruction word length rewrite instruction is present among a plurality of instructions constituting the VLIW instruction, but the present invention is not limited to this. That is,
For example, as shown in FIG. 15 showing the conventional example described above, V is set in the field of the general control unit located at the head of the VLIW instruction.
In the VLIW instruction for designating the LIW instruction word length, as shown in the figure, a dedicated decoding / control means 24n + 1 for decoding the VLIW instruction word length in the field is provided, and the decoding control means 24n + 1 provides A dedicated execution unit 2n + 1 for controlling and storing the decoded VLIW instruction word length in the VLIW instruction word length register 11 and updating the VLIW instruction word length may be provided.

(Second Embodiment) FIG. 16 shows a second embodiment of the present invention. This figure shows an instruction control unit 1 'of the variable word length VLIW instruction processor according to the first embodiment, in which the instruction control unit 1 shown in FIG. 2 is partially modified. The difference is that the instruction control unit 1 shown in FIG.
VLIW instruction word length register 11 and instruction number calculation means 1
2 and an instruction number register 60 is provided.
Other configurations are the same as those in FIG. That is, in the first embodiment, the VLIW instruction word length rewritten by the instruction word length rewriting instruction included in the VLIW instruction is VL
The instruction number is stored in the IW instruction word length register 11 and the instruction number is calculated by the instruction number calculating means 12 by dividing the instruction word length by the bit length of one instruction. In this embodiment, only the instruction number register 60 is provided, and therefore, the VLIW instruction includes:
An instruction (an instruction number rewriting instruction) for rewriting and updating the number of instructions included in the instruction to the desired number of instructions is included. Therefore, it is only necessary to change the wording of the "VLIW instruction word length rewriting instruction" shown in FIGS. 5 to 7 of the first embodiment to the "instruction number rewriting instruction". Omitted. In the present embodiment, the bit lengths of the instructions included in the VLIW instruction do not need to be the same, but may be different.

[0117]

As described above, according to the variable word length VLIW instruction processor of the present invention, a VLIW instruction word length register or instruction number register rewritable by an instruction is provided. So, "NO
The instruction of P "(no execution) can be reduced or eliminated, and the instruction memory can be used effectively.
Since the VLIW instruction word length register or instruction number register can be initialized by program loading or the like,
By setting the instruction word length to a fixed value, it becomes possible to execute an object program of a conventional processor.

According to the variable word length VLIW instruction processor of the present invention, the VLI
The number of instructions included in the W instruction is divided by the number of execution units to obtain a quotient and a remainder. After repeatedly executing a number of instructions equal to the number of the execution units by the number of the quotients, the number of instructions is equal to the remainder. Since the number of instructions is executed, even if the maximum number of instructions that the VLIW instruction processor can execute simultaneously in parallel is different, or if the number of instructions included in the VLIW instruction is larger than the maximum number of instructions that can be executed in parallel by the processor, This has the effect that the VLIW instruction can always be executed.

[Brief description of the drawings]

FIG. 1 shows a variable word length VLIW according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a block configuration of an instruction processor.

FIG. 2 is a block diagram showing an internal configuration of an instruction control unit provided in the variable word length VLIW instruction processor.

FIG. 3 is a diagram showing an example of a program executed by the variable word length VLIW instruction processor.

FIG. 4 is a diagram showing a first example of the influence of a VLIW instruction word length rewriting instruction on a pipeline operation of the variable word length VLIW instruction processor.

FIG. 5 is a diagram showing a second example.

FIG. 6 is a diagram showing a third example.

FIG. 7 is a diagram showing a fourth example.

FIG. 8 is a block diagram showing the internal configuration of a VLIW instruction repetition control means provided in the instruction control unit of the variable word length VLIW instruction processor.

FIG. 9 is a diagram showing a first example of the effect of a branch instruction on a pipeline operation of the variable word length VLIW instruction processor.

FIG. 10 is a diagram showing a second example.

FIG. 11 is a diagram showing a third example.

FIG. 12 is a diagram showing a fourth example.

FIG. 13 is a flowchart showing details of initial program loading in the variable word length VLIW instruction processor.

FIG. 14 is an explanatory diagram of a case where an object program of a conventional VLIW instruction processor is used in the variable word length VLIW instruction processor.

FIG. 15 is a diagram showing a modification in the case of using a VLIW instruction having a field indicating a VLIW instruction word length.

FIG. 16 shows a variable word length VLI according to the second embodiment of the present invention.
FIG. 3 is a block diagram illustrating an internal configuration of an instruction control unit included in the W instruction processor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Instruction control unit 2a-2n Execution unit 2n + 1 Dedicated execution unit 11 VLIW instruction word length register 12 Instruction number calculation means 14 Division means 18 VLIW instruction repetition control means 19 Multiplication means 21 Control means 23 Instruction control means 24a-24n Decryption / execution control means (decryption / control means) 24n + 1 Decryption / execution control means (dedicated decryption / execution means)
Control means) 28 branch destination address reservation register 49 IF pipeline control means (instruction fetch pipeline control means) 51 EX pipeline control means (execution pipeline control means) 52 WB pipeline control means (write pipeline control means) 60 Instruction number register

Claims (39)

(57) [Claims] 1. A plurality of execution units for executing an instruction, a VLIW instruction word length register storing a VLIW instruction word length, a VLIW instruction including an instruction of the VLIW instruction word length, and a VLIW instruction in the VLIW instruction VLI according to word length
The VLIW instruction word length of the W instruction word length register is rewritten, and the VL stored in the VLIW instruction word length register is changed.
A variable word length VLIW instruction processor, comprising: an instruction control unit that controls parallel execution of instructions by all or some of the plurality of execution units based on an IW instruction word length. 2. A VL including an instruction of the VLIW instruction word length.
2. The variable word length VL according to claim 1, wherein the IW instruction includes a word length rewriting instruction for rewriting a VLIW instruction word length among a plurality of instructions constituting the VLIW instruction.
IW instruction processor. 3. The variable word length VLIW instruction processor according to claim 2, wherein said word length rewriting instruction is executed by any one of said plurality of execution units. 4. A VL including an instruction of the VLIW instruction word length.
2. The variable word length VLIW instruction processor according to claim 1, wherein the IW instruction is a VLIW instruction having a field indicating a VLIW instruction word length. 5. A dedicated execution unit for rewriting a VLIW instruction word length stored in the VLIW instruction word length register, and a VLI indicated in the field in the VLIW instruction.
A decoding / control means for decoding the W instruction word length and controlling the execution unit exclusively for rewriting so as to rewrite the VLIW instruction word length stored in the VLIW instruction word length register to the decoded VLIW instruction word length is separately provided. 5. The variable word length VLIW instruction processor according to claim 4, comprising: 6. One VLIW instruction comprises a plurality of instructions, the plurality of instructions having the same predetermined bit length, and wherein the instruction control unit is stored in the VLIW instruction word length register. 2. The variable word length VLIW instruction processor according to claim 1, further comprising instruction number calculation means for calculating the number of instructions included in one VLIW instruction by dividing a VLIW instruction word length by the predetermined bit length. 7. An instruction control unit, comprising: a plurality of instructions constituting one VLIW instruction, divided into a plurality of instruction groups, and control means for executing the instructions in parallel for each instruction group. 2. The variable word length VLIW instruction processor of claim 1. 8. The control means sets the number of instructions constituting one VLIW instruction as a dividend,
Division means for obtaining a quotient and its remainder using the number of execution units as a divisor; and when the quotient is not "0", simultaneously executing a number of instructions equal to the number using the plurality of execution units. Is repeated by the number of quotients. Thereafter, if the remainder is not “0”, instructions are executed in parallel using the execution units of the number equal to the number of remainders, while the quotient is “0”. 8. The variable word length VL according to claim 7, further comprising: instruction control means for executing instructions in parallel in parallel using the number of execution units equal to the number of remainders.
IW instruction processor. 9. The VLIW having a word length rewrite instruction.
9. The variable word length VLIW instruction processor according to claim 7, wherein the instructions include the word length rewriting instruction in an instruction group executed at the last time. 10. The VLI having a word length rewrite instruction.
9. The variable word length VLIW instruction processor according to claim 7, wherein the W instruction includes the word length rewriting instruction in an instruction group executed immediately before the last instruction. 11. The VLI having a word length rewrite instruction.
9. The variable word length VLIW instruction processor according to claim 7, wherein the W instruction includes the word length rewriting instruction in an instruction group executed two times before the last instruction. 12. The VLIW instruction including the word length rewriting instruction according to a position of an instruction group including the word length rewriting instruction among a plurality of instruction groups constituting a VLIW instruction. The next VLIW
12. The variable word length VLIW instruction processor according to claim 9, further comprising instruction fetch pipeline control means for suppressing fetching of an instruction executed first time in an instruction. 13. The variable word length VLIW instruction processor according to claim 7, wherein a certain VLIW instruction includes a branch instruction in a group of instructions executed at the last time. 14. The variable word length according to claim 7, wherein a certain VLIW instruction includes a branch instruction in an instruction group to be executed immediately before the last time. V
LIW instruction processor. 15. The variable word length according to claim 7, wherein a certain VLIW instruction includes a branch instruction in a group of instructions executed two times before the last time. V
LIW instruction processor. 16. The VLIW instruction following the VLIW instruction including the branch instruction according to a position of an instruction group including the branch instruction in a plurality of instruction groups constituting a VLIW instruction. 16. The variable word length according to claim 13, further comprising execution pipeline control means and write pipeline control means for canceling execution and writing of an instruction executed first time in the instruction. VLIW instruction processor. 17. The variable word length VLIW instruction according to claim 16, wherein said instruction control unit further comprises a branch destination address reservation register for storing a branch destination address of a branch instruction included in said VLIW instruction. Processor. 18. The variable word length VLIW instruction processor according to claim 1, wherein the VLIW instruction word length stored in the VLIW instruction word length register is initialized at power-on and at system reset. 19. A VLIW instruction word length stored in a VLIW instruction word length register executes an object program for a processor that executes a VLIW instruction having the same instruction format and a different number of execution units from the VLIW instruction. 2. The variable word length VLIW instruction processor according to claim 1, wherein the word length is rewritten by a word length rewriting instruction included in the VLIW instruction executed immediately before the head of the object program. 20. A plurality of execution units for executing instructions, an instruction number register for storing the number of instructions included in the VLIW, and a VLIW instruction including an instruction for the number of instructions.
An instruction for rewriting the number of instructions in the instruction number register according to the number of instructions in the instruction, and for controlling parallel execution of instructions by all or some of the plurality of execution units based on the number of instructions stored in the instruction number register. A variable word length VLIW instruction processor comprising a control unit. 21. The variable VLIW instruction according to claim 20, wherein the VLIW instruction including the instruction of the instruction number includes an instruction number rewriting instruction for rewriting the instruction number among a plurality of instructions constituting the VLIW instruction. Word length VLIW instruction processor. 22. The variable word length VLIW instruction processor according to claim 21, wherein said instruction number rewriting instruction is executed by any one of said plurality of execution units. 23. The variable word length VLIW instruction processor according to claim 20, wherein the VLIW instruction including the instruction of the number of instructions is a VLIW instruction having a field indicating the number of instructions. 24. A dedicated execution unit for rewriting the number of instructions stored in the instruction number register, and an instruction stored in the instruction number register, which decodes the number of instructions indicated in the field in the VLIW instruction. 24. The variable word length VLIW according to claim 23, further comprising decoding / control means for controlling the execution unit dedicated to rewriting so as to rewrite the number to the number of decoded instructions.
Instruction processor. 25. An instruction control unit, comprising: a plurality of instructions constituting one VLIW instruction, divided into a plurality of instruction groups, and control means for executing instructions in parallel for each of the instruction groups. 21. The variable word length VLIW instruction processor of claim 20. 26. A control means, comprising: a number of instructions constituting one VLIW instruction as a dividend;
Division means for obtaining a quotient and its remainder using the number of execution units as a divisor; and when the quotient is not "0", simultaneously executing a number of instructions equal to the number using the plurality of execution units. Is repeated by the number of quotients. Thereafter, if the remainder is not “0”, instructions are executed in parallel using the execution units of the number equal to the number of remainders, while the quotient is “0”. 26. The variable word length V according to claim 25, further comprising: instruction control means for executing instructions in parallel in parallel using the same number of execution units as the remainder.
LIW instruction processor. 27. The VL having an instruction number rewrite instruction.
26. The IW instruction, wherein the instruction number rewriting instruction is included in an instruction group executed at the last time.
27. A variable word length VLIW instruction processor according to claim 26. 28. The VL having an instruction number rewrite instruction.
27. The variable word length VLIW instruction processor according to claim 25, wherein the IW instruction includes the instruction number rewriting instruction in an instruction group executed immediately before the last instruction. 29. The VL having an instruction number rewriting instruction.
27. The variable word length VLIW instruction processor according to claim 25, wherein the IW instruction includes the instruction number rewriting instruction in an instruction group executed two times before the last instruction. 30. The instruction control unit, according to a position of an instruction group including the instruction number rewriting instruction among a plurality of instruction groups constituting a VLIW instruction, the VLIW instruction including the instruction number rewriting instruction. Next VL
30. The variable word length VLIW instruction processor according to claim 27, further comprising instruction fetch pipeline control means for suppressing fetch of an instruction executed first time in an IW instruction. 31. The variable word length VLIW instruction processor according to claim 25, wherein a certain VLIW instruction includes a branch instruction in a group of instructions executed at the last time. 32. The variable word length according to claim 25, wherein a certain VLIW instruction includes a branch instruction in a group of instructions executed immediately before the last time. VLIW instruction processor. 33. The variable word length according to claim 25, wherein a certain VLIW instruction includes a branch instruction in an instruction group executed two times before the last time. VLIW instruction processor. 34. The VLIW instruction following the VLIW instruction including the branch instruction according to a position of an instruction group including the branch instruction among a plurality of instruction groups constituting a VLIW instruction. 34. The variable word length according to claim 31, further comprising execution pipeline control means and write pipeline control means for canceling execution and writing of an instruction executed first time in the instruction. VLIW instruction processor. 35. The variable word length VLIW instruction according to claim 34, wherein said instruction control unit further comprises a branch destination address reservation register for storing a branch destination address of a branch instruction included in said VLIW instruction. Processor. 36. The variable word length VL according to claim 20, wherein the number of instructions stored in the instruction number register is initially set when power is turned on and when the system is reset.
IW instruction processor. 37. The number of instructions stored in the instruction number register, when executing an object program for a processor that executes a VLIW instruction having the same instruction format and a different number of execution units from the VLIW instruction, 21. The variable word length VLIW instruction processor according to claim 20, wherein the variable word length VLIW instruction processor is rewritten by an instruction number rewriting instruction included in the VLIW instruction executed immediately before the head of the object program. 38. A variable word length VLIW instruction processor comprising: a plurality of execution units for executing an instruction; and an instruction control unit for controlling execution of the instruction by each execution unit, wherein the instruction control unit comprises a VLIW instruction. Division means for obtaining a quotient and its remainder by using the number of instructions included in the dividend as a dividend and the number of the execution units as a divisor, and when the quotient is not “0”, the number of execution units is reduced by using the plurality of execution units. The simultaneous and parallel execution of an equal number of instructions is repeated by the number of quotients, and if the remainder is not "0", the instructions are executed in parallel by using an execution unit having a number equal to the number of the remainders. On the other hand, when the quotient is “0”, the apparatus further comprises instruction control means for executing instructions in parallel using the same number of execution units as the remainder. Accordingly, it defines a plurality of instructions forming a single VLIW instruction into a plurality of instructions, variable word length VLIW-instruction processor, characterized by parallel execution of instructions by the respective instructions. 39. The variable word length VLIW instruction processor according to claim 38, wherein the instruction control unit further includes a branch destination address reservation register for storing a branch destination address of a branch instruction included in the VLIW instruction.