JPH08161222A - Processor and program preparation method therefor - Google Patents

Abstract

PURPOSE: To select an external RAM access method corresponding to a required processing speed. CONSTITUTION: The instruction code of a first mode for which an access object becomes an internal or external RAM by the arithmetic result of a valid address computing part 30 and the instruction code of a second mode for which the instruction code itself indicates it is access to the external RAM and an external RAM access address is specified by the previous step of the instruction code are provided. A control part 20 delays the operation of the program counter 13 and the decoding operation of the instruction code for a system clock cycle number W set in a weight cycle register 25 when the decoded result of the instruction code is the RAM read instruction of the first mode and the arithmetic result of the valid address computing part 30 is within the address range of the external RAM and delays the operation of the program counter 13 and the decoding operation of the instruction code for the system clock cycle number W-2 when the decoded result of the instruction code is the RAM read instruction of the second mode and the W-2 is positive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor such as a digital signal processor and a microprocessor, and a program creating method thereof.

[0002]

2. Description of the Related Art For example, in a DSP, a program ROM
And a data RAM (internal RAM).
The internal RAM operates at high speed, but has a storage capacity of, for example, 1
Since it is as small as K bytes, an external RAM, which operates slower than the internal RAM but has a large storage capacity, is used.

There are the following two methods for accessing the external RAM. (1) Operand address calculation result (execution address)
If the value exceeds the range of the internal RAM, the external RAM access processing is started. Wait time required to access external RAM,
Stop the operation. (2) If it is possible to identify the external RAM access by the instruction code itself, the external RAM access address is calculated in advance in the step before the external RAM access instruction, and it is determined that the instruction code is the external RAM access, The calculated external RAM access address is output. If waiting time is required to access the external RAM,
Execute the next step instruction.

In the method (1), the external RAM is replaced with the internal RAM.
Can be treated as a mere extension of the above, and software can be created without distinguishing between internal RAM and external RAM, which has the advantage of simplifying the software. It has the disadvantage of being slow. The method (2) has an advantage that high-speed processing is possible, but has a disadvantage that the software becomes complicated because it is necessary to create the software by distinguishing the internal RAM and the external RAM.

[0005]

The conventional processor has the following problems.
Since either one of the methods (1) and (2) is adopted, when the processor adopting the method (2) is used, the software can be used even for a portion having no problem even if the processing time is slow. Becomes complicated, and when a processor adopting the method of (1) is used, even if only a part of the high-speed processing is sufficient, it cannot be performed, and the performance of the system to which the processor is applied deteriorates. There was a problem.

In view of such problems, an object of the present invention is to provide a processor capable of selecting an external RAM access method according to a required processing speed and a program creating method thereof.

[0007]

In the processor of the first invention, a program counter, a program memory in which a program is stored, and an instruction code is read out by being addressed by the contents of the program counter,
An internal RAM for reading and writing data, an effective address calculation unit for calculating an access address to the internal RAM and the external RAM, a data register for transferring data between the internal RAM and the external RAM, and the external RA
A wait cycle register in which the access time W of M is set by a program in units of system clock cycles and an instruction code read from the program memory are decoded, and the decoding result, the operation result of the effective address operation unit and the operation result The operation of the program counter, the effective address operation unit and the data register is controlled based on the contents of the wait cycle register, the decoding operation of the instruction code is controlled, and the read / write operation for the internal RAM and the external RAM is performed. And a control unit for controlling
The instruction code for M access is the instruction code of the first mode in which the read / write operation target is the internal RAM or the external RAM, and the instruction code itself is an access to the external RAM. And an instruction code of a second mode in which the external RAM access address is designated by the instruction code of the previous step of the instruction code, and the control unit reads the RAM of the decoding result of the instruction code in the first mode. When the instruction is an instruction and the operation result of the effective address operation unit is within the address range of the external RAM, the system in which the operation of the program counter and the operation of decoding the instruction code are set in the wait cycle register By delaying by the number of clock cycles W, the data read from the external RAM is transferred to the data register. If the decoding result of the instruction code is a RAM read instruction in the second mode, and the value W-2 obtained by subtracting 2 from the system clock cycle number W set in the wait cycle register is positive. In this case, the data read from the external RAM is held in the data register by delaying the operation of the program counter and the decoding operation of the instruction code by the number of system clock cycles W-2.

According to the first aspect of the present invention, since the RAM access in both the first and second modes is possible, it is possible to select the external RAM access method according to the required processing speed. In the program creating method of the second invention, using the processor, a program to be stored in the program memory is created by using the external RAM read command in the second mode, at least for a portion requiring high-speed processing.

According to the second aspect of the invention, by using the RAM access instruction of the first mode which is the same format as the internal RAM access instruction for the portion which does not require the high speed processing, the program is simplified and the high speed processing is performed. High-speed processing can be performed by using the external RAM read command in the second mode for a necessary portion.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 2A, an external RAM 50 is connected to the digital signal processor (DSP) 10 via an external address bus AB and an external data bus DB. The external address bus AB has 24 bits. The DSP 10 has a higher RA than the external RAM 50.
M11 is built in. The internal RAM 11 has a storage capacity of 1 Kbyte, and its address is 0 to 1023.
And

The DSP 10 uses RA as a basic instruction.
It has an M access instruction and an inter-register operation instruction. R
For the AM access instruction, the internal RAM 11 or the external RAM is used.
The internal RAM 11 stores an instruction for reading data from the memory 50 and loading the data in the data register R, and an operation result between the registers R.
Alternatively, there is an instruction to be stored in the external RAM 50. The data register R is actually a register group, but is represented as one register for simplification, and in some cases, R1, R2
Express.

The DSP 10 has the RAM access instructions of the above-mentioned methods (1) and (2).
The access mode of this method is called a first mode, and the access mode of the method (2) is called a second mode. In the first mode,
The 14-bit offset address register OFS1 and the displacement register IX1 are used, and in the second mode, the 24-bit offset address register OFS2 and the displacement register IX2 are used.

In the first mode, an instruction to load the data register R from the internal RAM 11 or the external RAM 50 is represented by, for example, LOAD R, # 100 + IX1. Here, # 100 indicates that the content of the offset address register OFS1 is the value 100. Figure 2
In (B), the offset address register OFS1
And the contents of the displacement register IX1 are added to obtain an effective address. If the result is 1023 or less, the internal RAM 11
Access to external RAM if not
It is determined to be access to 50. In the case of accessing the external RAM 50, the upper 10 bits of the offset address register OFS2 are placed in the upper 14 bits of the addition result.
The address to which the bit is added is used as the address for the external RAM 50.

In the second mode, an instruction to load the data register R from the external RAM 50 is represented by two steps, for example, INST R1, R2, # 100 + IX2 LOAD R. INST is an arbitrary register-to-register operation instruction to which the load instruction LOA of the next step is added.
Address operation # 100 + IX2 required for DR is added. # 100 is the offset address register OF
It indicates that the content of S2 is 100. The effective address is obtained by adding the contents of the offset address register OFS2 and the displacement register IX2 in FIG. 2 (C). The second mode is determined from the instruction code of LOAD R itself.

It should be noted that instead of INST R1 and R2, a RAM access instruction in the first mode may be used, and, in addition to the instructions INST R1 and R2, an address operation instruction of only # 100 + IX2 may be used. In addition, the calculation of the effective address is addition in the above case.
In the case of -IX2, it is subtraction, and generally it is addition and subtraction.

FIG. 1 shows a schematic configuration of the DSP 10. An internal RAM 11, a data register R, an arithmetic circuit 12, a program counter 13, a program ROM 14, a controller 20, a first address calculator 30, and a second address calculator via a bus BUS including an address bus, a data bus, and a control bus. Between 40 are connected.

The control unit 20 has a four-stage instruction register IR.
1, IR1A, IR2, and IR2A are connected in cascade, the instruction code addressed by the program counter 13 is read from the program ROM 14 and held in the instruction register IR1, and the contents are synchronized with the clock in the instruction register IR1A. , IR2, and IR2A are sequentially shifted. The contents of the instruction registers IR1, IR1A and IR2 are decoded by the decoders 21, 22 and 23, respectively, and the control circuit 24 generates control signals according to the results. The decoder 21 is for calculating an operand address, the decoder 22 is for generating a control signal for the output of the calculation result, and the decoder 23 is for calculating and transferring data. The content of the instruction register IR2A is used as immediate data, and its output end is connected to the data bus.

The wait cycle register 25 holds the access time of the external RAM 50 in units of clock cycles. When a wait time for accessing the external RAM 50 is required, the control circuit 24 presets the contents of the wait cycle register 25 in the down counter 26, sets the RS flip-flop 27 at the same time, and sets the clock to the clock input terminal of the down counter 26. Supply. When the zero detection circuit 28 detects that the count value of the down counter 26 is 0, it resets the RS flip-flop 27. The control circuit 24 stops the operation of the program counter 13 while the inverting output terminal * Q of the RS flip-flop 27 is at a low level, and stops the shift between the instruction registers IR1, IR1A, IR2 and IR2A.

In the first address calculation section 30, the contents of the offset address register OFS1 and the displacement register IX1 are calculated by the adder / subtractor 31, and the data length judgment circuit 32 judges whether the result is 1024 or more.
The control circuit 24 is responsive to the determination result and the decoding result of the decoder 21 or 22 as described later, and the internal RAM 1
1 or access control to the external RAM 50 is performed. The output of the adder / subtractor 31 is supplied to the address bus and second address calculator 40 via the address buffer register 33.

The second address calculator 40 uses the adder / subtractor 41 to calculate the contents of the offset address register OFS2 and the displacement register IX2. Upper 1 of adder / subtractor 41
The 0 bit and the lower 14 bits are supplied to one input ends of the selectors 42 and 43, respectively, which are selected in the second mode and taken out as a 24-bit address onto the external address bus AB. When accessing the external RAM 50 in the first mode, the 14-bit address from the address buffer register 33 is selected by the selector 43, and the offset address register OFS2 is selected.
The upper 10 bits of the
These 10 bits are added to the upper side of the bits and are taken out onto the external address bus AB as a 24-bit address. Internal data bus of bus BUS and external data bus D
A data buffer register 44 is connected to B.

Next, various operations of the present embodiment configured as described above will be described with reference to FIGS. 3 to 5 show the operation in the first mode, and FIGS. 6 to 8 show the operation in the second mode. The shaded areas in FIGS.
The process for the instruction code of the address a of FIG. Figure 3-
Instruction address, instruction fetch, operation,
Operand addresses and transfer operation types are selective depending on the instruction code. That is, in the case of a RAM access (transfer between RAM and register) instruction,
The instruction address, instruction fetch, operand address and transfer are valid, and in the case of the inter-register operation instruction, the instruction address, instruction fetch and operation are valid.

System clock edge times t1, t
The operation will be described in the order of 2, t3, .... For example, the description at t3 includes the description between t3 and t4. Generally, the fact that the content of the register X becomes the instruction code of the address a or the value related thereto is represented as X (a). Also, if the content of the program counter 13 becomes a, for example, PC = a
It is represented by.

[FIG. 3] When data is read from the internal RAM 11 (t1) PC = a. (T3) IR1 (a), PC = a + 1. The control circuit 24 controls the OFS 1 based on the output of the decoder 21.
(A) and IX1 (a). (T4) IR1A (a), and OFS1 (a)
And IX1 (a) are output from the adder / subtractor 31.

(T5) IR2 (a), IR1 (a +
1), PC = a + 2, OFS1 (a + 1), IX1 (a
+1). Internal RAM by the data length determination circuit 32
The access is determined, and the internal RAM 11 is addressed by the output of the address buffer register 33. (T6) IR1A (a + 1) and IR2A (a).
The content of the address a of the internal RAM 11 is read onto the internal data bus. OFS1 (a + 1) and IX1 (a +
The calculation result of 1) is output from the adder / subtractor 31.

(T7) IR2 (a + 1), IR1 (a +
2), PC = a + 3, OFS1 (a + 2), IX1 (a
+2). Internal RAM by the data length determination circuit 32
The access is determined, and the internal RAM 11 is addressed by the output of the address buffer register 33. The data on the internal data bus is held in the arithmetic circuit 12. [FIG. 4] Case of reading external RAM in the first mode (external RAM access time is one clock cycle) (t1 to t4) Same as the case of FIG.

(T5) IR2 (a), IR1 (a +
1), PC = a + 2, OFS1 (a + 1), IX1 (a
+1). External RAM by the data length determination circuit 32
The access is determined, and the decoder 22 determines that the access is read (external read). The 14-bit output of the address buffer register 33 is selected by the selector 43, and the upper 1 of the offset address register OFS2 is selected.
The 0 bit is selected by the selector 42.

(T6) The outputs of the selectors 42 and 43 become valid, and the address is fetched onto the external address bus AB. Based on the determination at t5, the content 1 of the wait cycle register 25 is loaded into the down counter 26,
The RS flip-flop 27 is set and the wait signal PWAIT becomes low level. OFS1 (a + 1) and I
The calculation result of X1 (a + 1) is output from the adder / subtractor 31.

(T7) Since the wait signal PWAIT is at the low level, the operation of the program counter 13 and the shift between the instruction registers IR1 to IR2A are stopped. The content of the address a of the external RAM 50 is the external data bus DB
Read on. (T8) The count value of the down counter 26 is decremented by 1 at the rising edge of the clock synchronized with the system clock, and the zero detection circuit 28 determines that this count value is 0, and the RS flip-flop 27 is reset. Rise time t
At 8, the wait signal PWAIT is at a low level and the above stop is maintained. The data on the external data bus DB is held in the data buffer register 44 and fetched on the internal data bus.

(T9-) The operation is the same as that after t7 in FIG. [FIG. 5] Case of external RAM writing in the first mode (external RAM access time is one clock cycle) (t1 to t4) Same as the case of FIG. (T5) The operation is the same as the operation at t5 in FIG. 4 except that the data length determination circuit 32 determines that the access is an external RAM and the decoder 22 determines that the access is a write (external write).

(T6) The outputs of the selectors 42 and 43 are enabled, the address is fetched on the external address bus AB, and at the same time, the contents of the data register R are fetched on the internal data bus, except at t6 in FIG. Is the same as the operation in. In the case of external RAM writing, unlike the case of external RAM reading, access wait time is unnecessary, so the wait signal PWAIT remains at high level.

(T7) The data on the internal data bus is held in the data buffer register 44, and the external data bus D
The operation is basically the same as that at t7 in FIG. 3 except that this data is fetched on B. [FIG. 6] In the case of external RAM read in the second mode (external RAM access time is one clock cycle) As described above, the external RAM read address has already been calculated by the adder / subtractor 41 in the previous step.

(T1) PC = a. (T3) IR1 (a), PC = a + 1. Based on the output of the decoder 21, the control circuit 24 determines that the external RAM is read (external read). (T4) IR1A (a) is obtained. Further, the outputs of the selectors 42 and 43 become valid, and the address is taken out onto the external address bus AB. (T5) IR2 (a), IR1 (a + 1), PC = a +
2, OFS1 (a + 1), IX1 (a + 1).

(T6) IR1A (a + 1), IR2A
(A). The data on the external data bus DB is held in the data buffer register 44 and fetched on the internal data bus. OFS1 (a + 1) and IX1 (a + 1)
The calculation results of and are output from the adder / subtractor 31. (From t7) The operation is the same as that after t7 in FIG.

Therefore, the read time from the external RAM 50 is the same as that from the internal RAM 11 (FIG. 3), which is 2 clock cycles shorter than the read time from the external RAM 50 in the first mode (FIG. 4). [FIG. 7] In the case of external RAM writing in the second mode (external RAM access time is one clock cycle) As in the case of FIG. 6, the external RAM read address has already been calculated by the adder / subtractor 41 in the previous step.

(T1) PC = a. (T3) IR1 (a), PC = a + 1. Based on the output of the decoder 21, the control circuit 24 determines that the external RAM write (external write). (T4) IR1A (a) is obtained. Selectors 42 and 43
Output is enabled, and the address is the external address bus AB
Taken out.

(T5) IR2 (a), IR1 (a +
1), PC = a + 2, OFS1 (a + 1), IX1 (a
+1). (T6) IR1A (a + 1) and IR2A (a).
Similar to the case of FIG. 3, the contents of the data register R are taken out onto the internal data bus from this time point t6. OFS
The operation result of 1 (a + 1) and IX1 (a + 1) is output from the adder / subtractor 31.

(From t7) The operation is the same as that after t7 in FIG. Therefore, the writing time to the external RAM 50 is
It will be the same as that in the first mode (FIG. 5). From this, it is preferable to perform the external RAM writing in the first mode because the software becomes simpler. [FIG. 8] In the case of external RAM read in the second mode (external RAM access time is 3 clock cycles) It is assumed that the instruction code at the address a + 1 is read from the internal RAM 11. This instruction code is the same as in the case of FIG.

(.About.t6) Same as the case of FIG. (T6 to t13) From t4 (3 clock cycles which is the external RAM access time)-(1 clock cycle)
After the lapse of 2 clock cycles, the wait signal PWAIT becomes low level for one clock cycle, and the processing for the instruction code after the address a + 2 is delayed by one clock cycle. That is, PC = a + 3 and IR
1 (a + 2), IR1A (a + 2), IR2 (a +
2), the change of IR2A (a + 2) is delayed by one clock cycle. Further, changes in the outputs of the adder / subtractor 31 and the address buffer register 33 for the instruction code of the address a + 1 are delayed by one clock cycle.

Since there is no delay in processing for the instruction code at address a + 1 and the processing for the instruction code at addresses a + 2 and later is delayed by one clock cycle, the contents on the internal data bus and the arithmetic circuit 12 are It is data relating to instruction codes in the order of a + 1, a, a + 2. (T13-) The same operation is performed after t11 (not shown) when the time axis of FIG. 3 is extended.

Therefore, the average read time from the external RAM 50 is shorter than the read time from the external RAM 50 in the first mode by 2 clock cycles. In the case of external RAM writing in the second mode, and
When the external RAM access time is 2 clock cycles or more, unlike the case of reading the external RAM, the access wait time is not necessary, and therefore the inside of the processor is the same as in the case of FIG. 7. From this, it is preferable to perform the external RAM writing in the first mode regardless of the external RAM access time because the software becomes simpler.

From the above, as for the RAM access instruction, by using the instruction of the first mode in the portion where there is no problem even in the low speed processing, the software is simplified, and the portion requiring the high speed processing is outside the second mode. It is preferable to use RAM read instructions.

[0042]

As described above, according to the processor according to the first aspect of the present invention, since the RAM access in both the first and second modes is possible, the external RAM access method can be selected according to the required processing speed. The effect is that it becomes possible to select. According to the program creating method of the second invention, the program is simplified by using the RAM access instruction of the first mode, which has the same format as the internal RAM access instruction, for the portion that does not require high-speed processing.
In addition, by using the external RAM read command in the second mode for the portion requiring high-speed processing, high-speed processing can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital signal processor according to an embodiment of the present invention.

FIG. 2A is a digital signal processor and an external R.
It is a connection diagram with AM, (B) is an effective address explanatory drawing in a 1st mode, (C) is an effective address explanatory drawing in a 2nd mode.

FIG. 3 is a timing chart for reading an internal RAM.

FIG. 4 is a timing chart of external RAM read in the first mode when the external RAM access time is one clock cycle.

FIG. 5 is a timing chart of external RAM writing in the first mode when the external RAM access time is one clock cycle.

FIG. 6 is a timing chart of external RAM read in the second mode when the external RAM access time is one clock cycle.

FIG. 7 is a timing chart of external RAM writing in the second mode when the external RAM access time is one clock cycle.

FIG. 8 is a timing chart of external RAM read in the second mode when the external RAM access time is 3 clock cycles.

[Explanation of symbols]

 10 Digital Signal Processor 11 Internal RAM 13 Program Counter 14 Program ROM 20 Control Unit 21-23 Decoder 24 Control Circuit 25 Wait Cycle Register 26 Down Counter 27 RS Flip Flop 28 Zero Detection Circuit 30 First Address Calculation Unit 31, 41 Adder / Subtractor 32 Data length determination circuit 33 Address buffer register 40 Second address calculator 42, 43 Selector 50 External RAM R Data register IR1, IR1A, IR2, IR2A Instruction register OFS1, OFS2 Offset address register IX1, IX2 Displacement register

Claims (2)

[Claims] 1. A program counter, a program memory in which a program is stored, an instruction code is read by being addressed by the contents of the program counter, an internal RAM for reading and writing data, and access to the internal RAM and external RAM. An effective address calculation unit for calculating an address, a data register for transferring data between the internal RAM and the external RAM, and a wait time in which the access time W of the external RAM is set by a program in units of system clock cycles. The cycle register and the instruction code read from the program memory are decoded, and based on the decoding result, the calculation result of the effective address calculation unit and the contents of the wait cycle register, the program counter and the effective address calculation unit. And the data register And a control unit for controlling the decoding operation of the instruction code and controlling the read / write operation with respect to the internal RAM and the external RAM. The instruction code of the first mode in which the read / write operation target is the internal RAM or the external RAM and the instruction code itself is an access to the external RAM according to the calculation result of the unit, and the instruction of the previous step of the instruction code Second code where external RAM access address is specified by code
And an instruction code of a mode, the controller decodes the instruction code as a first mode RAM read instruction, and the operation result of the effective address operation unit is within the address range of the external RAM. In some cases, by delaying the operation of the program counter and the operation of decoding the instruction code by the number W of system clock cycles set in the wait cycle register, the external RA
When the data read from M is held in the data register and the decoding result of the instruction code is the RAM read instruction in the second mode, and when the number of system clock cycles W set in the wait cycle register is 2 When the value W-2 obtained by subtracting is negative, the operation of the program counter and the operation of decoding the instruction code are delayed by the number of system clock cycles W-2, so that the data read from the external RAM is A processor characterized by being held in a data register. 2. The processor according to claim 1, wherein the RAM access instruction creates a program stored in the program memory by using the external RAM read instruction in the second mode, at least for a portion requiring high-speed processing. The method for creating a program is characterized by: