JP2721610B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller having a processor capable of pipeline processing.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, for the purpose of improving the processing speed of a programmable controller, a coprocessor dedicated to instruction execution which operates in parallel with a conventional general-purpose main processor 11 is used. It has been proposed to provide 21. Coprocessor 21
In order to speed up the processing, it has been considered to use a reduced instruction set processor (RISC processor). In this case, the source code of the sequence program designed by the user or the like and stored in the source program memory 12 is compiled and converted into a reduced instruction, and then stored in the object program memory 22. The processing is executed by the coprocessor 21 based on the object code including the reduction instruction stored in the memory 22. Compilation of the source code is performed by the main processor 11 using a compiler stored in the system memory 13. The main processor 11 is not used for executing the instructions of the sequence program, but is used for compiling the source code and for controlling peripheral devices and communication performed through the interface 14. Communication between the main processor 11 and the coprocessor 21 is performed via the bus controller 15. Here, the data bus of the main processor 11 has 16 bits, and the data bus of the coprocessor 21 has 32 bits with the object program memory 22 and 16 bits with the data memory 23. Bus controller 15
Has a function of connecting the 16-bit data bus of the main processor 11 and the 32-bit data bus of the coprocessor 21. The internal processing of the coprocessor 21 is 3
The instruction is executed in two bits, so that the instruction can be executed faster than the main processor 11 in combination with the RISC processor.

[0003] The relationship between the source code and the object code is as shown in FIG. For example, when the source code has three instructions and the number of words in each instruction is 2, 4, and 4, the number of words in the object code using the reduced instruction is, for example, 3 for each instruction in the source code. ,
7, 5, etc. In the object code, one word corresponds to one instruction. In the above example, one instruction using two words in the source code is three instructions in the object code.

[0004]

By the way, the instruction set of the coprocessor 21 is provided with what is called a differential instruction for detecting the rise or fall of the input. In general, the differential instruction is of a type that performs differential processing only for one scan, not for each scan. Now, it is assumed that the object program is as shown in FIG. Here, the differential instruction D that detects the rising of the input only once
F is used. When the input X0 rises from off to on, the output Y30 turns on. This process is performed only for one scan. To perform such processing, it is necessary to hold the value of the input X0 of the previous scan. That is, in order to execute the differential instruction DF in only one scan, once the input X0 rises from off to on, it is necessary to keep the input X0 on thereafter. By keeping it on after the next scan, the rise is not detected by the differential instruction DF. Thus, the input X0 is turned on.
In order to maintain the off state, it is considered to provide a data memory 23 having the same address as the object program memory 22 and each memory cell being 1 bit as shown in FIG. 5B.

For example, as shown in FIG. 5B corresponding to the ladder diagram of FIG. 5A, an instruction to take input X0 at address 0 of object program memory 22, and input X0 and data memory at address 1 It is assumed that an instruction for detecting the presence or absence of a rise by comparison with the value held in 23 and an instruction for outputting an output Y30 at address 2 are stored. When the instruction at address 0 is executed and the input X0 rises from off to on, at address 1, the data memory 23
Input X0 of the previous scan stored at address 1 of
(In the initial state, the input X0 is off.) And the input X0 obtained by executing the address 0 is detected to detect a rise, and an addition operation is performed. Thereafter, the output Y30 is obtained. Here, once the input X0 is turned on, since the address 1 of the data memory 23 is kept on thereafter,
Even if the input X0 fetched at the address 0 is on, the addition operation is not performed at the address 1.

On the other hand, as shown in FIG. 6, the execution speed of the coprocessor 21 is improved by performing pipeline processing. That is, when executing instructions in the coprocessor 21, an instruction fetch cycle IF for fetching instructions one by one from the object program memory 22, a decode cycle DEC for decoding fetched instructions, and an execution cycle EXE for executing decoded instructions Usually, it is necessary to reduce the execution time of the instruction by repeating the operation of fetching the next instruction during the decoding of one instruction. Here, instruction fetch cycle IF, decode cycle DEC, execution cycle EX
E is one machine cycle, and one machine cycle is defined, for example, for three cycles (six phases) of a clock signal.

The coprocessor 21 has a bit processing unit for executing a basic instruction which is a 1-bit instruction, and the bit processing unit has a bit accumulator which is an accumulator for holding 1-bit data to be subjected to arithmetic processing. If the input X0 fetched at the address (0) in the object program of FIG.
1 is stored in the bit accumulator. Next, when the differential instruction DF is fetched at the address (1), data at the same address in the data memory 23 is read at the same time. The data memory 23 stores the input X0 of the previous scan. For example, the input X0 is turned off (=
If "0"), the value of the data memory 23 is "0". In the execution cycle of the differential instruction DF, the value read from the data memory 23 is compared with the value of the bit accumulator. Here, if the value read from the data memory 23 is “0” and the value of the bit accumulator is “1”, the input X0 has risen, so that the condition is satisfied and the differentiation instruction DF is executed. , And the next instruction OTY30 is executed. Here, when the differential instruction DF is executed, the data memory 23
If "1" is written to the address (1), the rising edge of the input X0 is not detected after the next scan, and the rising edge of only one scan can be detected.

In the coprocessor 21, the address is incremented every machine cycle. When the address is (1), the instruction ST X0
Is decoded, and the differential instruction DF is fetched. Further, when the address becomes (2), execution of the instruction ST X0, decoding of the differential instruction FD, and fetching of the instruction OT Y30 are performed. Since the pipeline processing is performed as described above, the differential instruction DF is identified in the machine cycle whose address is (2).
Although data must be written to the address (1) of the data memory 23 in response to the differentiation instruction DF, the designated address has already been (2), and data cannot be written to the address (1). There is a problem. That is, if the pipeline processing is performed with the above-described memory configuration, there is a problem that the pulse-type application instruction cannot be processed.

In order to solve this problem, it is conceivable to separately manage the addresses of the object program memory 22 and the data memory 23. However, there is a problem that the management of the addresses becomes complicated and the hardware becomes complicated. is there. It is also considered that the execution of the differential instruction is transferred to the main processor 11.
The effect of improving the processing speed by half.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to simplify the address processing by sharing the addresses of the object program memory and the data memory, and to perform the pipeline processing without any inconvenience. It is intended to provide a programmable controller.

[0011]

According to the present invention, to achieve the above object, a program memory storing a sequence program, a data memory having 1-bit memory cells each having the same address as the program memory, and
An address generator that specifies the addresses of the program memory and the data memory; an instruction register that fetches the instruction stored at the address specified by the address generator from the program memory; and an instruction that decodes the instruction stored in the instruction register A decoder, an operation unit for executing the decoded instruction, and a controller for performing fetch, decoding, and execution of one instruction in order and performing pipeline control so as to fetch the next instruction from decoding to execution. In the programmable controller provided, when the instruction decoded by the instruction decoder is a differentiation instruction, the controller decrements the designated address by the address generator and interrupts the fetch of the next instruction to the instruction register to perform the differentiation instruction. Data Write to the data memory, then, it is to resume the fetch of the next instruction.

[0012]

According to the above configuration, in a configuration in which the program memory and the data memory share an address, when a differential instruction is identified during pipeline processing, the designated address is decremented. Since the fetch of the next instruction is interrupted and the data required for the differential instruction is written to the data memory, and then the fetch of the next instruction is resumed, the pipeline processing is temporarily interrupted during the execution of the differential instruction and the data memory is stopped. The required data can be written to the memory, and the processing can be performed only inside the coprocessor, while using simple hardware sharing the address between the program memory and the data memory. It becomes possible.

[0013]

FIG. 1 shows the structure of the main part of a coprocessor 21. Clock generator 31 generates a clock signal so as to synchronize internal circuits. The clock signal includes a normal synchronous clock sclk synchronized with the machine cycle.
A fetch clock fclk for giving a timing for fetching an instruction, a read clock rclk for setting a read timing for the object program memory 22 and the data memory 23, a write clock wclk for setting a write timing for the data memory 23, and a program to be described later. There is a rewrite clock cclk to the counter 41.

The instruction is read into the instruction register 32 in synchronization with the fetch clock fclk. At the same time that the next instruction is read into the instruction register 32, the previous instruction is input to the instruction decoder 33 and decoded. That is, one fetch clock fclk is generated for each machine cycle. When the instruction decoder 33 determines that the instruction is a differential instruction, a pulse is generated. This pulse is input to a controller 34 that controls the internal operation of the coprocessor 21 and is input to a counter 36 at the same time.
The counter 36 is enabled. Since the counter 36 counts the synchronous clock sclk in an operable state,
As a result, the output value of the counter 36 corresponds to the total number of differential instructions. The output of the counter 36 is input to the controller 34.

The controller 34 can read the value of the bit memory register 37 which takes in the value of the data memory 23, and sends and receives signals wb and rb to and from a bit accumulator (not shown). Data can be read and data can be written to the bit accumulator. Further, the controller 34 controls the clock generator 31 to output a fetch enable signal fe and a write enable signal we for controlling the output timing of the fetch clock fclk and the write clock wclk. The controller 34 also outputs an increase / decrease signal inde for selecting whether to increment or decrement the output value of the program counter 41.

The output value of the program counter 41 is stored in the object program memory 22 and the data memory 23.
The increment terminal 43 for incrementing the output value and the decrementer 44 for decrementing the output value are connected to the output terminal of the program counter 41. The outputs of the incrementer 43 and the decrementer 45 are output from a selector 42 which is a multiplexer.
, And the increase / decrease signal inde is input to the selector 42, thereby selecting whether to increment or decrement the output value of the program counter 41. That is, the designated address can be increased or decreased by increasing or decreasing the output value of the program counter 41.

The operation will be described below with reference to the case of executing the instruction shown in FIG. Here, for ease of explanation,
As shown in FIG. 2, numbers 1 to 7 are assigned to each machine cycle in order from the first cycle. The first cycle and the second cycle are the same as the conventional one. In the second cycle, since the address (1) is specified, the differential instruction DF is fetched, and the data of the address (1) in the data memory 23 is taken into the bit memory register 37. In the third cycle, the instruction STX0 is executed, and at the same time, the differential instruction DF is decoded. Here, the decoding of the differential instruction DF is performed in the first half of the third cycle. The counter 36 becomes operable by decoding the differential instruction DF, and the counter 36 counts the synchronous clock sclk. The controller 34 receives the output of the instruction decoder 33 and the output of the counter 36,
As shown in FIG. 2C, the increase / decrease signal falls from the increment to the decrement, and a request is made to decrement the output value of the program counter 41. FIG. 2 (e)
The fetch enable signal fe falls so as to inhibit the fetch of the instruction. At this time, the instruction ST
X0 is executed, and the input X0 is written to the bit accumulator by the write signal wb as shown in FIG.

In the third cycle, a request by the increase / decrease signal is issued to decrement the output value of the program counter 41. Therefore, in the fourth cycle, the address which is the output value of the program counter is (1) as shown in FIG. ). Here, since the fetch enable signal fe inhibits the fetch, the next instruction OTY30 is not fetched in the fourth cycle, and the differential instruction DF
Is performed only. At the start of the fourth cycle, the write enable signal we rises and the value stored in the bit accumulator (that is, the value of X0 in the current scan) is written to the data memory 23. In the fourth cycle, since there is no input from the instruction decoder 33 to the controller 34, the increase / decrease signal inde returns to the increment side.

At the fifth cycle, the output value of the program counter 41 is incremented to the address (2).
Is specified, the fetch enable signal fe rises in the second half of the fifth cycle, and the instruction OTY30 is fetched. Since the differential instruction DF is executed in the fifth cycle, the value of the bit accumulator is compared with the value stored in the bit memory register 37 in the second cycle, and the value stored in the bit memory register 37 is set to "0". If the value stored in the bit accumulator is 1, the rising condition is satisfied and the bit accumulator is set to "1". However, here, the bit accumulator is already "1". Thereafter, the control returns to the normal pipeline control. In the sixth cycle, writing to the memory is performed if the bit accumulator is “1”, but no operation is performed if the accumulator is “0”.

As described above, since the instruction execution processing is continued in the coprocessor 21 with the disturbance of the pipeline control being minimized, the address of the data memory 23 is shared with the object code memory 22. In combination with this, the hardware can be relatively simple and high-speed processing is possible.

[0021]

According to the present invention, as described above, in a configuration in which the program memory and the data memory share an address, when a differential instruction is identified during pipeline processing, a designated address is assigned. While decrementing, the fetch of the next instruction is interrupted, the data required for the differential instruction is written to the data memory, and then the fetch of the next instruction is resumed, so the pipeline processing is temporarily interrupted when the differential instruction is executed Required data can be written to the data memory, and the processing can be performed only inside the coprocessor while using simple hardware in which the address is shared between the program memory and the data memory. There is an effect that high-speed processing becomes possible.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an embodiment.

FIG. 2 is an operation explanatory diagram of the embodiment.

FIG. 3 is a block diagram of a programmable controller according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a relationship between a source code and an object code in the programmable controller according to the present invention.

5A is a diagram illustrating a part of an instruction represented by a ladder diagram, and FIG. 5B is an explanatory diagram illustrating a configuration of a memory.

FIG. 6 is an operation explanatory view showing a conventional operation.

[Explanation of symbols]

 31 clock generator 32 instruction register 33 instruction decoder 34 controller 41 program counter 42 selector 43 incrementer 44 decrementer

Claims (1)

(57) [Claims] 1. A program memory storing a sequence program, a data memory having 1-bit memory cells having the same address as the program memory, an address generator designating addresses of the program memory and the data memory, and an address An instruction register for fetching the instruction stored at the address specified by the generator from the program memory, an instruction decoder for decoding the instruction stored in the instruction register, an operation unit for executing the decoded instruction, A controller that sequentially fetches, decodes, and executes instructions and performs a pipeline control so that the next instruction is fetched between decoding and execution. Differentiation instruction , Decrement the designated address by the address generator, interrupt the fetch of the next instruction to the instruction register, write the data required for the differential instruction to the data memory, and then resume the fetch of the next instruction. Features a programmable controller.