JPH07210454A - High-speed processor - Google Patents

Abstract

PURPOSE:To reduce processing time for read access to a low speed I/0 device and a memory by installing a buffer circuit for looking-ahead read data and making the buffer circuit operate by a proper program. CONSTITUTION:At the time of receiving an instruction including the address of necessary data, a look-ahead control circuit 3a immediately fetches data into a look-ahead dedicated buffer 2. A bus master executes another processing and when data becomes necessary, executes normal read instruction. At the time of receiving the read instruction, the look-ahead control circuit 3a starts a normal read cycle and compares the object address with an address stored in the look-ahead control circuit 3a to stop the normal read cycle when they are equal to deliver data from the look-ahead dedicated buffer 2 to the bus master. Thereby, when the bus master reads data from the low speed device, the processing is not interrupted by the insertion of wait, so that processing speed is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed processing device, and more particularly to a high-speed processing device designed to reduce the processing time for read access. For example, it is possible to speed up a read cycle applied to a circuit using a low-speed I / O (Input / Output) device or a memory.

[0002]

2. Description of the Related Art In accessing a low-speed I / O device or memory, a read cycle without speed increasing means takes longer than a write cycle using a buffer to enable high speed. In other words, in the write cycle, write data is buffered by a device that can operate at high speed,
By delegating subsequent operations to the bus management circuit, CP can be used without directly accessing slow devices.
This is because a bus master such as U (Central Processing Unit) can end the cycle. However, in the read cycle, since the access is not completed until the operation of the slow device is completed, the access time depends on the operation speed of the slow device, and the series of operations cannot be shortened.

FIG. 4 is a block diagram of a conventional processing apparatus. In the figure, 11 is a CPU (Central Processing Unit), 12 is a memory controller, and 13 is a memory (low-speed memory). When the read command is executed in CPU 11 after the preprocessing is performed, the read command is transmitted to memory controller 12 via the address bus. In the memory controller 12, a memory address and a memory control signal are created, transmitted to the memory 13 via the memory address bus, data is output from the memory 13 and C is transmitted via the data bus.
Data is read by the PU 11. CPU11
When the post-processing is performed and the write command is executed, the write command is transmitted to the memory controller 12 via the address bus. In the memory controller 12,
A memory address bus and a memory control signal are created, and data is written in the memory 13.

FIG. 5 is a flow chart for explaining the operation of the processing apparatus shown in FIG. As can be seen from FIG. 5, the processing of the CPU 11 includes four modes of “preprocessing”, “data read”, “postprocessing”, and “data write”. Hereinafter, each mode will be described in order. Pre-processing : Pre-processing is performed in the CPU 11. Data read : When a read command is executed in the CPU 11, a memory address and a control signal are created in the memory controller 12, and the memory 13
At, data reading is performed. Data is read in the CPU 11.

Post-processing : Post-processing is performed in the CPU 11. Data write : When a write command is executed in the CPU 11, data is output, the memory controller 12 creates a memory address and a control signal and latches the data, and the memory 13 writes the data. Be done.

That is, after the "preprocessing" mode ends, C
The PU 11 executes the data read instruction, and the "data read" mode is started. Upon receiving the data read command, the memory controller 12 controls the low speed memory 13 corresponding to the address and reads the data. The CPU 11 receives this data directly from the low speed memory 13 via the data bus. Therefore, the CPU 11 cannot finish the "data read" mode until the data read from the low speed memory 13 is finished.

[0007]

As described above, in the conventional processing device, the I / O device and the main memory are slower than the operating speed of the bus master such as the CPU (central processing unit). It is possible to use a high-speed device for the main memory, but it is difficult to actually use it due to the problems of board space and cost. Therefore, the write buffer is used in the write cycle, which contributes to the improvement of the processing speed. However, there is a problem that there is no effective means for shortening the read cycle, which is a bottleneck in improving the processing speed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high-speed processing device capable of high-speed read access to a memory without using an expensive high-speed memory device. .

[0009]

In order to achieve the above object, the present invention provides a pre-reading unit provided in a processing unit for executing a read instruction and a memory controller operated by a command consisting of an address of required data. A control circuit and a pre-read-only buffer for fetching data from the memory corresponding to the address, wherein the memory controller compares the address with the pre-read data according to a data read command from the processing device, and the addresses are equal. Is characterized in that the read cycle of the memory is stopped and the data from the read-only buffer is supplied to the processing device.

[0010]

When the prefetch control circuit receives an instruction including the address of the required data, it immediately fetches the data into the prefetch dedicated buffer. After that, the bus master executes other processing, and executes a normal read instruction when data is needed. When the read-ahead control circuit receives the read command, it starts a normal read cycle, compares the target address with the address stored in the read-ahead control circuit, and if they are equal, stops the normal read cycle. , Pass data from the read-only buffer to the bus master. Therefore, when the bus master reads from a low-speed device, the wait is not inserted and the processing is not interrupted, and the processing speed can be improved.

[0011]

Embodiments will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a speed-up processing device according to the present invention, in which 1 is a CPU (Centra).
l Processing Unit: central processing unit), 2 is a read-only buffer, 3 is a memory controller, 3a is a read-ahead control circuit, and 4 is a memory (low-speed memory). In addition, CPU
The process of No. 1 consists of four modes of "pre-processing", "data read", "post-processing" and "data write".

Before starting the "pre-processing" mode, a command consisting of the address of the required data is written in the pre-reading control circuit 3a in the memory controller 3 in the "write-in pre-reading command" mode. The prefetch control circuit 3
When "a" receives "write-ahead command write", from the low-speed memory 4 corresponding to the address written in the command,
Data is loaded into the read-only buffer 2. CPU1
Starts the "preprocessing" immediately after the "writing of the prefetch command" to the prefetch control circuit 3a is completed. When the "data read" mode is started, the CPU 1 executes a data read instruction.

Upon receiving the data read command, the memory controller 3 starts controlling the low-speed memory 4 corresponding to the address, and reads the address from the prefetch control circuit 3a.
If it is equal, the read cycle to the low-speed memory 4 is stopped and the data is passed from the read-only buffer 2 to the CPU 1. Therefore, if the target data exists in the read-only buffer 2, the CPU 1 does not access the low-speed memory 4,
It can immediately receive the data and exit the "data read" mode.

In a high-speed processing apparatus for accessing a low-speed I / O device or memory, a pre-read control circuit for pre-reading data and a pre-read data dedicated buffer for storing pre-read data are provided, and a data read instruction is provided. When the memory controller receiving the low speed memory starts the low speed memory control corresponding to the address and the address is equal to the address stored in the prefetch control circuit, the read cycle of the low speed memory is stopped and the data from the prefetch dedicated buffer is transferred to the CPU. It is possible to shorten the processing time in read access by performing the operation of supplying to

2 and 3 are flow charts for explaining the operation of the high speed processing apparatus in FIG. C
The processing of PU1 is composed of four modes of "preprocessing", "data read", "postprocessing", and "data write".
Hereinafter, each mode will be described in order. Pre-processing : The pre-read command is written in the CPU 1 before the start of the pre-processing. When the preprocessing is started,
Preprocessing is performed in the CPU 1, memory addresses and control signals are created in the memory controller 3, data is output in the memory 4,
The data output from the memory 4 is latched in the memory controller 3.

Data read : When the CPU 1 executes a read command, the memory controller 3 creates a memory address and a control signal and compares the address with the preread data. If the pre-read data and the address are different, normal memory read is performed. If they are the same, access to the memory 4 is stopped and the latch data is output. CPU
At 1, data is read.

Post-processing : Post-processing is performed in the CPU 1. Data write : When a write command is executed in the CPU 1, data is output, a memory address and a controller signal are created in the memory controller 3, data is latched, and data is written in the memory 4.

Here, it is assumed that the CPU 1 takes 2 clocks (60 nsec) at an operating frequency of 30 MHz in one cycle and 800 nsec to access the low speed memory, and that the prefetch control circuit 3a and the prefetch dedicated buffer 2 can be accessed in a non-wait manner. Then, in the processing using the conventional circuit as shown in FIG. 5, the time required for one loop is expressed by the following expression (1). x + 800 + y + 60 (nsec) (1)

However, in the processing using the high speed processing apparatus according to the present invention as shown in FIGS. 2 and 3, when the processing time x is sufficiently long, the data transfer time from the low speed memory to the read-ahead dedicated buffer 2 is increased. Is absorbed at the pretreatment time x,
When viewed from the CPU 1, it is 0 nsec. Therefore 1
The time required for the loop is as shown in equation (2) below. 60 + x + 60 + y + 60 (nsec) (2) where x> 800 (nsec)

Thus, when the optimum operation is possible,
Regardless of the time required to access the low-speed memory, one CPU cycle (6
0 nsec) and 1 CPU cycle (60 nsec) for "reading from the read-only buffer", a total of 2 CPU cycles (120 nsec), data can be read from the low-speed memory.

[0021]

As is apparent from the above description, according to the present invention, in a high speed processing apparatus for accessing a low speed I / O device or memory, a prefetch control circuit for prefetching data, and a prefetch control circuit. A read-only buffer for storing data, a memory controller that receives a data read command starts low-speed memory control corresponding to an address, and if the address is equal to the address stored in the read-ahead control circuit, low-speed Stops the memory read cycle and loads the data from the read-only buffer to C
By enabling the operation of supplying to the PU, the processing time in read access can be shortened, so that it is not necessary to use an expensive high-speed memory device,
High-speed read access to the memory becomes possible. Also, I /
This is more effective for speeding up read access of low-speed devices such as O devices, and greatly improves the processing speed of the entire system.

[Brief description of drawings]

FIG. 1 is a configuration diagram for explaining an embodiment of a speed-up processing device according to the present invention.

FIG. 2 is a flowchart (No. 1) for explaining the operation of the speed-up processing device in FIG.

FIG. 3 is a flowchart (part 2) for explaining the operation of the speed-up processing device in FIG.

FIG. 4 is a block diagram of a conventional processing apparatus.

5 is a flowchart for explaining the operation of the processing device in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU (Central Processing Unit: Central processing unit), 2 ... Prefetch-only buffer, 3 ... Memory controller, 3a ... Prefetch control circuit, 4 ... Memory.

Claims (1)

[Claims] 1. A processor for executing a read instruction, a pre-read control circuit provided in a memory controller which operates by a command consisting of an address of required data, and a pre-read for fetching data from a memory corresponding to the address. The memory controller compares the address with the pre-read data in response to a data read command from the processing device. If the addresses are equal, the read cycle of the memory is stopped and the pre-read-only buffer is used. The data processing method described above is supplied to the processing device.