JPH0266629A - Data processing system - Google Patents

Abstract

PURPOSE:To improve the overall executing performance of a machine instruction by supplying the contents of an index register to a memory operand access process part and starting the memory operand access process to a store instruction in case the contents of the index register are not needed for the memory operand address calculation process. CONSTITUTION:It is decided whether the contents of an index register group 6 are required for the memory operand address calculation process or not. If not, the contents of an arithmetic register which are written into an MMU 11 with an ST instruction 3 under a memory address conversion process are not read out of an arithmetic register group included in an arithmetic execution process part 17 but out of the group 6. Then the contents of the arithmetic register are supplied to a memory operand access process part 16 via a store data line 9. Thus the memory operand access process can be started to the instruction 3 before the end of the arithmetic execution process applied to an instruction A set right before the instruction 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing method in a data processing apparatus that processes data by pipeline control, and particularly relates to store instruction processing.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of main parts of a data processing device for executing machine instruction processing in a conventional data processing system. In the figure, 11 is a main storage device in which programs and the like are stored, 12 is an instruction read processing unit that reads instructions from the main storage device 11, 13 is an instruction decode processing unit that decodes the read instructions, and 14 is the decoded instruction. A memory operand address calculation processing unit 15 calculates the operand address from the operand address.
1 is a memory address conversion processing unit that converts an address into a memory address; 16 is a memory operand access processing unit that accesses the main storage device 11 based on the memory address and reads data from the main storage device 11;
Reference numeral 7 denotes an arithmetic execution processing unit that executes an arithmetic operation using the read data.

FIG. 5 is a timing chart for explaining the above machine instruction processing. In the figure, 1 is a load instruction (hereinafter referred to as an instruction) that reads operand data from the main memory 11 and sets it in a register in a basic processing unit (not shown); 2 is a load instruction that reads operand data from the main memory 11 and performs basic processing. Addition instruction (hereinafter referred to as A instruction) that adds the contents of a register in the device and sets the result in a register in the basic processing device; 3 writes the contents of the register in the basic processing device to the main memory 11; This shows a store instruction (hereinafter referred to as ST instruction).

Next, the operation will be explained. Instruction 1 read from the MMU (main memory unit) 11 by the instruction read processing unit 12
are an instruction decode processing section 13, a memory operand address calculation processing section 14, and a memory address conversion processing section 1.
5 in order, each processing unit performs the processing described above, and the memory operand access processing unit 16
The data is read from the UII, and the calculation execution processing unit 17 selects M.
Set the data read from the MUII to the register in the BPU (basic processing unit). The A instruction 2 that follows the L instruction 1 performs the same processing as the L instruction 1 up to the memory operand processing unit 16 with a one-timing delay from the L instruction 1, and then reads it from the MMUII in the arithmetic execution processing unit 17. Add the data and the contents of the register in the BPU,
Set in the register in BPU. Following A command 2 <ST
The instruction 3 performs the same processing as the A instruction 2 until the memory address conversion processing unit 15 is delayed by one timing from the A instruction 2, and the arithmetic execution processing unit 17 reads the contents of the register in the BPU and performs memory operand access. Processing section 16
At this point, the arithmetic execution processing section 17 attempts to write the contents of the register read out to the MMUII, but at this time, the arithmetic execution processing section 17 is processing the A instruction 2.
Therefore, the processing subsequent to the arithmetic execution processing of ST instruction 3 is made to wait until this processing is completed before being processed.

At this time, the memory address translation processing section 15 is controlled not to accept the next processing until the processing by the memory operand access processing section 16 according to the ST instruction 2 can be started. The L instruction 1° following the sT instruction 3 performs memory operand address calculation processing one timing later than the ST instruction 3, but the memory address conversion processing unit 15 accepts or rejects the next processing due to the previous ST instruction 3. Since the memory address conversion process is controlled so that it does not occur, the memory address conversion process is made to wait for one timing, and the processes after the memory address conversion process are also delayed.
Processing is delayed.

[Problem to be solved by the invention]

In conventional data processing systems, for example, data to be written to the main memory during store instruction processing is obtained from the arithmetic execution processing unit, so store instruction processing is forced to wait until the machine instruction immediately before the store instruction is processed. There is a problem in that the machine instruction immediately after the store instruction is also executed with a delay, resulting in a decrease in the execution performance of the entire machine instruction.

This invention was made to solve the above-mentioned problems, and it writes data to the main storage device without waiting for the completion of the arithmetic execution process of the machine instruction immediately before the store instruction, and also writes the data immediately after the store instruction. An object of the present invention is to provide a data processing method that eliminates processing waiting for machine instructions, thereby improving the execution performance of the entire machine instructions.

[Means to solve the problem]

In the data processing method according to the present invention, the contents of an index register 16 for changing an operand address during execution of a machine instruction provided in a memory operand address calculation processing unit 14 are processed by memory operand address calculation processing. If it is determined that it is not necessary, the contents of the index register 6 are supplied to the memory operand access processing unit 16, and memory operand access processing for the store instruction is started. .

[Effect]

In this data processing method, if the contents of the index register 16 are not needed in the memory operand address calculation process, the contents are supplied to the memory operand access processing section 16, which performs memory operand access for the store instruction. Processing begins.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the main structure of a data processing device for executing machine instruction processing in a data processing system according to an embodiment of the present invention.

In FIG. 1, components corresponding to those shown in FIG. 4 are designated by the same reference numerals, and their explanations will be omitted. FIG. 2 is a timing chart for explaining the machine instruction processing described above, and components corresponding to those shown in FIG. 5 are given the same reference numerals.

FIG. 3 is a block diagram for explaining the hardware configuration of the memory operand address calculation processing section in this embodiment. In Figure 3, 4 is a relative memory address specified as part of the machine instruction word, 5 is a base register group that is part of the machine instruction word and is used to specify the base address, and 6 is a part of the machine instruction word. a group of index registers for specifying addresses for changing operand addresses in part; 7 is the relative address 4;
and an adder for adding the contents of the base register specified and read out from the base register group 5 by the machine instruction word and the contents of the index register specified and read out by the machine instruction word from the index register group 6; 8 is a memory address register for setting the output of the adder 7, and 9 is a store data line for supplying the contents read from the index register group 6 to the operand access processing section 16.

Next, the operation will be explained.

It is assumed that the contents of the registers of the base register group 5, the contents of the registers of the index register group 6, and the contents of the arithmetic register group in the arithmetic execution processing section 17 are controlled so that they are always equal. ing. L command 1. A
The same processing as the conventional one is performed from the instruction reading process of instruction 2 to the operation execution process. Also, following A command 2, <
The same processing as the conventional one is performed from instruction reading of ST instruction 3 to memory operand address calculation processing. At the timing of the memory address conversion process following the memory operand address calculation process, the memory operand address calculation process of the instruction 1', which is a machine instruction following the ST instruction 3, is being performed simultaneously. In this memory operand address calculation process, whether or not the contents of the base register group 5 and the index register group 6 are necessary is specified by specifying the machine instruction word.

It is determined whether the contents of the index register group 6 are necessary in the memory operand address calculation process of "L instruction 1", and if it is determined that the contents are not necessary, the ST instruction 3 during the memory address conversion process is determined. MMU (main memory unit)
The contents of the calculation register to be written to the calculation execution processing unit 1
The ST instruction 3 Memory operand access processing for ST instruction 3 can be started without waiting for the completion of the operation execution processing for A instruction 2 immediately before.

In the above embodiment, the index and address are calculated in the memory operand address calculation process of L instruction 1° following ST instruction 3.
Although we have explained the case where register group 6 is not used, S
If the instruction following T instruction 3 is not limited to the L instruction but does not use the index register group, the same effect as in the above embodiment can be achieved.

Also, in the above embodiment, ST instruction 3 was explained, but
A machine instruction that simply writes the contents of an arithmetic register in the basic processing unit to the main memory will produce the same effect as the above embodiment.

According to the above embodiment, when executing a machine instruction that writes the contents of an arithmetic register in the basic processing unit to the main memory, the contents of the arithmetic register are retrieved from the index register group in the memory operand address calculation processing section. Therefore, the contents of the arithmetic register for writing to the main memory can be retrieved without waiting for the completion of the arithmetic execution process of the machine instruction immediately before the store instruction, and the machine instruction can be executed at high speed.

〔Effect of the invention〕

As described above, according to the present invention, the contents of the index register of the memory operand address calculation section are
If the operand address calculation process determines that it is not necessary, the contents of the index register are stored in memory.
Since the data is supplied to the operand access processing section and starts the memory operand access processing for the store instruction, the data written to the main memory during store instruction processing is not obtained from the operation execution processing section, but from the memory. Obtained from the operand address calculation processing unit, this allows data to be written to the main memory without waiting for the completion of the arithmetic execution processing of the machine instruction immediately preceding the store instruction, and also enables processing for the machine instruction immediately following the store instruction. The effect is that there is no waiting, and therefore the overall execution performance of machine instructions is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main structure of a data processing device for executing machine instruction processing in a data processing system according to an embodiment of the present invention, and FIG. 2 explains machine instruction processing in this embodiment. 3 is a block diagram for explaining the hardware configuration of the memory operand address calculation processing section in this embodiment, and FIG. 4 is a timing chart for executing machine instruction processing in the conventional data processing method. FIG. 5 is a block diagram showing the configuration of main parts of the data processing device, and FIG. 5 is a timing chart for explaining machine instruction processing in this conventional example. 6... Index register group, 11...
. . . Main storage device, 12 . . . Instruction read processing section, 13 . . . Instruction decode processing section, 14 . .
...Memory operand address calculation processing unit, 15
...Memory address conversion processing unit, 16...
...Memory operand access processing unit, 17...
...Arithmetic execution processing unit. Agent Daikun Masuo (2 idiots) Ton] Brother No. 3 erasure 4th

Claims (1)

[Claims] In order to sequentially read machine instructions from the program memory area of the main memory and sequentially execute instructions based on the read instructions, there is an instruction read processing unit that reads the instructions from the main memory, and a An instruction decoding processing unit that decodes the instruction, a memory operand address calculation processing unit that calculates an operand address from the decoded instruction, a memory address conversion processing unit that converts the operand address into a memory address, and the memory・Memory operand that accesses the main memory based on the address and reads data from the main memory.
In a data processing device comprising an access processing unit and an operation execution processing unit that executes an operation using the read data, the memory operand address calculation processing unit is provided with a memory operand address calculation processing unit that changes an operand address during execution of a machine instruction. If the contents of the index register for the store instruction are determined to be unnecessary in the memory operand address calculation process, the contents of the index register are supplied to the memory operand access processing section, and the contents of the index register are - A data processing method characterized by starting operand access processing.