JPS5812052A - Information processor - Google Patents

Abstract

PURPOSE:To perform information processing in a high speed, by providing a firmware storage circuit storing a specific address in an information proessor. CONSTITUTION:A control table and a machine language program are stored in a main storage device 401 and a head address and a program start address of the table in the device 401 are stored in a firmware storage circuit (FS)410. An instruction controlling readout storage of the device 401 is stored in a microinstruction memory 404 and the instruction read out from the memory 404 is set to a register (CSDR)405. An instruction from the CSDR 405 is decoded at decoders 406 and 417 and outputs a signal controlling a main storage address register 407, a main storage data register 408, a main storage write register 409, an FS 410, selectors 414 and 443, a main storage control circuit 440 and an arithmetic logical operation circuit 416. To access the FS 410 with a microinstruction, the deficiency of performance due to repetitive readout of the same data from the main storage can be prevented, the effect of the firmware can be given and high speed processing can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to an information processing apparatus using a microgram control method.

A technique for directly microprogramming a part of a control program that controls a computer system to improve the performance of the system is well known as a firmware technique. However, when implementing firmware on a conventional information processing device, one job (
The same data on the main memory device is read out repeatedly while processing a unit of work (unit of work), which has the disadvantage that the effectiveness of the firmware is diminished.

This is it! This will be further explained using It. Assume now that the arrangement of data on the main memory is shown in FIG. ioo, 110, 120° 130 in FIG. 1 indicate tables, and entries 101, 1 in each table
11 and 102 indicate the start addresses of tables 110, 120, and 130, respectively. Now, as an example, data A,
12$t-, data B, moving to position 131 H1
Considering the case of implementation using T firmware, the microprogram performs the following processing. First, read the table 11 from the ET'7101t main memory.
Find the start address of 0, then find the end address of table 110! Jlli is read to obtain the start address of the table 120, and then entry 121 of the table 120 is taken out to obtain data At. Next, the entry 102 is read to find the start address of the table 130 and stored in the data At entry 131.

Here, while the computer system is processing one job, KFi repeats the processing of the microprogram described above many times, and each time, the table 110, 1
Processing to obtain the start addresses of 20 and 130 will be performed. As described above, when implementing firmware using a conventional information processing device, there is a drawback that when the same data is read, there is a large drop in performance due to K, and the effect of the firmware cannot be fully demonstrated.

An object of the present invention is to provide a high-speed information processing device that can prevent performance degradation due to reading the same data as described above and can fully utilize the effects of firmware.

For the above purpose, the present invention focuses on the fact that the start address of a table and the start address of a machine language program do not change during job execution, and uses high-speed firmware storage to store this information in an information processing device. A circuit was installed.

Thereby, by using the address in the firmware storage circuit in the information processing device instead of the table address in the main memory, it is possible to provide a high-speed information processing device that can fully utilize the firmware effect.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 shows an example of a microprogram in which a firmware storage circuit according to the present invention is added, and FIG. 4 shows an information processing apparatus according to the present invention.

In FIG. 4, a firmware storage circuit (FS) 410,
A decoder 417 decodes whether the microinstruction is a microinstruction that accesses the firmware storage circuit 410t.
, a storage circuit 410 and a main memory data register 40
According to the present invention, a selector 414 for selecting the output of 8 is provided in the new 9. However, in this explanation, the operation in a conventional information processing device to which the mosquito memory circuit 410 is not added will first be explained, and then the operation will be explained as follows. Now, the operation of the information processing apparatus according to the present invention will be explained. The case of deviation will also be explained with reference to the case shown in FIG. 1 where data At- in entry 121 is moved as data B to entry 131.

First, the firmware according to the present invention has self-memory power! The case where it is not added will be explained. In this case, there is no selector 414 and the output of register 408 is connected to the input of arithmetic logic circuit 416.

First, the microinstruction 201 is transferred to the microinstruction memory 404.
is read out through the signal line group 433 and set in the microinstruction data register (08DR) 405.

This microinstruction is decoded by decoder 4406 to generate control signals 440-444. Decoder 406
Fi, microinstruction f)K, control signals 440, 441, 4 when the instruction is to read the main memory 401t
43,444. In this case, the control signal 443 is added to the selector 415 and connected to the address field of the microinstruction to connect the good signal line group 427 to the signal line group 429.
control so that it is sent to The signal line group 427 has a value indicating the address of the table entry 101. The control signal 444 is added to the arithmetic logic circuit 416 and controls the signal line group 429 to be sent to the signal line group 430. The control signal 441 is added to the main memory address register (MAR) 407 and the data on the signal line group 430 (
address in this case)? Control is set to MAR. Further, the control signal 440 is transmitted to the main memory control circuit 40.
2, the contents of the main memory 401 at the address indicated by the MAR output signal line group 421 are sent to the main memory data register (MDR) 408 through the signal line group 422.
A control signal 446t- is generated for setting the .

As described above, the start address of the table 110 is set in the MDR, 408 by executing the microinstruction 201 shown in FIG. When the microinstruction 202 is decoded, signals 440 and 441 are output, the contents of the MDR 40g are set in the MAR 407 via the arithmetic logic circuit 416, and the start address of the table 120 is set in the MDR 408. Similarly, by executing the 1 microinstruction 203, data A is set in the MD 1408. Next, by executing the microinstruction 204, the signal 44
2 is output, data A is set in the main memory write register (MDW) 409, and the microinstruction 205
As in the case of the i micro instruction 201, the execution of
The address of the table 13G is set in the MDR 408. Next, when microinstruction 206 is executed, data A-! in MDW 40Q is executed in the same manner as microinstruction 202. It is stored in the data B position indicated by JXMAR407. When it is jin, control signal 44
0 is the main memory device 401 at the address indicated by the signal line group 421
The data of the signal line group 423, which is the output from the MDW 409, is stored in the %MDW 409.

The operation when the firmware storage circuit 410 of the present invention is not added has been described above.

Next, the operation of the information processing apparatus to which the firmware storage circuit 410 in FIG. 4 is added will be explained.

In the information processing apparatus of the present invention, the microprogram shown in FIG. 5 is executed only once by a firmware startup command during system startup operation (initialization). The firmware instruction is the ninth instruction that executes a microprogram that performs more sophisticated processing than the microb C1gram for processing ordinary machine language instructions.

First, the microinstruction 501 is transferred to the microinstruction memory 404.
is read from and executed. The operating position at this time is the same as 201 in FIG.
The address of the starting area "'111 is set in the MDR 408. 7 Next, the microinstruction 502 is executed, which is the same as 202 in FIG. At L/, l of 121 is set in the MDR 408. In the case of this microinstruction, the signal 449 is not output, and the selector 414 selects the MDR 408 08DR) 405. This microinstruction is decoded by the decoders 406 and 417VC. In this case, the control signal 449 is not output and the selector 414 sends the output signal line group 424 of the MDR 408 to the output line 428. Also, the control signal 444 is controlled to be sent to the signal line group 428t43G.Signal line 447
is added to the firmware storage circuit 410jC and indicates an address within the storage circuit 410. When the microinstruction is F8410f: access instruction, the decoder 417
It decodes it and outputs the address field within that microinstruction on line 447. In this case, the addresses are numbered to show 411. Control signal 448 #i indicates a write signal for the square storage circuit 410 and instructs to write to the signal line group 430 (in this case, data A) t entry 410. In this way, the address of area 121 of table 120 is set in entry 411 of memory circuit 410. Next, the microinstruction 504 is executed by the same operation as the microinstruction 205 in FIG.
MDili4osVc is set. Microinstruction 505 is then read and executed. This and I are control signals 4
47 is entry 41 in firmware storage circuit 410
2. This is the entry 41
1,412 stores the start addresses of the table 120 and the table 1300. Therefore, from now on, the tables 120 and 130 can be accessed by the microprogram shown in FIG.

First, the microinstruction 301 is transferred to the microinstruction memory 404.
microinstruction data register (C8
DR) 405. ? - microinstructions are decoded by decoders 406 and 417. A control signal 447 is applied to firmware storage circuit 410.

In this case, this signal is the address of entry 411. At this time, the entry 411 stores the start address of the table 120. Microinstruction 301 is F84
10, the signal 448 is not output, but the signal 449 is output. Therefore, the contents of entry 411 of F8410 are read to signal line group 425.

The control signal 449 is added to the selector 414 and the signal line group 4
25 to the signal line group 428. Control signal 444 is applied to arithmetic logic circuit 416 to route signal line group 428 to signal line group 430. control signal 4
41 is main memory address register (MAR) 4
07 and the contents of the signal line group 430 tMAR407
Set to . A control signal 440 is added to the main memory control circuit 402, and k, M are controlled by the same operation as described above.
The data person will be set in DR408. Microinstruction: The operation of 302 is the same as the microinstruction 204 described above.
When set in the dynamic clock instruction data register 405,
Control signals 440 to 448 perform the following control.

A control signal 447 is applied to the firmware storage circuit 410, indicated at 410, and instructs `J412''. At this time, the entry 412 stores the start address of the table 130. Control signals 449, 444
, 441 performs the same control as for microinstruction 301.

A control signal 440 is applied to the memory control circuit 402 to control the MDW 40 in the same manner as described for the microinstruction 206.
Data A in 9 will be stored in the position of data B indicated by MAR40B.

As explained above, according to this embodiment, what used to be processed in 6 steps by a conventional information processing device can now be processed in 6 steps.
Processing can be performed in three steps, which has the effect of allowing high-speed firmware processing.

The firmware storage circuit according to the present FIAK is different from a general-purpose register for the following reasons. That is, a field for indicating the address of a general-purpose register exists in a part of the machine language instruction in the main memory, whereas a field for indicating the address of the firmware storage circuit exists in the microinstruction.

In addition, while the work register holds intermediate results when executing each machine language instruction, the firmware storage circuit sets values at system startup, and when each of the seven firmware instructions is executed, the expected values are already stored. It differs from the work register in that it is set. However, the object of the present invention can also be achieved in an arithmetic processing device configured using the firmware storage circuit according to the present invention as part of a work register.

In this embodiment, an example has been described in which the memory address in the firmware storage circuit is directly addressed by a microinstruction. The object of the present invention can also be achieved.

As described above, according to the present invention, it is possible to provide a high-speed information processing device that can prevent performance deterioration due to reading the same data and can fully utilize the effects of firmware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of table arrangement in the main memory, FIG. 2 is a diagram showing an example of a microprogram by a conventional information processing device, and FIGS. Diagram 4 showing an example of a microprogram by a processing device
The figure is a diagram showing an information processing device according to the present invention. 410...firmware storage circuit, 447.0. Firmware storage circuit address control signal line, 425...
・Firmware storage circuit output signal line group, 448fJ
1 st/jσ ￥J2 concave leaf 3 figure

Claims (1)

[Claims] A main memory for storing control tables and machine language programs, an address register for specifying the address of the main memory, a register for storing data read from the main memory, and a main memory. A register for holding data to be stored in the device, a microinstruction storage device for storing a microprogram for controlling reading and storage from the main storage device, and a microinstruction storage device for specifying an address of the microinstruction storage device. an address register;
An information processing device having a register for holding a microinstruction read out from a microinstruction storage device, and means for generating a control signal tube from the microinstruction,
An information processing device characterized by comprising a memory circuit for storing a specific address in a main memory.