JPH01266642A - Memory controller - Google Patents

Abstract

PURPOSE:To start up the system in a short time without executing a CPU processing which takes time by executing the initialization of a memory as a hardware by a memory control circuit. CONSTITUTION:When a power source is turned on, a command is outputted to a memory control circuit 22 from a CPU 20, and an instruction for starting the initialization of a memory is given to a memory initialization control part 44 from a bus control part 34. The control part 44 generates memory initialization data, and simultaneously, allows an address counter part 42 to count up. Subsequently, by controlling a data switching part 32, these generated data and an output address are sent out to a memory access control part 30. As a result, in a memory 24, the generated data are written successively to the output address. When the initialization is executed, the control part 44 resets a count value of the counter part 42 to a value before the initialization and allows said counter part to count up again. Next, the data is read out of the address concerned, compared with write data by the control part 30, and a result of comparison of all the data is sent to the CPU 20. When it is confirmed to be normal, the CPU 20 loads a program and starts up an OS.

Description

[Detailed Description of the Invention] [Table of Contents Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Overview Memory Control for Controlling Memory Access] Regarding equipment,
In particular, we aim to provide a memory control circuit that can reduce the time required to initialize memory at system startup, especially for memory control devices that perform data checks during memory access. a generating means, a data writing means for writing the generated data into the memory, a write address specifying means for specifying a write address of the generated data,
and a write start instruction means for instructing the start of writing of generated data at the time of system startup.

[Industrial Application Field] The present invention relates to a memory control circuit that performs memory access control, and particularly to a memory control circuit that performs a data check during memory access.

In a computer system in which a data check is performed during memory access using an FCC circuit, a parity check circuit, etc., it is necessary to initialize the additional bits of the FCC check pit and parity check bit when starting up the system.

[Prior Art] The configuration of a computer system is explained in FIG. 12, and this system includes a CPU 20. Memory control circuit 22. Memory 24. It is composed of an I10 interface 26.

The memory access of the CPU 20 is performed by the memory control circuit 2.
The FCC check and parity check are performed by the memory control circuit 22.

Here, at the time of system startup, Fig. 13 (A)
, (B), the CPU 20 writes data to the memory 24, and as a result, the data is written to the memory 24.
is initialized.

At that time, predetermined data are written to all addresses in the memory 24, and the FCC check bits and parity check bits thereof are set to normal values.

[Problems to be Solved by the Invention] However, in the past, the memory 24 was initialized by the CPU 20, and this initialization required processing such as fetching instructions, calculating access addresses, and setting up addresses. Therefore, in a system in which a large capacity memory 24 is used, there is a problem in that it takes a long time to start up the system.

The present invention has been made in view of the above-mentioned conventional problems,
The purpose is to provide a memory control circuit that allows the system to be started up in a short time.

[Means for Solving the Problems] In order to achieve the above object, a circuit according to the present invention is configured as shown in FIG.

The initialization data generation means IO in the figure generates data for memory initialization, and the generated data is written to the memory by the memory writing means 12.

The write address of the generated data is specified by the write address designation means 14, and the start of writing of the generated data is instructed by the write start instruction means 16 at the time of system startup.

[Operations] In the present invention, the memory is initialized by the memory control circuit when the system is started up.

[Embodiments] Hereinafter, preferred embodiments of the circuit according to the present invention will be described based on the drawings.

In FIG. 2, the memory 24 is the memory access control unit 3.
0, and the memory access control unit 3
0 is the data switching unit 32. Address bus 36 . It is connected to a data bus 38 and a control line 40.

Further, an address counter section 42 and a memory initialization control section 44 are connected to the data switching section 32, and the address counter section 42 is controlled by the memory initialization control section 44.

FIG. 3 shows a flowchart for explaining the general operation of this embodiment. When the system is powered on, the CPU 20 sends the memory 2 to the memory control circuit 22 of this embodiment.
4 initialization start is commanded.

As a result, the memory initialization control unit 44 is transferred from the bus control unit 34 to the memory initialization control unit 44.
An instruction to start memory initialization is given to the memory 24, and the memory 24 is initialized.

Therefore, data for memory initialization is generated by the memory initialization control section 44, and the address counter section 42 is successively counted up by the memory initialization control section 44.

Then, the data switching unit 32 is controlled by the memory initialization control unit 44.
is switched, and the data generated by the memory initialization control unit 44 is transferred to the memory access control unit 30 via the data switching unit 32.
given to.

Further, the output address of the address counter section 42 due to the count-up is also given to the memory access control section 30 via the data switching section 32.

As a result, the data generated by the memory initialization control section 44 is written to the output address of the address counter section 42 as shown in FIG. 4(B), and during that time, writing by the CPU 20 is performed as shown in FIG. Never.

Therefore, instruction fetch, access address calculation,
Address set-up and the like are not performed on the CPU 20 side, and the CPU 20 can perform r10 check processing in parallel as shown in FIG. 3 during this time.

When the memory 24 is initialized as described above,
The address counter unit 42 is controlled by the memory initialization control unit 44.
The count value of is reset to the value before memory initialization,
The count-up starts again.

This causes the data to be transferred from the corresponding address in the memory 24 to the fifth
The data is read out as shown in FIG. 3B, and the write data and the read data are compared by the memory access control unit 30 (data check).

The comparison results are sequentially given to the memory initialization control unit 44, and when normal comparison results are obtained for all addresses or when an abnormal comparison result is obtained for any address, the memory initialization control unit 44 The unit 44 sends data indicating the result of the memory check to the CPU 20 via the bus control unit 34 (completion notification).

That is, the CPU 20 does not perform the memory check process shown in FIGS.
As shown in A) and (B), the memory check is performed on the memory control circuit 22 side.

After that, C confirmed that a normal memory check result was obtained.
When confirmed by the PU 20, an initial program load is performed as shown in FIG. 3, and the operating system is started.

As explained above, according to this embodiment, the initialization of the memory 24 is not performed by the CPU 20, but is instead performed by the memory control circuit 22, so that command fetches, access address calculations, address set-up, etc. This time-consuming CPU processing is not performed, and similar processing is performed by hardware in the memory control circuit 22.

Therefore, the initialization of the memory 24 can be completed in a short time, and as a result, the system can be used immediately.

Further, according to this embodiment, the memory check is performed by the memory control circuit 22 instead of the CPU 20, so that the time required to start up the system can be further reduced.

Since the CPU 20 performs the I10 check while the memory is being initialized and checked, it is possible to further reduce the time required to start up the system.

Incidentally, it has been confirmed that the time required to start up the system can be reduced by more than half.

In addition, when DRAM is used as the memory 24, the DRAM is used in the normal mode shown in FIGS. 7(A) and (B) as well as in the normal mode shown in FIGS. 8(A) and (B). Since memory access operations can be performed continuously by nibble operation, the memory 24 can be initialized quickly by the memory control circuit 22 by using this nibble mode as shown in FIGS. 9(A) and 9(B).

Figure 9(A) also uses its nibble mode.

It is also possible to perform a memory check at high speed by the memory control circuit 22 as shown in (B).

Incidentally, a computer system equipped with a memory check function is also provided with a battleroll function that reads memory and returns the read data eleven times, regardless of task processing.

If this function is provided as hardware in the memory control circuit 22, that circuit can be used for the above-mentioned memory initialization and memory check.

FIG. 11 shows the configuration of a second embodiment that utilizes this patrol function, and memory patrol is performed by a patrol counter section 46 and a patrol control section 48.

Since the patrol function is not required during memory initialization and memory check, the patrol counter section 46 is controlled by the memory initialization control section 44 in place of the patrol control section 4, and therefore the patrol counter section 46 is controlled during the first execution. It is used as the address counter section 42 in the example.

Therefore, it is not necessary to add a new counter for memory initialization or memory check, and it is therefore possible to suppress an increase in the number of parts.

[Effects of the Invention] As described above, according to the present invention, since the memory is initialized by hardware, it is possible to shorten the time required for initialization and quickly start up the computer system.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the invention, Fig. 2 is an explanatory diagram of the configuration of the first embodiment, Fig. 3 is a schematic explanatory diagram of the operation of the first embodiment, and Fig. 4 is a memory initialization operation of the first embodiment. 5 is an explanatory diagram of the memory check operation of the first embodiment, FIG. 6 is an explanatory diagram of the memory check operation by the CPU, FIG. 7 is an explanatory diagram of the normal access operation of the DRAM, and FIG. 8 is an explanatory diagram of the DRAM nibble. FIG. 9 is an explanatory diagram of a high-speed memory initialization operation; FIG. 10 is an explanatory diagram of a high-speed memory check operation; FIG. 11 is an explanatory diagram of the configuration of the second embodiment; FIG. 12 is an explanatory diagram of a computer system. Configuration explanatory diagram, 13th
FIG. 1 is an explanatory diagram of the prior art. 206・φc p u. 22... Memory control circuit, 24... Memory, 30... Memory access control section, 32... Data switching section, 34... Bus control section, 42... Address counter section, 44...・Memory initialization side phloem, 46...Patrol counter g block 48...Patrol control unit.

Claims (1)

[Claims] Initialization data generation means (10) for generating data for memory initialization; data writing means (12) for writing the generated data into the memory; and designating a write address for the generated data. A memory control circuit comprising: a write address specifying means (14); and a write start instructing means (16) for instructing the start of writing of generated data at the time of system startup.