JPH0962568A - Data transfer control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate unnecessary execution machine times especially in the case that transfer data starts with word 0 in a block of a register file with respect to the instruction which transfers data having arbitrary transfer length to a storage area. SOLUTION: A transfer word address generation circuit 12 generates the word address of a register file 20 in accordance with the output of a length register 11 which receives the transfer length. A word 0 discrimination circuit 14 discriminates whether transfer data starts with word 0 in a block of the register file 20 or not by the generated word address; and if it starts with word 0, preliminarily taken-out data in word 0 is transferred. If it doesn't start with word 0, a suppression circuit 17 suppresses data transfer for the first machine time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control circuit for controlling data transfer to a storage area, and more particularly to a data transfer control circuit for a main memory in an information processing device.

[0002]

2. Description of the Related Art A conventional data transfer control circuit of this type is
When the contents of the register file in the arithmetic unit are transferred to the storage area over multiple words under the condition that they are in the same block, the word address of the register file for the transfer data is the block of the register file in the micro instruction. Only the boundary is specified, and the word address within the block boundary is generated from the transfer length.

The generation of a word address within a block boundary from a transfer length will be described below by using an example. Here, it is assumed that one block is composed of 8 words and the transfer length is represented by 8-bit data. The word is 0
It shall be represented by the origin. (Example 1) Microinstruction 1: Transfers consecutive words for a specified transfer length from the first word in a block to the storage area in the block, left-justified to the left.

In this case, the transfer length is represented by 3 bits out of 8 bits, [000] indicates 1 word transfer, and the word address is [000] as it is.

8-word transfer is indicated by [111], and the word address is counted up from [000] to [111]. (Example 2) Microinstruction 2: Transfers consecutive words of the specified transfer length over the last word in a block to the storage area in the block, right-justified.

In this case, the transfer length is represented by 3 bits out of 8 bits, [000] indicates one word transfer, and the word address becomes [111] by inverting this value.

[111] indicates 8-word transfer, and the word address is inverted from [000] to [111].
Count up to. (Example 3) Microinstruction 3: Transfers scattered word data in a block to a storage area.

In this case, the transfer length is represented by 8 bits.
The word corresponding to the bit that is 1 "is transferred.

In the case of [01010011], word 1,
Four words, word 3, word 6, and word 7, are sequentially transferred to the storage area.

In this way, the contents of the register file are
Execution of a microinstruction for transferring to a storage area over an arbitrary plurality of words requires an extra 1T execution time in order to extract the transfer length information registered in advance together with the execution of the microinstruction and generate a word address. .

[0011]

In the above-mentioned conventional data transfer control circuit, since the word address in the block of the transfer data is generated from the arbitrary transfer length, the designation of the micro instruction is 0 in the block of the register file. Even when the transfer data for the word indicated by the transfer length is taken out from the word, since the transfer length information is taken out to generate the word address of the register file, there is a problem that an extra 1T execution time is required.

[0012]

According to the circuit of the present invention, a micro-instruction is provided in a data transfer control circuit for extracting data of an arbitrary length in one block data from a register file in an arithmetic unit and continuously sending it to a storage area. From the output of the transfer word address generation circuit, which generates a word address of the register file from the contents of the length register and the type of the microinstruction. A word determination circuit that determines whether or not an address in a block of the register file is a predetermined word, a data transfer instruction generation circuit that generates a data transfer instruction from a microinstruction to a storage area, and an output of the word determination circuit Indicates a word other than the specified word, the first machine tie Characterized in that it only has a suppression circuit for suppressing the data transfer instruction between.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The data transfer control circuit 10 of the present invention includes a length register 11 for receiving transfer length information designated by a micro instruction, and a transfer word address generation for generating a word address of a register file 20 from the content of the length register 11 and the type of micro instruction. From the output of the circuit 12, the transfer word address register 15 receiving the output of the transfer word address generation circuit 12, and the output of the transfer word address generation circuit 12, the in-block address of the register file 20 is 0.
0-word determination circuit 1 for determining whether or not to start from a word
4, a data transfer instruction generation circuit 13 that generates a data transfer instruction from the micro instruction to the storage area, a data transfer instruction register 16 that receives the output of the data transfer instruction generation circuit 13, and an output of the 0-word determination circuit 14. The transfer instruction register 16 includes an inhibiting circuit 17 capable of inhibiting the output.

When a microinstruction for data transfer of an arbitrary transfer length to the storage area is issued, a data transfer instruction is generated by the data transfer instruction generation circuit 13 and set in the data transfer instruction register 16. The microinstruction also refers to the transfer length information register group 30 to take out the transfer length information registered in advance,
Set to. The output of the length register 11 is used by the transfer word address generation circuit 12 to generate the transfer word address until there are no more transfer words. The output of the transfer word address generation circuit 12 is input to the transfer word address register 15. The transfer word address register 15 always indicates 0 word in the block of the register file 20 unless there is an input from the transfer word address generating circuit 12.

On the other hand, the output of the transfer word address generation circuit 12 is also input to the 0 word determination circuit 14, and when the transfer data is fetched from other than 0 word in the block of the register file 20, the first 1T inhibition is performed. A signal is output, and the inhibition circuit 17 inhibits the data transfer instruction.

When the fetch address of the transfer data starts from 0 word in the block of the register file 20, the inhibition signal is not issued in the 0 word determination circuit 14, and the contents of 0 word of the register file 20 fetched in advance are stored. It is transferred to the storage area. When the transfer word address starts from 0 word, the transfer word address generation circuit 12 inputs the transfer word to the transfer word address register 15 until there are no transfer words from the second word address, and then the register file 2
The word address of 0 is the transfer word address register 15
Is determined by the output of.

On the other hand, the fetch address of the transfer data is 0 in the block of the register file 20.
When starting from a word other than a word, the inhibition signal is issued for 1T in the 0-word determination circuit 14, and the transfer word address generation circuit 12 is transferred to the transfer word address register 15 during this time.
The word address generated in step 1 is input, and thereafter, the transfer data is fetched from the register file 20 by the output of the transfer word address register 15.

[0019]

As described above, according to the present invention, in an instruction for transferring data of an arbitrary transfer length to a storage area, particularly when the address in the block of the register file which is the transfer data starts from 0 word, By transferring 0-word data fetched in advance and transferring the word address data generated from the transfer length from the 2T onward, waste of the number of execution Ts required to generate the transfer word address from the transfer length Has the effect of eliminating.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 10 data transfer control circuit 11 length register 12 transfer word address generation circuit 13 data transfer instruction generation circuit 14 0 word determination circuit 15 transfer word address register 16 data transfer instruction register 17 inhibit circuit 20 register file 30 transfer length information register group.

Claims (2)

[Claims] 1. A length for receiving transfer length information designated by a microinstruction in a data transfer control circuit for extracting data of an arbitrary length in one block of data from a register file in an arithmetic unit and continuously sending the data to a storage area. A register, a transfer word address generation circuit that generates a word address of the register file based on the contents of the length register and the type of the microinstruction, and an in-block address of the register file is determined from the output of the transfer word address generation circuit. A word determination circuit for determining whether or not it is a word, a data transfer instruction generation circuit for generating a data transfer instruction from a microinstruction to a storage area, and an output of the word determination circuit indicates other than the predetermined word. At this time, the data transfer instruction is given only during the first one machine time. The data transfer control circuit, characterized in that it comprises a suppression circuit for stopping. 2. The data transfer control circuit according to claim 1, wherein the predetermined word is 0 word of the register file.